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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160614-2' into staging

Browse Source 
target-arm queue:
 * add PMU support for virt machine under KVM
 * fix reset and migration of TTBCR(S)
 * add virt-2.7 machine type
 * QOMify various ARM devices
 * implement xilinx DisplayPort device
 * don't permit ARMv8-only Neon insns to work on ARMv7

# gpg: Signature made Tue 14 Jun 2016 16:01:45 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160614-2: (30 commits)
  target-arm: Don't permit ARMv8-only Neon insns on ARMv7
  arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdma
  introduce xlnx-dp
  introduce xlnx-dpdma
  hw/i2c-ddc.c: Implement DDC I2C slave
  introduce dpcd module
  introduce aux-bus
  i2c: Factor our send() and recv() common logic
  i2c: implement broadcast write
  i2cbus: remove unused dev field
  hw/sd: QOM'ify pl181.c
  hw/dma: QOM'ify pxa2xx_dma.c
  hw/misc: QOM'ify mst_fpga.c
  hw/misc: QOM'ify exynos4210_pmu.c
  hw/misc: QOM'ify arm_l2x0.c
  hw/gpio: QOM'ify zaurus.c
  hw/gpio: QOM'ify pl061.c
  hw/gpio: QOM'ify omap_gpio.c
  hw/i2c: QOM'ify versatile_i2c.c
  hw/i2c: QOM'ify omap_i2c.c
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2016-06-14 16:04:25 +01:00
parent 7474f1be70 fe8fcf3d64
commit 1be08a0946
40 changed files with 3835 additions and 228 deletions
Download Patch File Download Diff File Expand all files Collapse all files
default-configs/aarch64-softmmu.mak
+3
View File
@@ -3,4 +3,7 @@
# We support all the 32 bit boards so need all their config
include arm-softmmu.mak
CONFIG_AUX=y
CONFIG_DDC=y
CONFIG_DPCD=y
CONFIG_XLNX_ZYNQMP=y
hw/arm/virt-acpi-build.c
+4
View File
@@ -538,6 +538,10 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
gicc->arm_mpidr = armcpu->mp_affinity;
gicc->uid = i;
gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
if (armcpu->has_pmu) {
gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
}
}
if (guest_info->gic_version == 3) {
hw/arm/virt.c
+84 -17
View File
@@ -42,6 +42,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "hw/boards.h"
#include "hw/compat.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
#include "qemu/bitops.h"
@@ -98,6 +99,36 @@ typedef struct {
#define VIRT_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
virt_machine_##major##_##minor##_options(mc); \
mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
if (latest) { \
mc->alias = "virt"; \
} \
} \
static const TypeInfo machvirt_##major##_##minor##_info = { \
.name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
.parent = TYPE_VIRT_MACHINE, \
.instance_init = virt_##major##_##minor##_instance_init, \
.class_init = virt_##major##_##minor##_class_init, \
}; \
static void machvirt_machine_##major##_##minor##_init(void) \
{ \
type_register_static(&machvirt_##major##_##minor##_info); \
} \
type_init(machvirt_machine_##major##_##minor##_init);
#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
#define DEFINE_VIRT_MACHINE(major, minor) \
DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
/* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
* RAM can go up to the 256GB mark, leaving 256GB of the physical
* address space unallocated and free for future use between 256G and 512G.
@@ -436,6 +467,37 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
}
static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
{
CPUState *cpu;
ARMCPU *armcpu;
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
CPU_FOREACH(cpu) {
armcpu = ARM_CPU(cpu);
if (!armcpu->has_pmu ||
!kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
return;
}
}
if (gictype == 2) {
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
GIC_FDT_IRQ_PPI_CPU_WIDTH,
(1 << vbi->smp_cpus) - 1);
}
armcpu = ARM_CPU(qemu_get_cpu(0));
qemu_fdt_add_subnode(vbi->fdt, "/pmu");
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
const char compat[] = "arm,armv8-pmuv3";
qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible",
compat, sizeof(compat));
qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts",
GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
}
}
static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
{
int i;
@@ -1259,6 +1321,8 @@ static void machvirt_init(MachineState *machine)
create_gic(vbi, pic, gic_version, vms->secure);
fdt_add_pmu_nodes(vbi, gic_version);
create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]);
if (vms->secure) {
@@ -1387,7 +1451,13 @@ static const TypeInfo virt_machine_info = {
.class_init = virt_machine_class_init,
};
static void virt_2_6_instance_init(Object *obj)
static void machvirt_machine_init(void)
{
type_register_static(&virt_machine_info);
}
type_init(machvirt_machine_init);
static void virt_2_7_instance_init(Object *obj)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1420,25 +1490,22 @@ static void virt_2_6_instance_init(Object *obj)
"Valid values are 2, 3 and host", NULL);
}
static void virt_2_6_class_init(ObjectClass *oc, void *data)
static void virt_machine_2_7_options(MachineClass *mc)
{
MachineClass *mc = MACHINE_CLASS(oc);
}
DEFINE_VIRT_MACHINE_AS_LATEST(2, 7)
mc->desc = "QEMU 2.6 ARM Virtual Machine";
mc->alias = "virt";
#define VIRT_COMPAT_2_6 \
HW_COMPAT_2_6
static void virt_2_6_instance_init(Object *obj)
{
virt_2_7_instance_init(obj);
}
static const TypeInfo machvirt_info = {
.name = MACHINE_TYPE_NAME("virt-2.6"),
.parent = TYPE_VIRT_MACHINE,
.instance_init = virt_2_6_instance_init,
.class_init = virt_2_6_class_init,
};
static void machvirt_machine_init(void)
static void virt_machine_2_6_options(MachineClass *mc)
{
type_register_static(&virt_machine_info);
type_register_static(&machvirt_info);
virt_machine_2_7_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
}
type_init(machvirt_machine_init);
DEFINE_VIRT_MACHINE(2, 6)
hw/arm/xlnx-zynqmp.c
+31 -1
View File
@@ -38,6 +38,12 @@
#define SATA_ADDR 0xFD0C0000
#define SATA_NUM_PORTS 2
#define DP_ADDR 0xfd4a0000
#define DP_IRQ 113
#define DPDMA_ADDR 0xfd4c0000
#define DPDMA_IRQ 116
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -165,6 +171,12 @@ static void xlnx_zynqmp_init(Object *obj)
TYPE_XILINX_SPIPS);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
}
object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -388,8 +400,26 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
object_property_add_alias(OBJECT(s), bus_name,
OBJECT(&s->spi[i]), "spi0",
&error_abort);
g_free(bus_name);
g_free(bus_name);
}
object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
}
static Property xlnx_zynqmp_props[] = {
hw/display/Makefile.objs
+2
View File
@@ -43,3 +43,5 @@ virtio-gpu.o-cflags := $(VIRGL_CFLAGS)
virtio-gpu.o-libs += $(VIRGL_LIBS)
virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS)
virtio-gpu-3d.o-libs += $(VIRGL_LIBS)
obj-$(CONFIG_DPCD) += dpcd.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dp.o
hw/display/dpcd.c
+173
View File
@@ -0,0 +1,173 @@
/*
* dpcd.c
*
* Copyright (C) 2015 : GreenSocs Ltd
* http://www.greensocs.com/ , email: info@greensocs.com
*
* Developed by :
* Frederic Konrad <fred.konrad@greensocs.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option)any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
/*
* This is a simple AUX slave which emulates a connected screen.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/misc/aux.h"
#include "hw/display/dpcd.h"
#ifndef DEBUG_DPCD
#define DEBUG_DPCD 0
#endif
#define DPRINTF(fmt, ...) do { \
if (DEBUG_DPCD) { \
qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
} \
} while (0);
#define DPCD_READABLE_AREA 0x600
struct DPCDState {
/*< private >*/
AUXSlave parent_obj;
/*< public >*/
/*
* The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
*/
uint8_t dpcd_info[DPCD_READABLE_AREA];
MemoryRegion iomem;
};
static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
{
uint8_t ret;
DPCDState *e = DPCD(opaque);
if (offset < DPCD_READABLE_AREA) {
ret = e->dpcd_info[offset];
} else {
qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
offset);
ret = 0;
}
DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset);
return ret;
}
static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
DPCDState *e = DPCD(opaque);
DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset);
if (offset < DPCD_READABLE_AREA) {
e->dpcd_info[offset] = value;
} else {
qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
offset);
}
}
static const MemoryRegionOps aux_ops = {
.read = dpcd_read,
.write = dpcd_write,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static void dpcd_reset(DeviceState *dev)
{
DPCDState *s = DPCD(dev);
memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
s->dpcd_info[DPCD_REVISION] = DPCD_REV_1_0;
s->dpcd_info[DPCD_MAX_LINK_RATE] = DPCD_5_4GBPS;
s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES;
s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_0] = DPCD_EDID_PRESENT;
/* buffer size */
s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF;
s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE
| DPCD_LANE0_CHANNEL_EQ_DONE
| DPCD_LANE0_SYMBOL_LOCKED
| DPCD_LANE1_CR_DONE
| DPCD_LANE1_CHANNEL_EQ_DONE
| DPCD_LANE1_SYMBOL_LOCKED;
s->dpcd_info[DPCD_LANE2_3_STATUS] = DPCD_LANE2_CR_DONE
| DPCD_LANE2_CHANNEL_EQ_DONE
| DPCD_LANE2_SYMBOL_LOCKED
| DPCD_LANE3_CR_DONE
| DPCD_LANE3_CHANNEL_EQ_DONE
| DPCD_LANE3_SYMBOL_LOCKED;
s->dpcd_info[DPCD_LANE_ALIGN_STATUS_UPDATED] = DPCD_INTERLANE_ALIGN_DONE;
s->dpcd_info[DPCD_SINK_STATUS] = DPCD_RECEIVE_PORT_0_STATUS;
}
static void dpcd_init(Object *obj)
{
DPCDState *s = DPCD(obj);
memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
}
static const VMStateDescription vmstate_dpcd = {
.name = TYPE_DPCD,
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
VMSTATE_END_OF_LIST()
}
};
static void dpcd_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->reset = dpcd_reset;
dc->vmsd = &vmstate_dpcd;
}
static const TypeInfo dpcd_info = {
.name = TYPE_DPCD,
.parent = TYPE_AUX_SLAVE,
.instance_size = sizeof(DPCDState),
.class_init = dpcd_class_init,
.instance_init = dpcd_init,
};
static void dpcd_register_types(void)
{
type_register_static(&dpcd_info);
}
type_init(dpcd_register_types)
hw/display/xlnx_dp.c
+1336
View File
File diff suppressed because it is too large Load Diff
hw/dma/Makefile.objs
+1
View File
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dpdma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
hw/dma/pxa2xx_dma.c
+22 -16
View File
@@ -12,6 +12,7 @@
#include "hw/hw.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32
@@ -450,31 +451,36 @@ static void pxa2xx_dma_request(void *opaque, int req_num, int on)
}
}
static int pxa2xx_dma_init(SysBusDevice *sbd)
static void pxa2xx_dma_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
PXA2xxDMAState *s = PXA2XX_DMA(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
memory_region_init_io(&s->iomem, obj, &pxa2xx_dma_ops, s,
"pxa2xx.dma", 0x00010000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static void pxa2xx_dma_realize(DeviceState *dev, Error **errp)
{
DeviceState *dev = DEVICE(sbd);
PXA2xxDMAState *s = PXA2XX_DMA(dev);
int i;
if (s->channels <= 0) {
return -1;
error_setg(errp, "channels value invalid");
return;
}
s->chan = g_new0(PXA2xxDMAChannel, s->channels);
for (i = 0; i < s->channels; i ++)
s->chan[i].state = DCSR_STOPINTR;
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_dma_ops, s,
"pxa2xx.dma", 0x00010000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
return 0;
}
DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
@@ -553,18 +559,18 @@ static Property pxa2xx_dma_properties[] = {
static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pxa2xx_dma_init;
dc->desc = "PXA2xx DMA controller";
dc->vmsd = &vmstate_pxa2xx_dma;
dc->props = pxa2xx_dma_properties;
dc->realize = pxa2xx_dma_realize;
}
static const TypeInfo pxa2xx_dma_info = {
.name = TYPE_PXA2XX_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxDMAState),
.instance_init = pxa2xx_dma_init,
.class_init = pxa2xx_dma_class_init,
};
hw/dma/xlnx_dpdma.c
+786
View File
File diff suppressed because it is too large Load Diff
hw/gpio/omap_gpio.c
+31 -30
View File
@@ -23,6 +23,7 @@
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
struct omap_gpio_s {
qemu_irq irq;
@@ -678,48 +679,46 @@ static const MemoryRegionOps omap2_gpif_top_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int omap_gpio_init(SysBusDevice *sbd)
static void omap_gpio_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
struct omap_gpif_s *s = OMAP1_GPIO(dev);
DeviceState *dev = DEVICE(obj);
struct omap_gpif_s *s = OMAP1_GPIO(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
if (!s->clk) {
error_report("omap-gpio: clk not connected");
return -1;
}
qdev_init_gpio_in(dev, omap_gpio_set, 16);
qdev_init_gpio_out(dev, s->omap1.handler, 16);
sysbus_init_irq(sbd, &s->omap1.irq);
memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1,
"omap.gpio", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static int omap2_gpio_init(SysBusDevice *sbd)
static void omap_gpio_realize(DeviceState *dev, Error **errp)
{
struct omap_gpif_s *s = OMAP1_GPIO(dev);
if (!s->clk) {
error_setg(errp, "omap-gpio: clk not connected");
}
}
static void omap2_gpio_realize(DeviceState *dev, Error **errp)
{
DeviceState *dev = DEVICE(sbd);
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
if (!s->iclk) {
error_report("omap2-gpio: iclk not connected");
return -1;
error_setg(errp, "omap2-gpio: iclk not connected");
return;
}
s->modulecount = s->mpu_model < omap2430 ? 4
: s->mpu_model < omap3430 ? 5
: 6;
for (i = 0; i < s->modulecount; i++) {
if (!s->fclk[i]) {
error_report("omap2-gpio: fclk%d not connected", i);
return -1;
}
}
: s->mpu_model < omap3430 ? 5
: 6;
if (s->mpu_model < omap3430) {
memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s,
"omap2.gpio", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
}
@@ -732,17 +731,20 @@ static int omap2_gpio_init(SysBusDevice *sbd)
for (i = 0; i < s->modulecount; i++) {
struct omap2_gpio_s *m = &s->modules[i];
if (!s->fclk[i]) {
error_setg(errp, "omap2-gpio: fclk%d not connected", i);
return;
}
m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
m->handler = &s->handler[i * 32];
sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
sysbus_init_irq(sbd, &m->wkup);
memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m,
"omap.gpio-module", 0x1000);
sysbus_init_mmio(sbd, &m->iomem);
}
return 0;
}
/* Using qdev pointer properties for the clocks is not ideal.
@@ -766,9 +768,8 @@ static Property omap_gpio_properties[] = {
static void omap_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = omap_gpio_init;
dc->realize = omap_gpio_realize;
dc->reset = omap_gpif_reset;
dc->props = omap_gpio_properties;
/* Reason: pointer property "clk" */
@@ -779,6 +780,7 @@ static const TypeInfo omap_gpio_info = {
.name = TYPE_OMAP1_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_gpif_s),
.instance_init = omap_gpio_init,
.class_init = omap_gpio_class_init,
};
@@ -797,9 +799,8 @@ static Property omap2_gpio_properties[] = {
static void omap2_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = omap2_gpio_init;
dc->realize = omap2_gpio_realize;
dc->reset = omap2_gpif_reset;
dc->props = omap2_gpio_properties;
/* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
hw/gpio/pl061.c
+8 -16
View File
@@ -341,20 +341,6 @@ static const MemoryRegionOps pl061_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl061_initfn(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
PL061State *s = PL061(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, pl061_set_irq, 8);
qdev_init_gpio_out(dev, s->out, 8);
return 0;
}
static void pl061_luminary_init(Object *obj)
{
PL061State *s = PL061(obj);
@@ -366,17 +352,23 @@ static void pl061_luminary_init(Object *obj)
static void pl061_init(Object *obj)
{
PL061State *s = PL061(obj);
DeviceState *dev = DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->id = pl061_id;
s->rsvd_start = 0x424;
memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, pl061_set_irq, 8);
qdev_init_gpio_out(dev, s->out, 8);
}
static void pl061_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl061_initfn;
dc->vmsd = &vmstate_pl061;
dc->reset = &pl061_reset;
}
hw/gpio/zaurus.c
+6 -8
View File
@@ -167,19 +167,18 @@ static void scoop_gpio_set(void *opaque, int line, int level)
s->gpio_level &= ~(1 << line);
}
static int scoop_init(SysBusDevice *sbd)
static void scoop_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
ScoopInfo *s = SCOOP(dev);
DeviceState *dev = DEVICE(obj);
ScoopInfo *s = SCOOP(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->status = 0x02;
qdev_init_gpio_out(dev, s->handler, 16);
qdev_init_gpio_in(dev, scoop_gpio_set, 16);
memory_region_init_io(&s->iomem, OBJECT(s), &scoop_ops, s, "scoop", 0x1000);
memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static int scoop_post_load(void *opaque, int version_id)
@@ -239,9 +238,7 @@ static const VMStateDescription vmstate_scoop_regs = {
static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = scoop_init;
dc->desc = "Scoop2 Sharp custom ASIC";
dc->vmsd = &vmstate_scoop_regs;
}
@@ -250,6 +247,7 @@ static const TypeInfo scoop_sysbus_info = {
.name = TYPE_SCOOP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ScoopInfo),
.instance_init = scoop_init,
.class_init = scoop_sysbus_class_init,
};
hw/i2c/Makefile.objs
+1
View File
@@ -1,4 +1,5 @@
common-obj-y += core.o smbus.o smbus_eeprom.o
common-obj-$(CONFIG_DDC) += i2c-ddc.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
hw/i2c/bitbang_i2c.c
+6 -8
View File
@@ -210,13 +210,14 @@ static void bitbang_i2c_gpio_set(void *opaque, int irq, int level)
}
}
static int gpio_i2c_init(SysBusDevice *sbd)
static void gpio_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
GPIOI2CState *s = GPIO_I2C(dev);
DeviceState *dev = DEVICE(obj);
GPIOI2CState *s = GPIO_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
I2CBus *bus;
memory_region_init(&s->dummy_iomem, OBJECT(s), "gpio_i2c", 0);
memory_region_init(&s->dummy_iomem, obj, "gpio_i2c", 0);
sysbus_init_mmio(sbd, &s->dummy_iomem);
bus = i2c_init_bus(dev, "i2c");
@@ -224,16 +225,12 @@ static int gpio_i2c_init(SysBusDevice *sbd)
qdev_init_gpio_in(dev, bitbang_i2c_gpio_set, 2);
qdev_init_gpio_out(dev, &s->out, 1);
return 0;
}
static void gpio_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = gpio_i2c_init;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "Virtual GPIO to I2C bridge";
}
@@ -242,6 +239,7 @@ static const TypeInfo gpio_i2c_info = {
.name = TYPE_GPIO_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(GPIOI2CState),
.instance_init = gpio_i2c_init,
.class_init = gpio_i2c_class_init,
};
hw/i2c/core.c
+103 -64
View File
@@ -10,12 +10,19 @@
#include "qemu/osdep.h"
#include "hw/i2c/i2c.h"
typedef struct I2CNode I2CNode;
struct I2CNode {
I2CSlave *elt;
QLIST_ENTRY(I2CNode) next;
};
struct I2CBus
{
BusState qbus;
I2CSlave *current_dev;
I2CSlave *dev;
QLIST_HEAD(, I2CNode) current_devs;
uint8_t saved_address;
bool broadcast;
};
static Property i2c_props[] = {
@@ -36,17 +43,12 @@ static void i2c_bus_pre_save(void *opaque)
{
I2CBus *bus = opaque;
bus->saved_address = bus->current_dev ? bus->current_dev->address : -1;
}
static int i2c_bus_post_load(void *opaque, int version_id)
{
I2CBus *bus = opaque;
/* The bus is loaded before attached devices, so load and save the
current device id. Devices will check themselves as loaded. */
bus->current_dev = NULL;
return 0;
bus->saved_address = -1;
if (!QLIST_EMPTY(&bus->current_devs)) {
if (!bus->broadcast) {
bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address;
}
}
}
static const VMStateDescription vmstate_i2c_bus = {
@@ -54,9 +56,9 @@ static const VMStateDescription vmstate_i2c_bus = {
.version_id = 1,
.minimum_version_id = 1,
.pre_save = i2c_bus_pre_save,
.post_load = i2c_bus_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8(saved_address, I2CBus),
VMSTATE_BOOL(broadcast, I2CBus),
VMSTATE_END_OF_LIST()
}
};
@@ -67,6 +69,7 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
I2CBus *bus;
bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
QLIST_INIT(&bus->current_devs);
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
return bus;
}
@@ -79,7 +82,7 @@ void i2c_set_slave_address(I2CSlave *dev, uint8_t address)
/* Return nonzero if bus is busy. */
int i2c_bus_busy(I2CBus *bus)
{
return bus->current_dev != NULL;
return !QLIST_EMPTY(&bus->current_devs);
}
/* Returns non-zero if the address is not valid. */
@@ -87,95 +90,127 @@ int i2c_bus_busy(I2CBus *bus)
int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
{
BusChild *kid;
I2CSlave *slave = NULL;
I2CSlaveClass *sc;
I2CNode *node;
if (address == 0x00) {
/*
* This is a broadcast, the current_devs will be all the devices of the
* bus.
*/
bus->broadcast = true;
}
QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
DeviceState *qdev = kid->child;
I2CSlave *candidate = I2C_SLAVE(qdev);
if (candidate->address == address) {
slave = candidate;
break;
if ((candidate->address == address) || (bus->broadcast)) {
node = g_malloc(sizeof(struct I2CNode));
node->elt = candidate;
QLIST_INSERT_HEAD(&bus->current_devs, node, next);
if (!bus->broadcast) {
break;
}
}
}
if (!slave) {
if (QLIST_EMPTY(&bus->current_devs)) {
return 1;
}
sc = I2C_SLAVE_GET_CLASS(slave);
/* If the bus is already busy, assume this is a repeated
start condition. */
bus->current_dev = slave;
if (sc->event) {
sc->event(slave, recv ? I2C_START_RECV : I2C_START_SEND);
QLIST_FOREACH(node, &bus->current_devs, next) {
sc = I2C_SLAVE_GET_CLASS(node->elt);
/* If the bus is already busy, assume this is a repeated
start condition. */
if (sc->event) {
sc->event(node->elt, recv ? I2C_START_RECV : I2C_START_SEND);
}
}
return 0;
}
void i2c_end_transfer(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
I2CNode *node, *next;
if (!dev) {
if (QLIST_EMPTY(&bus->current_devs)) {
return;
}
sc = I2C_SLAVE_GET_CLASS(dev);
if (sc->event) {
sc->event(dev, I2C_FINISH);
QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
sc = I2C_SLAVE_GET_CLASS(node->elt);
if (sc->event) {
sc->event(node->elt, I2C_FINISH);
}
QLIST_REMOVE(node, next);
g_free(node);
}
bus->broadcast = false;
}
bus->current_dev = NULL;
int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
{
I2CSlaveClass *sc;
I2CNode *node;
int ret = 0;
if (send) {
QLIST_FOREACH(node, &bus->current_devs, next) {
sc = I2C_SLAVE_GET_CLASS(node->elt);
if (sc->send) {
ret = ret || sc->send(node->elt, *data);
} else {
ret = -1;
}
}
return ret ? -1 : 0;
} else {
if ((QLIST_EMPTY(&bus->current_devs)) || (bus->broadcast)) {
return -1;
}
sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
if (sc->recv) {
ret = sc->recv(QLIST_FIRST(&bus->current_devs)->elt);
if (ret < 0) {
return ret;
} else {
*data = ret;
return 0;
}
}
return -1;
}
}
int i2c_send(I2CBus *bus, uint8_t data)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
if (!dev) {
return -1;
}
sc = I2C_SLAVE_GET_CLASS(dev);
if (sc->send) {
return sc->send(dev, data);
}
return -1;
return i2c_send_recv(bus, &data, true);
}
int i2c_recv(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
uint8_t data;
int ret = i2c_send_recv(bus, &data, false);
if (!dev) {
return -1;
}
sc = I2C_SLAVE_GET_CLASS(dev);
if (sc->recv) {
return sc->recv(dev);
}
return -1;
return ret < 0 ? ret : data;
}
void i2c_nack(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
I2CNode *node;
if (!dev) {
if (QLIST_EMPTY(&bus->current_devs)) {
return;
}
sc = I2C_SLAVE_GET_CLASS(dev);
if (sc->event) {
sc->event(dev, I2C_NACK);
QLIST_FOREACH(node, &bus->current_devs, next) {
sc = I2C_SLAVE_GET_CLASS(node->elt);
if (sc->event) {
sc->event(node->elt, I2C_NACK);
}
}
}
@@ -183,9 +218,13 @@ static int i2c_slave_post_load(void *opaque, int version_id)
{
I2CSlave *dev = opaque;
I2CBus *bus;
I2CNode *node;
bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
if (bus->saved_address == dev->address) {
bus->current_dev = dev;
if ((bus->saved_address == dev->address) || (bus->broadcast)) {
node = g_malloc(sizeof(struct I2CNode));
node->elt = dev;
QLIST_INSERT_HEAD(&bus->current_devs, node, next);
}
return 0;
}
hw/i2c/exynos4210_i2c.c
+6 -7
View File
@@ -299,33 +299,32 @@ static void exynos4210_i2c_reset(DeviceState *d)
s->scl_free = true;
}
static int exynos4210_i2c_realize(SysBusDevice *sbd)
static void exynos4210_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
Exynos4210I2CState *s = EXYNOS4_I2C(dev);
DeviceState *dev = DEVICE(obj);
Exynos4210I2CState *s = EXYNOS4_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_i2c_ops, s,
memory_region_init_io(&s->iomem, obj, &exynos4210_i2c_ops, s,
TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->bus = i2c_init_bus(dev, "i2c");
return 0;
}
static void exynos4210_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbdc = SYS_BUS_DEVICE_CLASS(klass);
dc->vmsd = &exynos4210_i2c_vmstate;
dc->reset = exynos4210_i2c_reset;
sbdc->init = exynos4210_i2c_realize;
}
static const TypeInfo exynos4210_i2c_type_info = {
.name = TYPE_EXYNOS4_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210I2CState),
.instance_init = exynos4210_i2c_init,
.class_init = exynos4210_i2c_class_init,
};
hw/i2c/i2c-ddc.c
+308
View File
@@ -0,0 +1,308 @@
/* A simple I2C slave for returning monitor EDID data via DDC.
*
* Copyright (c) 2011 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/i2c/i2c.h"
#include "hw/i2c/i2c-ddc.h"
#ifndef DEBUG_I2CDDC
#define DEBUG_I2CDDC 0
#endif
#define DPRINTF(fmt, ...) do { \
if (DEBUG_I2CDDC) { \
qemu_log("i2c-ddc: " fmt , ## __VA_ARGS__); \
} \
} while (0);
/* Structure defining a monitor's characteristics in a
* readable format: this should be passed to build_edid_blob()
* to convert it into the 128 byte binary EDID blob.
* Not all bits of the EDID are customisable here.
*/
struct EDIDData {
char manuf_id[3]; /* three upper case letters */
uint16_t product_id;
uint32_t serial_no;
uint8_t manuf_week;
int manuf_year;
uint8_t h_cm;
uint8_t v_cm;
uint8_t gamma;
char monitor_name[14];
char serial_no_string[14];
/* Range limits */
uint8_t vmin; /* Hz */
uint8_t vmax; /* Hz */
uint8_t hmin; /* kHz */
uint8_t hmax; /* kHz */
uint8_t pixclock; /* MHz / 10 */
uint8_t timing_data[18];
};
typedef struct EDIDData EDIDData;
/* EDID data for a simple LCD monitor */
static const EDIDData lcd_edid = {
/* The manuf_id ought really to be an assigned EISA ID */
.manuf_id = "QMU",
.product_id = 0,
.serial_no = 1,
.manuf_week = 1,
.manuf_year = 2011,
.h_cm = 40,
.v_cm = 30,
.gamma = 0x78,
.monitor_name = "QEMU monitor",
.serial_no_string = "1",
.vmin = 40,
.vmax = 120,
.hmin = 30,
.hmax = 100,
.pixclock = 18,
.timing_data = {
/* Borrowed from a 21" LCD */
0x48, 0x3f, 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40,
0xc0, 0x13, 0x00, 0x98, 0x32, 0x11, 0x00, 0x00, 0x1e
}
};
static uint8_t manuf_char_to_int(char c)
{
return (c - 'A') & 0x1f;
}
static void write_ascii_descriptor_block(uint8_t *descblob, uint8_t blocktype,
const char *string)
{
/* Write an EDID Descriptor Block of the "ascii string" type */
int i;
descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
descblob[3] = blocktype;
/* The rest is 13 bytes of ASCII; if less then the rest must
* be filled with newline then spaces
*/
for (i = 5; i < 19; i++) {
descblob[i] = string[i - 5];
if (!descblob[i]) {
break;
}
}
if (i < 19) {
descblob[i++] = '\n';
}
for ( ; i < 19; i++) {
descblob[i] = ' ';
}
}
static void write_range_limits_descriptor(const EDIDData *edid,
uint8_t *descblob)
{
int i;
descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
descblob[3] = 0xfd;
descblob[5] = edid->vmin;
descblob[6] = edid->vmax;
descblob[7] = edid->hmin;
descblob[8] = edid->hmax;
descblob[9] = edid->pixclock;
descblob[10] = 0;
descblob[11] = 0xa;
for (i = 12; i < 19; i++) {
descblob[i] = 0x20;
}
}
static void build_edid_blob(const EDIDData *edid, uint8_t *blob)
{
/* Write an EDID 1.3 format blob (128 bytes) based
* on the EDIDData structure.
*/
int i;
uint8_t cksum;
/* 00-07 : header */
blob[0] = blob[7] = 0;
for (i = 1 ; i < 7; i++) {
blob[i] = 0xff;
}
/* 08-09 : manufacturer ID */
blob[8] = (manuf_char_to_int(edid->manuf_id[0]) << 2)
| (manuf_char_to_int(edid->manuf_id[1]) >> 3);
blob[9] = (manuf_char_to_int(edid->manuf_id[1]) << 5)
| manuf_char_to_int(edid->manuf_id[2]);
/* 10-11 : product ID code */
blob[10] = edid->product_id;
blob[11] = edid->product_id >> 8;
blob[12] = edid->serial_no;
blob[13] = edid->serial_no >> 8;
blob[14] = edid->serial_no >> 16;
blob[15] = edid->serial_no >> 24;
/* 16 : week of manufacture */
blob[16] = edid->manuf_week;
/* 17 : year of manufacture - 1990 */
blob[17] = edid->manuf_year - 1990;
/* 18, 19 : EDID version and revision */
blob[18] = 1;
blob[19] = 3;
/* 20 - 24 : basic display parameters */
/* We are always a digital display */
blob[20] = 0x80;
/* 21, 22 : max h/v size in cm */
blob[21] = edid->h_cm;
blob[22] = edid->v_cm;
/* 23 : gamma (divide by 100 then add 1 for actual value) */
blob[23] = edid->gamma;
/* 24 feature support: no power management, RGB, preferred timing mode,
* standard colour space
*/
blob[24] = 0x0e;
/* 25 - 34 : chromaticity coordinates. These are the
* standard sRGB chromaticity values
*/
blob[25] = 0xee;
blob[26] = 0x91;
blob[27] = 0xa3;
blob[28] = 0x54;
blob[29] = 0x4c;
blob[30] = 0x99;
blob[31] = 0x26;
blob[32] = 0x0f;
blob[33] = 0x50;
blob[34] = 0x54;
/* 35, 36 : Established timings: claim to support everything */
blob[35] = blob[36] = 0xff;
/* 37 : manufacturer's reserved timing: none */
blob[37] = 0;
/* 38 - 53 : standard timing identification
* don't claim anything beyond what the 'established timings'
* already provide. Unused slots must be (0x1, 0x1)
*/
for (i = 38; i < 54; i++) {
blob[i] = 0x1;
}
/* 54 - 71 : descriptor block 1 : must be preferred timing data */
memcpy(blob + 54, edid->timing_data, 18);
/* 72 - 89, 90 - 107, 108 - 125 : descriptor block 2, 3, 4
* Order not important, but we must have a monitor name and a
* range limits descriptor.
*/
write_range_limits_descriptor(edid, blob + 72);
write_ascii_descriptor_block(blob + 90, 0xfc, edid->monitor_name);
write_ascii_descriptor_block(blob + 108, 0xff, edid->serial_no_string);
/* 126 : extension flag */
blob[126] = 0;
cksum = 0;
for (i = 0; i < 127; i++) {
cksum += blob[i];
}
/* 127 : checksum */
blob[127] = -cksum;
if (DEBUG_I2CDDC) {
qemu_hexdump((char *)blob, stdout, "", 128);
}
}
static void i2c_ddc_reset(DeviceState *ds)
{
I2CDDCState *s = I2CDDC(ds);
s->firstbyte = false;
s->reg = 0;
}
static void i2c_ddc_event(I2CSlave *i2c, enum i2c_event event)
{
I2CDDCState *s = I2CDDC(i2c);
if (event == I2C_START_SEND) {
s->firstbyte = true;
}
}
static int i2c_ddc_rx(I2CSlave *i2c)
{
I2CDDCState *s = I2CDDC(i2c);
int value;
value = s->edid_blob[s->reg];
s->reg++;
return value;
}
static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
{
I2CDDCState *s = I2CDDC(i2c);
if (s->firstbyte) {
s->reg = data;
s->firstbyte = false;
DPRINTF("[EDID] Written new pointer: %u\n", data);
return 1;
}
/* Ignore all writes */
s->reg++;
return 1;
}
static void i2c_ddc_init(Object *obj)
{
I2CDDCState *s = I2CDDC(obj);
build_edid_blob(&lcd_edid, s->edid_blob);
}
static const VMStateDescription vmstate_i2c_ddc = {
.name = TYPE_I2CDDC,
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_BOOL(firstbyte, I2CDDCState),
VMSTATE_UINT8(reg, I2CDDCState),
VMSTATE_END_OF_LIST()
}
};
static void i2c_ddc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
dc->reset = i2c_ddc_reset;
dc->vmsd = &vmstate_i2c_ddc;
isc->event = i2c_ddc_event;
isc->recv = i2c_ddc_rx;
isc->send = i2c_ddc_tx;
}
static TypeInfo i2c_ddc_info = {
.name = TYPE_I2CDDC,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(I2CDDCState),
.instance_init = i2c_ddc_init,
.class_init = i2c_ddc_class_init
};
static void ddc_register_devices(void)
{
type_register_static(&i2c_ddc_info);
}
type_init(ddc_register_devices);
hw/i2c/omap_i2c.c
+26 -18
View File
@@ -22,6 +22,7 @@
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#define TYPE_OMAP_I2C "omap_i2c"
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
@@ -445,29 +446,35 @@ static const MemoryRegionOps omap_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int omap_i2c_init(SysBusDevice *sbd)
static void omap_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
OMAPI2CState *s = OMAP_I2C(dev);
if (!s->fclk) {
error_report("omap_i2c: fclk not connected");
return -1;
}
if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
/* Note that OMAP1 doesn't have a separate interface clock */
error_report("omap_i2c: iclk not connected");
return -1;
}
DeviceState *dev = DEVICE(obj);
OMAPI2CState *s = OMAP_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->drq[0]);
sysbus_init_irq(sbd, &s->drq[1]);
memory_region_init_io(&s->iomem, OBJECT(s), &omap_i2c_ops, s, "omap.i2c",
(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
s->bus = i2c_init_bus(dev, NULL);
return 0;
}
static void omap_i2c_realize(DeviceState *dev, Error **errp)
{
OMAPI2CState *s = OMAP_I2C(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c",
(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
if (!s->fclk) {
error_setg(errp, "omap_i2c: fclk not connected");
return;
}
if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
/* Note that OMAP1 doesn't have a separate interface clock */
error_setg(errp, "omap_i2c: iclk not connected");
return;
}
}
static Property omap_i2c_properties[] = {
@@ -480,18 +487,19 @@ static Property omap_i2c_properties[] = {
static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = omap_i2c_init;
dc->props = omap_i2c_properties;
dc->reset = omap_i2c_reset;
/* Reason: pointer properties "iclk", "fclk" */
dc->cannot_instantiate_with_device_add_yet = true;
dc->realize = omap_i2c_realize;
}
static const TypeInfo omap_i2c_info = {
.name = TYPE_OMAP_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OMAPI2CState),
.instance_init = omap_i2c_init,
.class_init = omap_i2c_class_init,
};
hw/i2c/versatile_i2c.c
+6 -13
View File
@@ -79,32 +79,25 @@ static const MemoryRegionOps versatile_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int versatile_i2c_init(SysBusDevice *sbd)
static void versatile_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
VersatileI2CState *s = VERSATILE_I2C(dev);
DeviceState *dev = DEVICE(obj);
VersatileI2CState *s = VERSATILE_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
I2CBus *bus;
bus = i2c_init_bus(dev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
memory_region_init_io(&s->iomem, OBJECT(s), &versatile_i2c_ops, s,
memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
"versatile_i2c", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static void versatile_i2c_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = versatile_i2c_init;
}
static const TypeInfo versatile_i2c_info = {
.name = TYPE_VERSATILE_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(VersatileI2CState),
.class_init = versatile_i2c_class_init,
.instance_init = versatile_i2c_init,
};
static void versatile_i2c_register_types(void)

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