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intel-iommu: PASID support
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the existing support for scalable mode, we need to implement the following missing parts: 1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation with PASID 2) tag IOTLB with PASID 3) PASID cache and its flush 4) PASID based IOTLB invalidation For simplicity PASID cache is not implemented so we can simply implement the PASID cache flush as a no and leave it to be implemented in the future. For PASID based IOTLB invalidation, since we haven't had L1 stage support, the PASID based IOTLB invalidation is not implemented yet. For PASID based device IOTLB invalidation, it requires the support for vhost so we forbid enabling device IOTLB when PASID is enabled now. Those work could be done in the future. Note that though PASID based IOMMU translation is ready but no device can issue PASID DMA right now. In this case, PCI_NO_PASID is used as PASID to identify the address without PASID. vtd_find_add_as() has been extended to provision address space with PASID which could be utilized by the future extension of PCI core to allow device model to use PASID based DMA translation. This feature would be useful for: 1) prototyping PASID support for devices like virtio 2) future vPASID work 3) future PRS and vSVA work Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jason Wang
committed by
Michael S. Tsirkin
Michael S. Tsirkin
parent
940e552786
commit
1b2b12376c
+317
-101
File diff suppressed because it is too large
Load Diff
@@ -114,8 +114,9 @@
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VTD_INTERRUPT_ADDR_FIRST + 1)
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/* The shift of source_id in the key of IOTLB hash table */
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#define VTD_IOTLB_SID_SHIFT 36
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#define VTD_IOTLB_LVL_SHIFT 52
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#define VTD_IOTLB_SID_SHIFT 20
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#define VTD_IOTLB_LVL_SHIFT 28
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#define VTD_IOTLB_PASID_SHIFT 30
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#define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */
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/* IOTLB_REG */
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@@ -191,6 +192,7 @@
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#define VTD_ECAP_SC (1ULL << 7)
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#define VTD_ECAP_MHMV (15ULL << 20)
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#define VTD_ECAP_SRS (1ULL << 31)
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#define VTD_ECAP_PASID (1ULL << 40)
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#define VTD_ECAP_SMTS (1ULL << 43)
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#define VTD_ECAP_SLTS (1ULL << 46)
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@@ -211,6 +213,8 @@
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#define VTD_CAP_DRAIN_READ (1ULL << 55)
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#define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
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#define VTD_CAP_CM (1ULL << 7)
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#define VTD_PASID_ID_SHIFT 20
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#define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1)
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/* Supported Adjusted Guest Address Widths */
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#define VTD_CAP_SAGAW_SHIFT 8
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@@ -262,6 +266,8 @@
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#define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
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/* For the low 64-bit of 128-bit */
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#define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
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#define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40)
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#define VTD_FRCD_PP(val) (((val) & 0x1) << 31)
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/* DMA Remapping Fault Conditions */
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typedef enum VTDFaultReason {
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@@ -379,6 +385,11 @@ typedef union VTDInvDesc VTDInvDesc;
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#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
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#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL
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#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
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#define VTD_INV_DESC_IOTLB_PASID_PASID (2ULL << 4)
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#define VTD_INV_DESC_IOTLB_PASID_PAGE (3ULL << 4)
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#define VTD_INV_DESC_IOTLB_PASID(val) (((val) >> 32) & VTD_PASID_ID_MASK)
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#define VTD_INV_DESC_IOTLB_PASID_RSVD_LO 0xfff00000000001c0ULL
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#define VTD_INV_DESC_IOTLB_PASID_RSVD_HI 0xf80ULL
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/* Mask for Device IOTLB Invalidate Descriptor */
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#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
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@@ -413,6 +424,7 @@ typedef union VTDInvDesc VTDInvDesc;
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/* Information about page-selective IOTLB invalidate */
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struct VTDIOTLBPageInvInfo {
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uint16_t domain_id;
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uint32_t pasid;
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uint64_t addr;
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uint8_t mask;
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};
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@@ -12,6 +12,8 @@ vtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "context invalidate device
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vtd_inv_desc_iotlb_global(void) "iotlb invalidate global"
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vtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16
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vtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8
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vtd_inv_desc_iotlb_pasid_pages(uint16_t domain, uint64_t addr, uint8_t mask, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8" pasid 0x%"PRIx32
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vtd_inv_desc_iotlb_pasid(uint16_t domain, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" pasid 0x%"PRIx32
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vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32
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vtd_inv_desc_wait_irq(const char *msg) "%s"
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vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64
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@@ -97,11 +97,13 @@ struct VTDPASIDEntry {
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struct VTDAddressSpace {
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PCIBus *bus;
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uint8_t devfn;
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uint32_t pasid;
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AddressSpace as;
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IOMMUMemoryRegion iommu;
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MemoryRegion root; /* The root container of the device */
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MemoryRegion nodmar; /* The alias of shared nodmar MR */
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MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
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MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */
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IntelIOMMUState *iommu_state;
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VTDContextCacheEntry context_cache_entry;
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QLIST_ENTRY(VTDAddressSpace) next;
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@@ -113,6 +115,7 @@ struct VTDAddressSpace {
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struct VTDIOTLBEntry {
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uint64_t gfn;
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uint16_t domain_id;
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uint32_t pasid;
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uint64_t slpte;
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uint64_t mask;
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uint8_t access_flags;
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@@ -261,6 +264,7 @@ struct IntelIOMMUState {
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uint8_t aw_bits; /* Host/IOVA address width (in bits) */
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bool dma_drain; /* Whether DMA r/w draining enabled */
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bool dma_translation; /* Whether DMA translation supported */
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bool pasid; /* Whether to support PASID */
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/*
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* Protects IOMMU states in general. Currently it protects the
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@@ -272,6 +276,7 @@ struct IntelIOMMUState {
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/* Find the VTD Address space associated with the given bus pointer,
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* create a new one if none exists
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*/
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VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
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VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus,
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int devfn, unsigned int pasid);
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#endif
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@@ -28,6 +28,8 @@ enum PCIBusFlags {
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PCI_BUS_CXL = 0x0004,
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};
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#define PCI_NO_PASID UINT32_MAX
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struct PCIBus {
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BusState qbus;
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enum PCIBusFlags flags;
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