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target/riscv: Improve the scause logic

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No functional change, just making the code easier to read.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Alistair Francis
2019-05-24 12:09:24 -07:00
committed by Palmer Dabbelt
parent 0a01f2eecb
commit 16fdb8ff64
1 changed files with 1 additions and 1 deletions
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target/riscv/cpu_helper.c
+1 -1
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@@ -515,7 +515,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
env->scause = cause | ~(((target_ulong)-1) >> async);
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->pc = (env->stvec >> 2 << 2) +