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Merge remote-tracking branch 'pmaydell/arm-devs.next' into staging

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# By Peter Crosthwaite (20) and others
# Via Peter Maydell
* pmaydell/arm-devs.next: (24 commits)
  i.MX: Improve EPIT timer code.
  exynos4210.c: register rom_mem for memory migration
  hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region
  i.MX: split GPT and EPIT timer implementation
  sd/sd.c: Fix "inquiry" ACMD41
  sd/sdhci:ADMA: fix interrupt
  sd/sdhci.c: Fix bdata_read DPRINT message
  sd/sdhci: Fix Buffer Write Ready interrupt
  sd/sdhci.c: Only reset data_count on new commands
  xilinx_spips: lqspi: Fix byte/misaligned access
  xilinx_spips: lqspi: Push more data to tx-fifo
  xilinx_spips: Multiple debug verbosity levels
  xilinx_spips: Debug msgs for Snoop state
  xilinx_spips: Fix striping behaviour
  xilinx_spips: Fix CTRL register RW bits
  xilinx_spips: lqspi: Dont touch config register
  xilinx_spips: Implement automatic CS
  xilinx_spips: Add automatic start support
  xilinx_spips: Trash LQ page cache on mode change
  xilinx_spips: Fix QSPI FIFO size
  ...

Message-id: 1370277021-26129-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
2013-06-03 13:24:25 -05:00
parent 8b779b368b 95669e6984
commit 0ded1fe5f3
8 changed files with 736 additions and 456 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/arm/exynos4210.c
+25 -3
View File
@@ -79,6 +79,28 @@
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
unsigned size)
{
assert(offset < sizeof(chipid_and_omr));
return chipid_and_omr[offset];
}
static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
return;
}
static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
.read = exynos4210_chipid_and_omr_read,
.write = exynos4210_chipid_and_omr_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.max_access_size = 1,
}
};
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
@@ -219,15 +241,15 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
/*** Memory ***/
/* Chip-ID and OMR */
memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
sizeof(chipid_and_omr), chipid_and_omr);
memory_region_set_readonly(&s->chipid_mem, true);
memory_region_init_io(&s->chipid_mem, &exynos4210_chipid_and_omr_ops,
NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
&s->chipid_mem);
/* Internal ROM */
memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
EXYNOS4210_IROM_SIZE);
vmstate_register_ram_global(&s->irom_mem);
memory_region_set_readonly(&s->irom_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
&s->irom_mem);
hw/arm/xilinx_zynq.c
+1 -1
View File
@@ -66,7 +66,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
dev = qdev_create(NULL, "xilinx,spips");
dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
hw/sd/sd.c
+9 -2
View File
@@ -43,6 +43,8 @@ do { fprintf(stderr, "SD: " fmt , ## __VA_ARGS__); } while (0)
#define DPRINTF(fmt, ...) do {} while(0)
#endif
#define ACMD41_ENQUIRY_MASK 0x00ffffff
typedef enum {
sd_r0 = 0, /* no response */
sd_r1, /* normal response command */
@@ -1277,9 +1279,14 @@ static sd_rsp_type_t sd_app_command(SDState *sd,
}
switch (sd->state) {
case sd_idle_state:
/* We accept any voltage. 10000 V is nothing. */
if (req.arg)
/* We accept any voltage. 10000 V is nothing.
*
* We don't model init delay so just advance straight to ready state
* unless it's an enquiry ACMD41 (bits 23:0 == 0).
*/
if (req.arg & ACMD41_ENQUIRY_MASK) {
sd->state = sd_ready_state;
}
return sd_r3;
hw/sd/sdhci.c
+14 -14
View File
@@ -260,6 +260,7 @@ static void sdhci_send_command(SDHCIState *s)
sdhci_update_irq(s);
if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
s->data_count = 0;
sdhci_do_data_transfer(s);
}
}
@@ -404,15 +405,14 @@ static void sdhci_write_block_to_card(SDHCIState *s)
/* Next data can be written through BUFFER DATORT register */
s->prnsts |= SDHC_SPACE_AVAILABLE;
if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
s->norintsts |= SDHC_NIS_WBUFRDY;
}
/* Finish transfer if that was the last block of data */
if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
((s->trnmod & SDHC_TRNS_MULTI) &&
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
SDHCI_GET_CLASS(s)->end_data_transfer(s);
} else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
s->norintsts |= SDHC_NIS_WBUFRDY;
}
/* Generate Block Gap Event if requested and if not the last block */
@@ -730,6 +730,15 @@ static void sdhci_do_adma(SDHCIState *s)
break;
}
if (dscr.attr & SDHC_ADMA_ATTR_INT) {
DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
if (s->norintstsen & SDHC_NISEN_DMA) {
s->norintsts |= SDHC_NIS_DMA;
}
sdhci_update_irq(s);
}
/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
(s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
@@ -752,15 +761,6 @@ static void sdhci_do_adma(SDHCIState *s)
return;
}
if (dscr.attr & SDHC_ADMA_ATTR_INT) {
DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr);
if (s->norintstsen & SDHC_NISEN_DMA) {
s->norintsts |= SDHC_NIS_DMA;
}
sdhci_update_irq(s);
return;
}
}
/* we have unfinished business - reschedule to continue ADMA */
@@ -773,7 +773,6 @@ static void sdhci_do_adma(SDHCIState *s)
static void sdhci_data_transfer(SDHCIState *s)
{
SDHCIClass *k = SDHCI_GET_CLASS(s);
s->data_count = 0;
if (s->trnmod & SDHC_TRNS_DMA) {
switch (SDHC_DMA_TYPE(s->hostctl)) {
@@ -881,7 +880,8 @@ static uint32_t sdhci_read(SDHCIState *s, unsigned int offset, unsigned size)
case SDHC_BDATA:
if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
ret = SDHCI_GET_CLASS(s)->bdata_read(s, size);
DPRINT_L2("read %ub: addr[0x%04x] -> %u\n", size, offset, ret);
DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset,
ret, ret);
return ret;
}
break;
hw/ssi/xilinx_spips.c
+249 -73
View File
File diff suppressed because it is too large Load Diff
hw/timer/Makefile.objs
+2 -1
View File
@@ -11,7 +11,8 @@ common-obj-$(CONFIG_XILINX) += xilinx_timer.o
common-obj-$(CONFIG_SLAVIO) += slavio_timer.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_timer.o
common-obj-$(CONFIG_GRLIB) += grlib_gptimer.o
common-obj-$(CONFIG_IMX) += imx_timer.o
common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
hw/timer/imx_epit.c
+432
View File
@@ -0,0 +1,432 @@
/*
* IMX EPIT Timer
*
* Copyright (c) 2008 OK Labs
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
* Updated by Peter Chubb
* Updated by Jean-Christophe Dubois
*
* This code is licensed under GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
*/
#include "hw/hw.h"
#include "qemu/bitops.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "hw/sysbus.h"
#include "hw/arm/imx.h"
#define TYPE_IMX_EPIT "imx.epit"
#define DEBUG_TIMER 0
#if DEBUG_TIMER
static char const *imx_epit_reg_name(uint32_t reg)
{
switch (reg) {
case 0:
return "CR";
case 1:
return "SR";
case 2:
return "LR";
case 3:
return "CMP";
case 4:
return "CNT";
default:
return "[?]";
}
}
# define DPRINTF(fmt, args...) \
do { printf("%s: " fmt , __func__, ##args); } while (0)
#else
# define DPRINTF(fmt, args...) do {} while (0)
#endif
/*
* Define to 1 for messages about attempts to
* access unimplemented registers or similar.
*/
#define DEBUG_IMPLEMENTATION 1
#if DEBUG_IMPLEMENTATION
# define IPRINTF(fmt, args...) \
do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
#else
# define IPRINTF(fmt, args...) do {} while (0)
#endif
#define IMX_EPIT(obj) \
OBJECT_CHECK(IMXEPITState, (obj), TYPE_IMX_EPIT)
/*
* EPIT: Enhanced periodic interrupt timer
*/
#define CR_EN (1 << 0)
#define CR_ENMOD (1 << 1)
#define CR_OCIEN (1 << 2)
#define CR_RLD (1 << 3)
#define CR_PRESCALE_SHIFT (4)
#define CR_PRESCALE_MASK (0xfff)
#define CR_SWR (1 << 16)
#define CR_IOVW (1 << 17)
#define CR_DBGEN (1 << 18)
#define CR_WAITEN (1 << 19)
#define CR_DOZEN (1 << 20)
#define CR_STOPEN (1 << 21)
#define CR_CLKSRC_SHIFT (24)
#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
#define TIMER_MAX 0XFFFFFFFFUL
/*
* Exact clock frequencies vary from board to board.
* These are typical.
*/
static const IMXClk imx_epit_clocks[] = {
0, /* 00 disabled */
IPG, /* 01 ipg_clk, ~532MHz */
IPG, /* 10 ipg_clk_highfreq */
CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
};
typedef struct {
SysBusDevice busdev;
ptimer_state *timer_reload;
ptimer_state *timer_cmp;
MemoryRegion iomem;
DeviceState *ccm;
uint32_t cr;
uint32_t sr;
uint32_t lr;
uint32_t cmp;
uint32_t cnt;
uint32_t freq;
qemu_irq irq;
} IMXEPITState;
/*
* Update interrupt status
*/
static void imx_epit_update_int(IMXEPITState *s)
{
if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
static void imx_epit_set_freq(IMXEPITState *s)
{
uint32_t clksrc;
uint32_t prescaler;
uint32_t freq;
clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
freq = imx_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler;
s->freq = freq;
DPRINTF("Setting ptimer frequency to %u\n", freq);
if (freq) {
ptimer_set_freq(s->timer_reload, freq);
ptimer_set_freq(s->timer_cmp, freq);
}
}
static void imx_epit_reset(DeviceState *dev)
{
IMXEPITState *s = IMX_EPIT(dev);
/*
* Soft reset doesn't touch some bits; hard reset clears them
*/
s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
s->sr = 0;
s->lr = TIMER_MAX;
s->cmp = 0;
s->cnt = 0;
/* stop both timers */
ptimer_stop(s->timer_cmp);
ptimer_stop(s->timer_reload);
/* compute new frequency */
imx_epit_set_freq(s);
/* init both timers to TIMER_MAX */
ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
if (s->freq && (s->cr & CR_EN)) {
/* if the timer is still enabled, restart it */
ptimer_run(s->timer_reload, 1);
}
}
static uint32_t imx_epit_update_count(IMXEPITState *s)
{
s->cnt = ptimer_get_count(s->timer_reload);
return s->cnt;
}
static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
{
IMXEPITState *s = IMX_EPIT(opaque);
uint32_t reg_value = 0;
uint32_t reg = offset >> 2;
switch (reg) {
case 0: /* Control Register */
reg_value = s->cr;
break;
case 1: /* Status Register */
reg_value = s->sr;
break;
case 2: /* LR - ticks*/
reg_value = s->lr;
break;
case 3: /* CMP */
reg_value = s->cmp;
break;
case 4: /* CNT */
imx_epit_update_count(s);
reg_value = s->cnt;
break;
default:
IPRINTF("Bad offset %x\n", reg);
break;
}
DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(reg), reg_value);
return reg_value;
}
static void imx_epit_reload_compare_timer(IMXEPITState *s)
{
if ((s->cr & CR_OCIEN) && s->cmp) {
/* if the compare feature is on */
uint32_t tmp = imx_epit_update_count(s);
if (tmp > s->cmp) {
/* reinit the cmp timer if required */
ptimer_set_count(s->timer_cmp, tmp - s->cmp);
if ((s->cr & CR_EN)) {
/* Restart the cmp timer if required */
ptimer_run(s->timer_cmp, 0);
}
}
}
}
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMXEPITState *s = IMX_EPIT(opaque);
uint32_t reg = offset >> 2;
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg), (uint32_t)value);
switch (reg) {
case 0: /* CR */
s->cr = value & 0x03ffffff;
if (s->cr & CR_SWR) {
/* handle the reset */
imx_epit_reset(DEVICE(s));
} else {
imx_epit_set_freq(s);
}
if (s->freq && (s->cr & CR_EN)) {
if (s->cr & CR_ENMOD) {
if (s->cr & CR_RLD) {
ptimer_set_limit(s->timer_reload, s->lr, 1);
} else {
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
}
}
imx_epit_reload_compare_timer(s);
ptimer_run(s->timer_reload, 1);
} else {
/* stop both timers */
ptimer_stop(s->timer_reload);
ptimer_stop(s->timer_cmp);
}
break;
case 1: /* SR - ACK*/
/* writing 1 to OCIF clear the OCIF bit */
if (value & 0x01) {
s->sr = 0;
imx_epit_update_int(s);
}
break;
case 2: /* LR - set ticks */
s->lr = value;
if (s->cr & CR_RLD) {
/* Also set the limit if the LRD bit is set */
/* If IOVW bit is set then set the timer value */
ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
} else if (s->cr & CR_IOVW) {
/* If IOVW bit is set then set the timer value */
ptimer_set_count(s->timer_reload, s->lr);
}
imx_epit_reload_compare_timer(s);
break;
case 3: /* CMP */
s->cmp = value;
imx_epit_reload_compare_timer(s);
break;
default:
IPRINTF("Bad offset %x\n", reg);
break;
}
}
static void imx_epit_timeout(void *opaque)
{
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("\n");
if (!(s->cr & CR_EN)) {
return;
}
if (s->cr & CR_RLD) {
ptimer_set_limit(s->timer_reload, s->lr, 1);
} else {
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
}
if (s->cr & CR_OCIEN) {
/* if compare register is 0 then we handle the interrupt here */
if (s->cmp == 0) {
s->sr = 1;
imx_epit_update_int(s);
} else if (s->cmp <= s->lr) {
/* We should launch the compare register */
ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
ptimer_run(s->timer_cmp, 0);
} else {
IPRINTF("s->lr < s->cmp\n");
}
}
}
static void imx_epit_cmp(void *opaque)
{
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("\n");
ptimer_stop(s->timer_cmp);
/* compare register is not 0 */
if (s->cmp) {
s->sr = 1;
imx_epit_update_int(s);
}
}
void imx_timerp_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
{
IMXEPITState *pp;
DeviceState *dev;
dev = sysbus_create_simple(TYPE_IMX_EPIT, addr, irq);
pp = IMX_EPIT(dev);
pp->ccm = ccm;
}
static const MemoryRegionOps imx_epit_ops = {
.read = imx_epit_read,
.write = imx_epit_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_imx_timer_epit = {
.name = TYPE_IMX_EPIT,
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr, IMXEPITState),
VMSTATE_UINT32(sr, IMXEPITState),
VMSTATE_UINT32(lr, IMXEPITState),
VMSTATE_UINT32(cmp, IMXEPITState),
VMSTATE_UINT32(cnt, IMXEPITState),
VMSTATE_UINT32(freq, IMXEPITState),
VMSTATE_PTIMER(timer_reload, IMXEPITState),
VMSTATE_PTIMER(timer_cmp, IMXEPITState),
VMSTATE_END_OF_LIST()
}
};
static void imx_epit_realize(DeviceState *dev, Error **errp)
{
IMXEPITState *s = IMX_EPIT(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
QEMUBH *bh;
DPRINTF("\n");
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, &imx_epit_ops, s, TYPE_IMX_EPIT,
0x00001000);
sysbus_init_mmio(sbd, &s->iomem);
bh = qemu_bh_new(imx_epit_timeout, s);
s->timer_reload = ptimer_init(bh);
bh = qemu_bh_new(imx_epit_cmp, s);
s->timer_cmp = ptimer_init(bh);
}
static void imx_epit_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = imx_epit_realize;
dc->reset = imx_epit_reset;
dc->vmsd = &vmstate_imx_timer_epit;
dc->desc = "i.MX periodic timer";
}
static const TypeInfo imx_epit_info = {
.name = TYPE_IMX_EPIT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXEPITState),
.class_init = imx_epit_class_init,
};
static void imx_epit_register_types(void)
{
type_register_static(&imx_epit_info);
}
type_init(imx_epit_register_types)
hw/timer/imx_timer.c → hw/timer/imx_gpt.c
+4 -362
View File
@@ -1,5 +1,5 @@
/*
* IMX31 Timer
* IMX GPT Timer
*
* Copyright (c) 2008 OK Labs
* Copyright (c) 2011 NICTA Pty Ltd
@@ -12,6 +12,7 @@
*/
#include "hw/hw.h"
#include "qemu/bitops.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "hw/sysbus.h"
@@ -54,7 +55,6 @@
* (free-running timer from 0 to OCR1 or TIMER_MAX) .
*/
#define TIMER_MAX 0XFFFFFFFFUL
/* Control register. Not all of these bits have any effect (yet) */
@@ -148,6 +148,7 @@ static void imx_timerg_set_freq(IMXTimerGState *s)
freq = imx_clock_frequency(s->ccm, imx_timerg_clocks[clksrc]) / (1 + s->pr);
DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc, freq);
if (freq) {
ptimer_set_freq(s->timer, freq);
}
@@ -206,7 +207,7 @@ static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
{
IMXTimerGState *s = (IMXTimerGState *)opaque;
DPRINTF("g-read(offset=%x)", offset >> 2);
DPRINTF("g-read(offset=%x)", (unsigned int)(offset >> 2));
switch (offset >> 2) {
case 0: /* Control Register */
DPRINTF(" cr = %x\n", s->cr);
@@ -427,347 +428,6 @@ static int imx_timerg_init(SysBusDevice *dev)
return 0;
}
/*
* EPIT: Enhanced periodic interrupt timer
*/
#define CR_EN (1 << 0)
#define CR_ENMOD (1 << 1)
#define CR_OCIEN (1 << 2)
#define CR_RLD (1 << 3)
#define CR_PRESCALE_SHIFT (4)
#define CR_PRESCALE_MASK (0xfff)
#define CR_SWR (1 << 16)
#define CR_IOVW (1 << 17)
#define CR_DBGEN (1 << 18)
#define CR_WAITEN (1 << 19)
#define CR_DOZEN (1 << 20)
#define CR_STOPEN (1 << 21)
#define CR_CLKSRC_SHIFT (24)
#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
/*
* Exact clock frequencies vary from board to board.
* These are typical.
*/
static const IMXClk imx_timerp_clocks[] = {
0, /* 00 disabled */
IPG, /* 01 ipg_clk, ~532MHz */
IPG, /* 10 ipg_clk_highfreq */
CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
};
typedef struct {
SysBusDevice busdev;
ptimer_state *timer_reload;
ptimer_state *timer_cmp;
MemoryRegion iomem;
DeviceState *ccm;
uint32_t cr;
uint32_t sr;
uint32_t lr;
uint32_t cmp;
uint32_t cnt;
uint32_t freq;
qemu_irq irq;
} IMXTimerPState;
/*
* Update interrupt status
*/
static void imx_timerp_update(IMXTimerPState *s)
{
if (s->sr && (s->cr & CR_OCIEN)) {
qemu_irq_raise(s->irq);
} else {
qemu_irq_lower(s->irq);
}
}
static void set_timerp_freq(IMXTimerPState *s)
{
int clksrc;
unsigned prescaler;
uint32_t freq;
clksrc = (s->cr & CR_CLKSRC_MASK) >> CR_CLKSRC_SHIFT;
prescaler = 1 + ((s->cr >> CR_PRESCALE_SHIFT) & CR_PRESCALE_MASK);
freq = imx_clock_frequency(s->ccm, imx_timerp_clocks[clksrc]) / prescaler;
s->freq = freq;
DPRINTF("Setting ptimer frequency to %u\n", freq);
if (freq) {
ptimer_set_freq(s->timer_reload, freq);
ptimer_set_freq(s->timer_cmp, freq);
}
}
static void imx_timerp_reset(DeviceState *dev)
{
IMXTimerPState *s = container_of(dev, IMXTimerPState, busdev.qdev);
/*
* Soft reset doesn't touch some bits; hard reset clears them
*/
s->cr &= ~(CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
s->sr = 0;
s->lr = TIMER_MAX;
s->cmp = 0;
s->cnt = 0;
/* stop both timers */
ptimer_stop(s->timer_cmp);
ptimer_stop(s->timer_reload);
/* compute new frequency */
set_timerp_freq(s);
/* init both timers to TIMER_MAX */
ptimer_set_limit(s->timer_cmp, TIMER_MAX, 1);
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
if (s->freq && (s->cr & CR_EN)) {
/* if the timer is still enabled, restart it */
ptimer_run(s->timer_reload, 1);
}
}
static uint32_t imx_timerp_update_counts(IMXTimerPState *s)
{
s->cnt = ptimer_get_count(s->timer_reload);
return s->cnt;
}
static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
DPRINTF("p-read(offset=%x)", offset >> 2);
switch (offset >> 2) {
case 0: /* Control Register */
DPRINTF("cr %x\n", s->cr);
return s->cr;
case 1: /* Status Register */
DPRINTF("sr %x\n", s->sr);
return s->sr;
case 2: /* LR - ticks*/
DPRINTF("lr %x\n", s->lr);
return s->lr;
case 3: /* CMP */
DPRINTF("cmp %x\n", s->cmp);
return s->cmp;
case 4: /* CNT */
imx_timerp_update_counts(s);
DPRINTF(" cnt = %x\n", s->cnt);
return s->cnt;
}
IPRINTF("imx_timerp_read: Bad offset %x\n",
(int)offset >> 2);
return 0;
}
static void imx_reload_compare_timer(IMXTimerPState *s)
{
if ((s->cr & CR_OCIEN) && s->cmp) {
/* if the compare feature is on */
uint32_t tmp = imx_timerp_update_counts(s);
if (tmp > s->cmp) {
/* reinit the cmp timer if required */
ptimer_set_count(s->timer_cmp, tmp - s->cmp);
if ((s->cr & CR_EN)) {
/* Restart the cmp timer if required */
ptimer_run(s->timer_cmp, 0);
}
}
}
}
static void imx_timerp_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
DPRINTF("p-write(offset=%x, value = %x)\n", (unsigned int)offset >> 2,
(unsigned int)value);
switch (offset >> 2) {
case 0: /* CR */
s->cr = value & 0x03ffffff;
if (s->cr & CR_SWR) {
/* handle the reset */
imx_timerp_reset(&s->busdev.qdev);
} else {
set_timerp_freq(s);
}
if (s->freq && (s->cr & CR_EN)) {
if (s->cr & CR_ENMOD) {
if (s->cr & CR_RLD) {
ptimer_set_limit(s->timer_reload, s->lr, 1);
} else {
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
}
}
imx_reload_compare_timer(s);
ptimer_run(s->timer_reload, 1);
} else {
/* stop both timers */
ptimer_stop(s->timer_reload);
ptimer_stop(s->timer_cmp);
}
break;
case 1: /* SR - ACK*/
/* writing 1 to OCIF clear the OCIF bit */
if (value & 0x01) {
s->sr = 0;
imx_timerp_update(s);
}
break;
case 2: /* LR - set ticks */
s->lr = value;
if (s->cr & CR_RLD) {
/* Also set the limit if the LRD bit is set */
/* If IOVW bit is set then set the timer value */
ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
} else if (s->cr & CR_IOVW) {
/* If IOVW bit is set then set the timer value */
ptimer_set_count(s->timer_reload, s->lr);
}
imx_reload_compare_timer(s);
break;
case 3: /* CMP */
s->cmp = value;
imx_reload_compare_timer(s);
break;
default:
IPRINTF("imx_timerp_write: Bad offset %x\n",
(int)offset >> 2);
}
}
static void imx_timerp_reload(void *opaque)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
DPRINTF("imxp reload\n");
if (!(s->cr & CR_EN)) {
return;
}
if (s->cr & CR_RLD) {
ptimer_set_limit(s->timer_reload, s->lr, 1);
} else {
ptimer_set_limit(s->timer_reload, TIMER_MAX, 1);
}
if (s->cr & CR_OCIEN) {
/* if compare register is 0 then we handle the interrupt here */
if (s->cmp == 0) {
s->sr = 1;
imx_timerp_update(s);
} else if (s->cmp <= s->lr) {
/* We should launch the compare register */
ptimer_set_count(s->timer_cmp, s->lr - s->cmp);
ptimer_run(s->timer_cmp, 0);
} else {
IPRINTF("imxp reload: s->lr < s->cmp\n");
}
}
}
static void imx_timerp_cmp(void *opaque)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
DPRINTF("imxp compare\n");
ptimer_stop(s->timer_cmp);
/* compare register is not 0 */
if (s->cmp) {
s->sr = 1;
imx_timerp_update(s);
}
}
void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
{
IMXTimerPState *pp;
DeviceState *dev;
dev = sysbus_create_simple("imx_timerp", addr, irq);
pp = container_of(dev, IMXTimerPState, busdev.qdev);
pp->ccm = ccm;
}
static const MemoryRegionOps imx_timerp_ops = {
.read = imx_timerp_read,
.write = imx_timerp_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_imx_timerp = {
.name = "imx-timerp",
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr, IMXTimerPState),
VMSTATE_UINT32(sr, IMXTimerPState),
VMSTATE_UINT32(lr, IMXTimerPState),
VMSTATE_UINT32(cmp, IMXTimerPState),
VMSTATE_UINT32(cnt, IMXTimerPState),
VMSTATE_UINT32(freq, IMXTimerPState),
VMSTATE_PTIMER(timer_reload, IMXTimerPState),
VMSTATE_PTIMER(timer_cmp, IMXTimerPState),
VMSTATE_END_OF_LIST()
}
};
static int imx_timerp_init(SysBusDevice *dev)
{
IMXTimerPState *s = FROM_SYSBUS(IMXTimerPState, dev);
QEMUBH *bh;
DPRINTF("imx_timerp_init\n");
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &imx_timerp_ops,
s, "imxp-timer",
0x00001000);
sysbus_init_mmio(dev, &s->iomem);
bh = qemu_bh_new(imx_timerp_reload, s);
s->timer_reload = ptimer_init(bh);
bh = qemu_bh_new(imx_timerp_cmp, s);
s->timer_cmp = ptimer_init(bh);
return 0;
}
void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
@@ -790,23 +450,6 @@ static void imx_timerg_class_init(ObjectClass *klass, void *data)
dc->desc = "i.MX general timer";
}
static void imx_timerp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = imx_timerp_init;
dc->vmsd = &vmstate_imx_timerp;
dc->reset = imx_timerp_reset;
dc->desc = "i.MX periodic timer";
}
static const TypeInfo imx_timerp_info = {
.name = "imx_timerp",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXTimerPState),
.class_init = imx_timerp_class_init,
};
static const TypeInfo imx_timerg_info = {
.name = "imx_timerg",
.parent = TYPE_SYS_BUS_DEVICE,
@@ -816,7 +459,6 @@ static const TypeInfo imx_timerg_info = {
static void imx_timer_register_types(void)
{
type_register_static(&imx_timerp_info);
type_register_static(&imx_timerg_info);
}