mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
- Many fixes from the floor as usual - New "edu" device (v1->v2: fix 32-bit compilation) - Disabling HLE and RTM on Haswell & Broadwell - kvm_stat updates - Added --enable-modules to Travis, in preparation for switching the default # gpg: Signature made Mon 26 Jan 2015 11:44:40 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: kvm_stat: Add RESET support for perf event ioctl target-i386: Disable HLE and RTM on Haswell & Broadwell sparse: Fix build with sparse on .S files exec: fix madvise of NULL pointer .travis.yml: Add "--enable-modules" apic: do not dereference pointer before it is checked for NULL kvm_stat: Print errno when syscall to perf_event_open() fails kvm_stat: Update exit reasons to the latest defintion kvm_stat: Add aarch64 support hw: misc, add educational driver vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR* qemu-timer: introduce timer_deinit qemu-timer: add timer_init and timer_init_ns/us/ms target-i386: make xmm_regs 512-bit wide target-i386: use vmstate_offset_sub_array for AVX registers tests/multiboot: Add test for modules multiboot: Fix offset of bootloader name tests/multiboot: Update reference output pc: fix KVM features in pc-1.3 and earlier machine types Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
@@ -98,3 +98,6 @@ matrix:
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EXTRA_PKGS="liblttng-ust-dev liburcu-dev"
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EXTRA_CONFIG="--enable-trace-backends=ust"
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compiler: gcc
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- env: TARGETS=i386-softmmu,x86_64-softmmu
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EXTRA_CONFIG="--enable-modules"
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compiler: gcc
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@@ -599,6 +599,11 @@ F: hw/net/opencores_eth.c
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||||
Devices
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-------
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EDU
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||||
M: Jiri Slaby <jslaby@suse.cz>
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S: Maintained
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F: hw/misc/edu.c
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IDE
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M: Kevin Wolf <kwolf@redhat.com>
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M: Stefan Hajnoczi <stefanha@redhat.com>
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@@ -4938,6 +4938,7 @@ echo "QEMU_CFLAGS=$QEMU_CFLAGS" >> $config_host_mak
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echo "QEMU_INCLUDES=$QEMU_INCLUDES" >> $config_host_mak
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if test "$sparse" = "yes" ; then
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echo "CC := REAL_CC=\"\$(CC)\" cgcc" >> $config_host_mak
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echo "CPP := REAL_CC=\"\$(CPP)\" cgcc" >> $config_host_mak
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echo "CXX := REAL_CC=\"\$(CXX)\" cgcc" >> $config_host_mak
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echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak
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echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak
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@@ -32,3 +32,4 @@ CONFIG_PCI_TESTDEV=y
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CONFIG_NVME_PCI=y
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CONFIG_SD=y
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CONFIG_SDHCI=y
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CONFIG_EDU=y
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@@ -0,0 +1,110 @@
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||||
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EDU device
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==========
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Copyright (c) 2014-2015 Jiri Slaby
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This document is licensed under the GPLv2 (or later).
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This is an educational device for writing (kernel) drivers. Its original
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intention was to support the Linux kernel lectures taught at the Masaryk
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University. Students are given this virtual device and are expected to write a
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driver with I/Os, IRQs, DMAs and such.
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The devices behaves very similar to the PCI bridge present in the COMBO6 cards
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developed under the Liberouter wings. Both PCI device ID and PCI space is
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inherited from that device.
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Command line switches:
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-device edu[,dma_mask=mask]
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dma_mask makes the virtual device work with DMA addresses with the given
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mask. For educational purposes, the device supports only 28 bits (256 MiB)
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by default. Students shall set dma_mask for the device in the OS driver
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properly.
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PCI specs
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---------
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PCI ID: 1234:11e8
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PCI Region 0:
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I/O memory, 1 MB in size. Users are supposed to communicate with the card
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through this memory.
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MMIO area spec
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--------------
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Only size == 4 accesses are allowed for addresses < 0x80. size == 4 or
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size == 8 for the rest.
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0x00 (RO) : identification (0xRRrr00edu)
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RR -- major version
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rr -- minor version
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0x04 (RW) : card liveness check
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It is a simple value inversion (~ C operator).
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0x08 (RW) : factorial computation
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The stored value is taken and factorial of it is put back here.
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This happens only after factorial bit in the status register (0x20
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below) is cleared.
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0x20 (RW) : status register, bitwise OR
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0x01 -- computing factorial (RO)
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0x80 -- raise interrupt 0x01 after finishing factorial computation
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0x24 (RO) : interrupt status register
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It contains values which raised the interrupt (see interrupt raise
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register below).
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0x60 (WO) : interrupt raise register
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Raise an interrupt. The value will be put to the interrupt status
|
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register (using bitwise OR).
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0x64 (WO) : interrupt acknowledge register
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Clear an interrupt. The value will be cleared from the interrupt
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status register. This needs to be done from the ISR to stop
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generating interrupts.
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0x80 (RW) : DMA source address
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Where to perform the DMA from.
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0x88 (RW) : DMA destination address
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Where to perform the DMA to.
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0x90 (RW) : DMA transfer count
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The size of the area to perform the DMA on.
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0x98 (RW) : DMA command register, bitwise OR
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0x01 -- start transfer
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0x02 -- direction (0: from RAM to EDU, 1: from EDU to RAM)
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0x04 -- raise interrupt 0x100 after finishing the DMA
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||||
IRQ controller
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||||
--------------
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||||
An IRQ is generated when written to the interrupt raise register. The value
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appears in interrupt status register when the interrupt is raised and has to
|
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be written to the interrupt acknowledge register to lower it.
|
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|
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DMA controller
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--------------
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One has to specify, source, destination, size, and start the transfer. One
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4096 bytes long buffer at offset 0x40000 is available in the EDU device. I.e.
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one can perform DMA to/from this space when programmed properly.
|
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|
||||
Example of transferring a 100 byte block to and from the buffer using a given
|
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PCI address 'addr':
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addr -> DMA source address
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0x40000 -> DMA destination address
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100 -> DMA transfer count
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1 -> DMA command register
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while (DMA command register & 1)
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;
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0x40000 -> DMA source address
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addr+100 -> DMA destination address
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100 -> DMA transfer count
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3 -> DMA command register
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while (DMA command register & 1)
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;
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@@ -1386,12 +1386,13 @@ static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp)
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cpu_physical_memory_set_dirty_range(new_block->offset,
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new_block->used_length);
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qemu_ram_setup_dump(new_block->host, new_block->max_length);
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qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
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qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
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if (kvm_enabled()) {
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kvm_setup_guest_memory(new_block->host, new_block->max_length);
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if (new_block->host) {
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qemu_ram_setup_dump(new_block->host, new_block->max_length);
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qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
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qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
|
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if (kvm_enabled()) {
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kvm_setup_guest_memory(new_block->host, new_block->max_length);
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}
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}
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return new_block->offset;
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||||
+1
-1
@@ -166,7 +166,7 @@ const VMStateDescription vmstate_ich9_pm = {
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VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
|
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VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
|
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VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
|
||||
VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
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VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
|
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VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
|
||||
VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
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VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
|
||||
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||||
+1
-1
@@ -285,7 +285,7 @@ static const VMStateDescription vmstate_acpi = {
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VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
|
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VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
|
||||
VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
|
||||
VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
|
||||
VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
|
||||
VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
|
||||
VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
|
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VMSTATE_STRUCT_TEST(
|
||||
|
||||
+1
-1
@@ -306,7 +306,7 @@ static const VMStateDescription vmstate_stellaris_gptm = {
|
||||
VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
|
||||
VMSTATE_UINT32(rtc, gptm_state),
|
||||
VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
|
||||
VMSTATE_TIMER_ARRAY(timer, gptm_state, 2),
|
||||
VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
+1
-1
@@ -791,7 +791,7 @@ static const VMStateDescription vmstate_fdc_result_timer = {
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_TIMER(result_timer, FDCtrl),
|
||||
VMSTATE_TIMER_PTR(result_timer, FDCtrl),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
@@ -520,7 +520,7 @@ static const VMStateDescription vmstate_cadence_uart = {
|
||||
VMSTATE_UINT32(rx_count, UartState),
|
||||
VMSTATE_UINT32(tx_count, UartState),
|
||||
VMSTATE_UINT32(rx_wpos, UartState),
|
||||
VMSTATE_TIMER(fifo_trigger_handle, UartState),
|
||||
VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
+2
-2
@@ -730,7 +730,7 @@ const VMStateDescription vmstate_serial_fifo_timeout_timer = {
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.version_id = 1,
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||||
.minimum_version_id = 1,
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||||
.fields = (VMStateField[]) {
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||||
VMSTATE_TIMER(fifo_timeout_timer, SerialState),
|
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VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
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||||
@@ -763,7 +763,7 @@ const VMStateDescription vmstate_serial_poll = {
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.minimum_version_id = 1,
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||||
.fields = (VMStateField[]) {
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||||
VMSTATE_INT32(poll_msl, SerialState),
|
||||
VMSTATE_TIMER(modem_status_poll, SerialState),
|
||||
VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
+1
-1
@@ -214,7 +214,7 @@ const VMStateDescription vmstate_ptimer = {
|
||||
VMSTATE_INT64(period, ptimer_state),
|
||||
VMSTATE_INT64(last_event, ptimer_state),
|
||||
VMSTATE_INT64(next_event, ptimer_state),
|
||||
VMSTATE_TIMER(timer, ptimer_state),
|
||||
VMSTATE_TIMER_PTR(timer, ptimer_state),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
+1
-1
@@ -286,7 +286,7 @@ static const VMStateDescription vmstate_pl330 = {
|
||||
PL330Queue),
|
||||
VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
|
||||
PL330Queue),
|
||||
VMSTATE_TIMER(timer, PL330State),
|
||||
VMSTATE_TIMER_PTR(timer, PL330State),
|
||||
VMSTATE_UINT32(inten, PL330State),
|
||||
VMSTATE_UINT32(int_status, PL330State),
|
||||
VMSTATE_UINT32(ev_status, PL330State),
|
||||
|
||||
+9
-7
@@ -156,6 +156,7 @@ int load_multiboot(FWCfgState *fw_cfg,
|
||||
MultibootState mbs;
|
||||
uint8_t bootinfo[MBI_SIZE];
|
||||
uint8_t *mb_bootinfo_data;
|
||||
uint32_t cmdline_len;
|
||||
|
||||
/* Ok, let's see if it is a multiboot image.
|
||||
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
|
||||
@@ -258,27 +259,28 @@ int load_multiboot(FWCfgState *fw_cfg,
|
||||
mbs.offset_mbinfo = mbs.mb_buf_size;
|
||||
|
||||
/* Calculate space for cmdlines, bootloader name, and mb_mods */
|
||||
mbs.mb_buf_size += strlen(kernel_filename) + 1;
|
||||
mbs.mb_buf_size += strlen(kernel_cmdline) + 1;
|
||||
mbs.mb_buf_size += strlen(bootloader_name) + 1;
|
||||
cmdline_len = strlen(kernel_filename) + 1;
|
||||
cmdline_len += strlen(kernel_cmdline) + 1;
|
||||
if (initrd_filename) {
|
||||
const char *r = initrd_filename;
|
||||
mbs.mb_buf_size += strlen(r) + 1;
|
||||
cmdline_len += strlen(r) + 1;
|
||||
mbs.mb_mods_avail = 1;
|
||||
while (*(r = get_opt_value(NULL, 0, r))) {
|
||||
mbs.mb_mods_avail++;
|
||||
r++;
|
||||
}
|
||||
mbs.mb_buf_size += MB_MOD_SIZE * mbs.mb_mods_avail;
|
||||
}
|
||||
|
||||
mbs.mb_buf_size += cmdline_len;
|
||||
mbs.mb_buf_size += MB_MOD_SIZE * mbs.mb_mods_avail;
|
||||
mbs.mb_buf_size += strlen(bootloader_name) + 1;
|
||||
|
||||
mbs.mb_buf_size = TARGET_PAGE_ALIGN(mbs.mb_buf_size);
|
||||
|
||||
/* enlarge mb_buf to hold cmdlines, bootloader, mb-info structs */
|
||||
mbs.mb_buf = g_realloc(mbs.mb_buf, mbs.mb_buf_size);
|
||||
mbs.offset_cmdlines = mbs.offset_mbinfo + mbs.mb_mods_avail * MB_MOD_SIZE;
|
||||
mbs.offset_bootloader = mbs.offset_cmdlines + strlen(kernel_filename) + 1
|
||||
+ strlen(kernel_cmdline) + 1;
|
||||
mbs.offset_bootloader = mbs.offset_cmdlines + cmdline_len;
|
||||
|
||||
if (initrd_filename) {
|
||||
char *next_initrd, not_last;
|
||||
|
||||
+6
-2
@@ -328,6 +328,10 @@ static void pc_compat_2_2(MachineState *machine)
|
||||
x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
|
||||
x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,
|
||||
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,
|
||||
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
|
||||
}
|
||||
|
||||
static void pc_compat_2_1(MachineState *machine)
|
||||
@@ -406,7 +410,7 @@ static void pc_compat_1_3(MachineState *machine)
|
||||
static void pc_compat_1_2(MachineState *machine)
|
||||
{
|
||||
pc_compat_1_3(machine);
|
||||
x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI);
|
||||
x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, 1 << KVM_FEATURE_PV_EOI);
|
||||
}
|
||||
|
||||
static void pc_init_pci_2_2(MachineState *machine)
|
||||
@@ -483,7 +487,7 @@ static void pc_init_isa(MachineState *machine)
|
||||
if (!machine->cpu_model) {
|
||||
machine->cpu_model = "486";
|
||||
}
|
||||
x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI);
|
||||
x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, 1 << KVM_FEATURE_PV_EOI);
|
||||
enable_compat_apic_id_mode();
|
||||
pc_init1(machine, 0, 1);
|
||||
}
|
||||
|
||||
@@ -307,6 +307,10 @@ static void pc_compat_2_2(MachineState *machine)
|
||||
x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
|
||||
x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,
|
||||
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
|
||||
x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,
|
||||
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
|
||||
}
|
||||
|
||||
static void pc_compat_2_1(MachineState *machine)
|
||||
|
||||
+1
-1
@@ -455,7 +455,7 @@ static const VMStateDescription vmstate_lm_kbd = {
|
||||
VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
|
||||
VMSTATE_UINT8(pwm.faddr, LM823KbdState),
|
||||
VMSTATE_BUFFER(pwm.addr, LM823KbdState),
|
||||
VMSTATE_TIMER_ARRAY(pwm.tm, LM823KbdState, 3),
|
||||
VMSTATE_TIMER_PTR_ARRAY(pwm.tm, LM823KbdState, 3),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
@@ -177,13 +177,14 @@ bool apic_next_timer(APICCommonState *s, int64_t current_time)
|
||||
|
||||
void apic_init_reset(DeviceState *dev)
|
||||
{
|
||||
APICCommonState *s = APIC_COMMON(dev);
|
||||
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
|
||||
APICCommonState *s;
|
||||
APICCommonClass *info;
|
||||
int i;
|
||||
|
||||
if (!s) {
|
||||
if (!dev) {
|
||||
return;
|
||||
}
|
||||
s = APIC_COMMON(dev);
|
||||
s->tpr = 0;
|
||||
s->spurious_vec = 0xff;
|
||||
s->log_dest = 0;
|
||||
@@ -208,6 +209,7 @@ void apic_init_reset(DeviceState *dev)
|
||||
}
|
||||
s->timer_expiry = -1;
|
||||
|
||||
info = APIC_COMMON_GET_CLASS(s);
|
||||
if (info->reset) {
|
||||
info->reset(s);
|
||||
}
|
||||
|
||||
@@ -450,7 +450,7 @@ static const VMStateDescription vmstate_nvic = {
|
||||
VMSTATE_UINT32(systick.control, nvic_state),
|
||||
VMSTATE_UINT32(systick.reload, nvic_state),
|
||||
VMSTATE_INT64(systick.tick, nvic_state),
|
||||
VMSTATE_TIMER(systick.timer, nvic_state),
|
||||
VMSTATE_TIMER_PTR(systick.timer, nvic_state),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user