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target/riscv: Set disassemble_info::endian value in disas_set_info()

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Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-8-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-03-06 15:46:18 +01:00
parent 724bac4190
commit 0a8bfcbe7c
1 changed files with 9 additions and 0 deletions
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target/riscv/cpu.c
+9
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@@ -1152,6 +1152,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
CPURISCVState *env = &cpu->env;
info->target_info = &cpu->cfg;
/*
* A couple of bits in MSTATUS set the endianness:
* - MSTATUS_UBE (User-mode),
* - MSTATUS_SBE (Supervisor-mode),
* - MSTATUS_MBE (Machine-mode)
* but we don't implement that yet.
*/
info->endian = BFD_ENDIAN_LITTLE;
switch (env->xl) {
case MXL_RV32:
info->print_insn = print_insn_riscv32;