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Merge tag 'single-binary-20241015' of https://github.com/philmd/qemu into staging

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Remove some target-specific endianness knowledge from target/.

For MIPS, propagate endianness at the board level, using QOM property.

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* tag 'single-binary-20241015' of https://github.com/philmd/qemu: (33 commits)
  hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
  hw/mips/cps: Set the vCPU 'cpu-big-endian' property
  target/mips: Expose MIPSCPU::is_big_endian property
  target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
  target/mips: Use gen_op_addr_addi() when possible
  target/mips: Have gen_addiupc() expand $pc during translation
  target/mips: Replace MO_TE by mo_endian()
  target/mips: Introduce mo_endian() helper
  target/mips: Remove unused MEMOP_IDX() macro
  target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
  target/mips: Explode MO_TExx -> MO_TE | MO_xx
  target/mips: Factor mo_endian_rev() out of MXU code
  target/mips: Convert mips16e decr_and_load/store() macros to functions
  target/mips: Replace MO_TE by  mo_endian_env() in get_pte()
  target/mips: Introduce mo_endian_env() helper
  target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
  target/mips: Declare mips_env_is_bigendian() in 'internal.h'
  hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry
  target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
  target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2024-10-16 20:22:08 +01:00
parent f774a67750 3e8f019be7
commit 08ae519ab8
35 changed files with 370 additions and 392 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/i386/multiboot.c
+19 -20
View File
@@ -133,9 +133,9 @@ static void mb_add_mod(MultibootState *s,
p = (char *)s->mb_buf + s->offset_mbinfo + MB_MOD_SIZE * s->mb_mods_count;
stl_p(p + MB_MOD_START, start);
stl_p(p + MB_MOD_END, end);
stl_p(p + MB_MOD_CMDLINE, cmdline_phys);
stl_le_p(p + MB_MOD_START, start);
stl_le_p(p + MB_MOD_END, end);
stl_le_p(p + MB_MOD_CMDLINE, cmdline_phys);
mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx,
s->mb_mods_count, start, end);
@@ -168,9 +168,9 @@ int load_multiboot(X86MachineState *x86ms,
/* Ok, let's see if it is a multiboot image.
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
for (i = 0; i < (8192 - 48); i += 4) {
if (ldl_p(header+i) == 0x1BADB002) {
uint32_t checksum = ldl_p(header+i+8);
flags = ldl_p(header+i+4);
if (ldl_le_p(header + i) == 0x1BADB002) {
uint32_t checksum = ldl_le_p(header + i + 8);
flags = ldl_le_p(header + i + 4);
checksum += flags;
checksum += (uint32_t)0x1BADB002;
if (!checksum) {
@@ -223,11 +223,11 @@ int load_multiboot(X86MachineState *x86ms,
mb_kernel_size, (size_t)mh_entry_addr);
} else {
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
uint32_t mh_header_addr = ldl_p(header+i+12);
uint32_t mh_load_end_addr = ldl_p(header+i+20);
uint32_t mh_bss_end_addr = ldl_p(header+i+24);
uint32_t mh_header_addr = ldl_le_p(header + i + 12);
uint32_t mh_load_end_addr = ldl_le_p(header + i + 20);
uint32_t mh_bss_end_addr = ldl_le_p(header + i + 24);
mh_load_addr = ldl_p(header+i+16);
mh_load_addr = ldl_le_p(header + i + 16);
if (mh_header_addr < mh_load_addr) {
error_report("invalid load_addr address");
exit(1);
@@ -239,7 +239,7 @@ int load_multiboot(X86MachineState *x86ms,
uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
uint32_t mb_load_size = 0;
mh_entry_addr = ldl_p(header+i+28);
mh_entry_addr = ldl_le_p(header + i + 28);
if (mh_load_end_addr) {
if (mh_load_end_addr < mh_load_addr) {
@@ -364,22 +364,21 @@ int load_multiboot(X86MachineState *x86ms,
/* Commandline support */
kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline);
stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name));
stl_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo);
stl_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */
stl_le_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline));
stl_le_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs,
bootloader_name));
stl_le_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo);
stl_le_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */
/* the kernel is where we want it to be now */
stl_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY
stl_le_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY
| MULTIBOOT_FLAGS_BOOT_DEVICE
| MULTIBOOT_FLAGS_CMDLINE
| MULTIBOOT_FLAGS_MODULES
| MULTIBOOT_FLAGS_MMAP
| MULTIBOOT_FLAGS_BOOTLOADER);
stl_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */
stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP);
stl_le_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */
stl_le_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP);
mb_debug("multiboot: entry_addr = %#x", mh_entry_addr);
mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys);
hw/i386/x86-common.c
+13 -13
View File
@@ -586,7 +586,7 @@ static bool load_elfboot(const char *kernel_filename,
uint64_t elf_low, elf_high;
int kernel_size;
if (ldl_p(header) != 0x464c457f) {
if (ldl_le_p(header) != 0x464c457f) {
return false; /* no elfboot */
}
@@ -669,8 +669,8 @@ void x86_load_linux(X86MachineState *x86ms,
* kernel protocol version.
* Please see https://www.kernel.org/doc/Documentation/x86/boot.txt
*/
if (ldl_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ {
protocol = lduw_p(header + 0x206);
if (ldl_le_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ {
protocol = lduw_le_p(header + 0x206);
} else {
/*
* This could be a multiboot kernel. If it is, let's stop treating it
@@ -762,7 +762,7 @@ void x86_load_linux(X86MachineState *x86ms,
/* highest address for loading the initrd */
if (protocol >= 0x20c &&
lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
lduw_le_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
/*
* Linux has supported initrd up to 4 GB for a very long time (2007,
* long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
@@ -781,7 +781,7 @@ void x86_load_linux(X86MachineState *x86ms,
*/
initrd_max = UINT32_MAX;
} else if (protocol >= 0x203) {
initrd_max = ldl_p(header + 0x22c);
initrd_max = ldl_le_p(header + 0x22c);
} else {
initrd_max = 0x37ffffff;
}
@@ -797,10 +797,10 @@ void x86_load_linux(X86MachineState *x86ms,
sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1;
if (protocol >= 0x202) {
stl_p(header + 0x228, cmdline_addr);
stl_le_p(header + 0x228, cmdline_addr);
} else {
stw_p(header + 0x20, 0xA33F);
stw_p(header + 0x22, cmdline_addr - real_addr);
stw_le_p(header + 0x20, 0xA33F);
stw_le_p(header + 0x22, cmdline_addr - real_addr);
}
/* handle vga= parameter */
@@ -824,7 +824,7 @@ void x86_load_linux(X86MachineState *x86ms,
exit(1);
}
}
stw_p(header + 0x1fa, video_mode);
stw_le_p(header + 0x1fa, video_mode);
}
/* loader type */
@@ -839,7 +839,7 @@ void x86_load_linux(X86MachineState *x86ms,
/* heap */
if (protocol >= 0x201) {
header[0x211] |= 0x80; /* CAN_USE_HEAP */
stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
stw_le_p(header + 0x224, cmdline_addr - real_addr - 0x200);
}
/* load initrd */
@@ -879,8 +879,8 @@ void x86_load_linux(X86MachineState *x86ms,
sev_load_ctx.initrd_data = initrd_data;
sev_load_ctx.initrd_size = initrd_size;
stl_p(header + 0x218, initrd_addr);
stl_p(header + 0x21c, initrd_size);
stl_le_p(header + 0x218, initrd_addr);
stl_le_p(header + 0x21c, initrd_size);
}
/* load kernel and setup */
@@ -926,7 +926,7 @@ void x86_load_linux(X86MachineState *x86ms,
kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
kernel = g_realloc(kernel, kernel_size);
stq_p(header + 0x250, prot_addr + setup_data_offset);
stq_le_p(header + 0x250, prot_addr + setup_data_offset);
setup_data = (struct setup_data *)(kernel + setup_data_offset);
setup_data->next = 0;
hw/mips/cps.c
+4
View File
@@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
CPUMIPSState *env = &cpu->env;
object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian,
&error_abort);
/* All VPs are halted on reset. Leave powering up to CPC. */
object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
&error_abort);
@@ -167,6 +170,7 @@ static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false),
DEFINE_PROP_END_OF_LIST()
};
hw/mips/fuloong2e.c
+1 -1
View File
@@ -229,7 +229,7 @@ static void mips_fuloong2e_init(MachineState *machine)
clock_set_hz(cpuclk, 533080000); /* ~533 MHz */
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
hw/mips/jazz.c
+2 -1
View File
@@ -212,7 +212,8 @@ static void mips_jazz_init(MachineState *machine,
* ext_clk[jazz_model].pll_mult);
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk,
TARGET_BIG_ENDIAN);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
hw/mips/loongson3_virt.c
+1 -1
View File
@@ -567,7 +567,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
int ip;
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
hw/mips/malta.c
+4 -1
View File
@@ -1034,7 +1034,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
int i;
for (i = 0; i < ms->smp.cpus; i++) {
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
TARGET_BIG_ENDIAN);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@@ -1054,6 +1055,8 @@ static void create_cps(MachineState *ms, MaltaState *s,
object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
&error_fatal);
object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian",
TARGET_BIG_ENDIAN, &error_abort);
object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
&error_fatal);
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
hw/mips/mipssim.c
+2 -1
View File
@@ -160,7 +160,8 @@ mips_mipssim_init(MachineState *machine)
#endif
/* Init CPUs. */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk,
TARGET_BIG_ENDIAN);
env = &cpu->env;
reset_info = g_new0(ResetData, 1);
hw/xtensa/xtfpga.c
+7 -5
View File
@@ -415,8 +415,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
}
}
if (entry_point != env->pc) {
uint8_t boot[] = {
#if TARGET_BIG_ENDIAN
uint8_t boot_be[] = {
0x60, 0x00, 0x08, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
@@ -425,7 +424,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
0x0a, 0x00, 0x00, /* jx a0 */
#else
};
uint8_t boot_le[] = {
0x06, 0x02, 0x00, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
@@ -434,14 +434,16 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
0xa0, 0x00, 0x00, /* jx a0 */
#endif
};
const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be)
: sizeof(boot_le);
uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le;
uint32_t entry_pc = tswap32(entry_point);
uint32_t entry_a2 = tswap32(tagptr);
memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
cpu_physical_memory_write(env->pc, boot, sizeof(boot));
cpu_physical_memory_write(env->pc, boot, boot_sz);
}
} else {
if (flash) {
include/exec/memop.h
-6
View File
@@ -164,12 +164,6 @@ static inline MemOp size_memop(unsigned size)
return (MemOp)ctz32(size);
}
/* Big endianness from MemOp. */
static inline bool memop_big_endian(MemOp op)
{
return (op & MO_BSWAP) == MO_BE;
}
/**
* memop_alignment_bits:
* @memop: MemOp value
include/exec/tswap.h
+1 -1
View File
@@ -28,7 +28,7 @@ bool target_words_bigendian(void);
#ifdef COMPILING_PER_TARGET
#define target_needs_bswap() (HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN)
#else
#define target_needs_bswap() (target_words_bigendian() != HOST_BIG_ENDIAN)
#define target_needs_bswap() (HOST_BIG_ENDIAN != target_words_bigendian())
#endif /* COMPILING_PER_TARGET */
static inline uint16_t tswap16(uint16_t s)
include/gdbstub/helpers.h
+4
View File
@@ -95,9 +95,13 @@ static inline uint8_t *gdb_get_reg_ptr(GByteArray *buf, int len)
#if TARGET_LONG_BITS == 64
#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val)
#define ldtul_p(addr) ldq_p(addr)
#define ldtul_le_p(addr) ldq_le_p(addr)
#define ldtul_be_p(addr) ldq_be_p(addr)
#else
#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val)
#define ldtul_p(addr) ldl_p(addr)
#define ldtul_le_p(addr) ldl_le_p(addr)
#define ldtul_be_p(addr) ldl_be_p(addr)
#endif
#endif /* _GDBSTUB_HELPERS_H_ */
include/hw/mips/cps.h
+1
View File
@@ -38,6 +38,7 @@ struct MIPSCPSState {
uint32_t num_vp;
uint32_t num_irq;
char *cpu_type;
bool cpu_is_bigendian;
MemoryRegion container;
MIPSGCRState gcr;
include/qemu/bswap.h
+2
View File
@@ -140,6 +140,8 @@ CPU_CONVERT(le, 16, uint16_t)
CPU_CONVERT(le, 32, uint32_t)
CPU_CONVERT(le, 64, uint64_t)
#undef CPU_CONVERT
/*
* Same as cpu_to_le{16,32,64}, except that gcc will figure the result is
* a compile-time constant if you pass in a constant. So this can be
linux-user/i386/signal.c
+2 -2
View File
@@ -754,8 +754,8 @@ static bool restore_sigcontext(CPUX86State *env, struct target_sigcontext *sc)
env->eip = tswapl(sc->rip);
#endif
cpu_x86_load_seg(env, R_CS, lduw_p(&sc->cs) | 3);
cpu_x86_load_seg(env, R_SS, lduw_p(&sc->ss) | 3);
cpu_x86_load_seg(env, R_CS, lduw_le_p(&sc->cs) | 3);
cpu_x86_load_seg(env, R_SS, lduw_le_p(&sc->ss) | 3);
tmpflags = tswapl(sc->eflags);
env->eflags = (env->eflags & ~0x40DD5) | (tmpflags & 0x40DD5);
target/alpha/gdbstub.c
+1 -1
View File
@@ -59,7 +59,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUAlphaState *env = cpu_env(cs);
target_ulong tmp = ldtul_p(mem_buf);
target_ulong tmp = ldq_le_p(mem_buf);
CPU_DoubleU d;
switch (n) {
target/avr/gdbstub.c
+2 -2
View File
@@ -69,13 +69,13 @@ int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
/* SP */
if (n == 33) {
env->sp = lduw_p(mem_buf);
env->sp = lduw_le_p(mem_buf);
return 2;
}
/* PC */
if (n == 34) {
env->pc_w = ldl_p(mem_buf) / 2;
env->pc_w = ldl_le_p(mem_buf) / 2;
return 4;
}
target/hexagon/gdbstub.c
+5 -5
View File
@@ -52,7 +52,7 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUHexagonState *env = cpu_env(cs);
if (n == HEX_REG_P3_0_ALIASED) {
uint32_t p3_0 = ldtul_p(mem_buf);
uint32_t p3_0 = ldl_le_p(mem_buf);
for (int i = 0; i < NUM_PREGS; i++) {
env->pred[i] = extract32(p3_0, i * 8, 8);
}
@@ -60,14 +60,14 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
if (n < TOTAL_PER_THREAD_REGS) {
env->gpr[n] = ldtul_p(mem_buf);
env->gpr[n] = ldl_le_p(mem_buf);
return sizeof(target_ulong);
}
n -= TOTAL_PER_THREAD_REGS;
if (n < NUM_PREGS) {
env->pred[n] = ldtul_p(mem_buf) & 0xff;
env->pred[n] = ldl_le_p(mem_buf) & 0xff;
return sizeof(uint8_t);
}
@@ -117,7 +117,7 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
{
int i;
for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
env->VRegs[n].uw[i] = ldtul_p(mem_buf);
env->VRegs[n].uw[i] = ldl_le_p(mem_buf);
mem_buf += 4;
}
return MAX_VEC_SIZE_BYTES;
@@ -127,7 +127,7 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
{
int i;
for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
env->QRegs[n].uw[i] = ldtul_p(mem_buf);
env->QRegs[n].uw[i] = ldl_le_p(mem_buf);
mem_buf += 4;
}
return MAX_VEC_SIZE_BYTES / 8;
target/loongarch/gdbstub.c
+4 -4
View File
@@ -67,10 +67,10 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
int length = 0;
if (is_la64(env)) {
tmp = ldq_p(mem_buf);
tmp = ldq_le_p(mem_buf);
read_length = 8;
} else {
tmp = ldl_p(mem_buf);
tmp = ldl_le_p(mem_buf);
read_length = 4;
}
@@ -106,13 +106,13 @@ static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
int length = 0;
if (0 <= n && n < 32) {
env->fpr[n].vreg.D(0) = ldq_p(mem_buf);
env->fpr[n].vreg.D(0) = ldq_le_p(mem_buf);
length = 8;
} else if (32 <= n && n < 40) {
env->cf[n - 32] = ldub_p(mem_buf);
length = 1;
} else if (n == 40) {
env->fcsr0 = ldl_p(mem_buf);
env->fcsr0 = ldl_le_p(mem_buf);
length = 4;
}
return length;
target/mips/cpu.c
+12 -5
View File
@@ -200,10 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
env->CP0_Config0 = env->cpu_model->CP0_Config0;
#if TARGET_BIG_ENDIAN
env->CP0_Config0 |= (1 << CP0C0_BE);
#endif
env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
CP0C0_BE, 1, cpu->is_big_endian);
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
@@ -541,6 +539,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
};
#endif
static Property mips_cpu_properties[] = {
DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN),
DEFINE_PROP_END_OF_LIST(),
};
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -571,6 +574,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_props(dc, mips_cpu_properties);
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
@@ -639,12 +643,15 @@ static void mips_cpu_register_types(void)
type_init(mips_cpu_register_types)
/* Could be used by generic CPU object */
MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk,
bool is_big_endian)
{
DeviceState *cpu;
cpu = DEVICE(object_new(cpu_type));
qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian,
&error_abort);
qdev_realize(cpu, NULL, &error_abort);
return MIPS_CPU(cpu);

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