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Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging

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First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

# gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits)
  hw/intc: sifive_plic: Fix the pending register range check
  hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
  hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
  hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
  hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
  hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
  hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
  hw/intc: sifive_plic: Update "num-sources" property default value
  hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
  hw/intc: sifive_plic: Improve robustness of the PLIC config parser
  hw/intc: sifive_plic: Drop PLICMode_H
  hw/riscv: spike: Remove misleading comments
  hw/riscv: Sort machines Kconfig options in alphabetical order
  hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
  hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
  hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
  RISC-V: Add Zawrs ISA extension support
  target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
  target/riscv: Simplify helper_sret() a little bit
  target/riscv: Set pc_succ_insn for !rvc illegal insn
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2023-01-06 22:15:53 +00:00
parent aaa90fede5 bc92f26151
commit 052e6534c4
41 changed files with 1226 additions and 255 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/intc/Kconfig
+3
View File
@@ -72,12 +72,15 @@ config RISCV_ACLINT
config RISCV_APLIC
bool
select MSI_NONBROKEN
config RISCV_IMSIC
bool
select MSI_NONBROKEN
config SIFIVE_PLIC
bool
select MSI_NONBROKEN
config GOLDFISH_PIC
bool
hw/intc/sifive_plic.c
+46 -20
View File
@@ -42,7 +42,6 @@ static PLICMode char_to_mode(char c)
switch (c) {
case 'U': return PLICMode_U;
case 'S': return PLICMode_S;
case 'H': return PLICMode_H;
case 'M': return PLICMode_M;
default:
error_report("plic: invalid mode '%c'", c);
@@ -78,6 +77,7 @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
uint32_t max_irq = 0;
uint32_t max_prio = plic->target_priority[addrid];
int i, j;
int num_irq_in_word = 32;
for (i = 0; i < plic->bitfield_words; i++) {
uint32_t pending_enabled_not_claimed =
@@ -88,7 +88,16 @@ static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
continue;
}
for (j = 0; j < 32; j++) {
if (i == (plic->bitfield_words - 1)) {
/*
* If plic->num_sources is not multiple of 32, num-of-irq in last
* word is not 32. Compute the num-of-irq of last word to avoid
* out-of-bound access of source_priority array.
*/
num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
}
for (j = 0; j < num_irq_in_word; j++) {
int irq = (i << 5) + j;
uint32_t prio = plic->source_priority[irq];
int enabled = pending_enabled_not_claimed & (1 << j);
@@ -131,10 +140,11 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
SiFivePLICState *plic = opaque;
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
uint32_t irq = (addr - plic->priority_base) >> 2;
return plic->source_priority[irq];
} else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
} else if (addr_between(addr, plic->pending_base,
(plic->num_sources + 31) >> 3)) {
uint32_t word = (addr - plic->pending_base) >> 2;
return plic->pending[word];
@@ -178,7 +188,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
SiFivePLICState *plic = opaque;
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
uint32_t irq = (addr - plic->priority_base) >> 2;
if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
/*
@@ -193,7 +203,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
sifive_plic_update(plic);
}
} else if (addr_between(addr, plic->pending_base,
plic->num_sources >> 3)) {
(plic->num_sources + 31) >> 3)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid pending write: 0x%" HWADDR_PRIx "",
__func__, addr);
@@ -281,7 +291,7 @@ static void sifive_plic_reset(DeviceState *dev)
*/
static void parse_hart_config(SiFivePLICState *plic)
{
int addrid, hartid, modes;
int addrid, hartid, modes, m;
const char *p;
char c;
@@ -290,11 +300,13 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
addrid += ctpop8(modes);
modes = 0;
hartid++;
if (modes) {
addrid += ctpop8(modes);
hartid++;
modes = 0;
}
} else {
int m = 1 << char_to_mode(c);
m = 1 << char_to_mode(c);
if (modes == (modes | m)) {
error_report("plic: duplicate mode '%c' in config: %s",
c, plic->hart_config);
@@ -305,8 +317,9 @@ static void parse_hart_config(SiFivePLICState *plic)
}
if (modes) {
addrid += ctpop8(modes);
hartid++;
modes = 0;
}
hartid++;
plic->num_addrs = addrid;
plic->num_harts = hartid;
@@ -317,11 +330,16 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
hartid++;
if (modes) {
hartid++;
modes = 0;
}
} else {
m = char_to_mode(c);
plic->addr_config[addrid].addrid = addrid;
plic->addr_config[addrid].hartid = hartid;
plic->addr_config[addrid].mode = char_to_mode(c);
plic->addr_config[addrid].mode = m;
modes |= (1 << m);
addrid++;
}
}
@@ -346,6 +364,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
parse_hart_config(s);
if (!s->num_sources) {
error_setg(errp, "plic: invalid number of interrupt sources");
return;
}
s->bitfield_words = (s->num_sources + 31) >> 5;
s->num_enables = s->bitfield_words * s->num_addrs;
s->source_priority = g_new0(uint32_t, s->num_sources);
@@ -362,7 +385,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
/* We can't allow the supervisor to control SEIP as this would allow the
/*
* We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached.
@@ -370,8 +394,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_report("SEIP already claimed");
exit(1);
error_setg(errp, "SEIP already claimed");
return;
}
}
@@ -402,8 +426,10 @@ static const VMStateDescription vmstate_sifive_plic = {
static Property sifive_plic_properties[] = {
DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
/* number of interrupt sources including interrupt source 0 */
DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
/* interrupt priority register base starting from source 0 */
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
@@ -476,11 +502,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
qdev_connect_gpio_out(dev, cpu_num,
qdev_connect_gpio_out(dev, cpu_num - hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
hw/misc/mchp_pfsoc_ioscb.c
+76 -2
View File
@@ -24,6 +24,7 @@
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
@@ -33,6 +34,10 @@
*/
#define IOSCB_WHOLE_REG_SIZE 0x10000000
#define IOSCB_SUBMOD_REG_SIZE 0x1000
#define IOSCB_CCC_REG_SIZE 0x2000000
#define IOSCB_CTRL_REG_SIZE 0x800
#define IOSCB_QSPIXIP_REG_SIZE 0x200
/*
* There are many sub-modules in the IOSCB module.
@@ -44,7 +49,10 @@
#define IOSCB_LANE01_BASE 0x06500000
#define IOSCB_LANE23_BASE 0x06510000
#define IOSCB_CTRL_BASE 0x07020000
#define IOSCB_QSPIXIP_BASE 0x07020100
#define IOSCB_MAILBOX_BASE 0x07020800
#define IOSCB_CFG_BASE 0x07080000
#define IOSCB_CCC_BASE 0x08000000
#define IOSCB_PLL_MSS_BASE 0x0E001000
#define IOSCB_CFM_MSS_BASE 0x0E002000
#define IOSCB_PLL_DDR_BASE 0x0E010000
@@ -141,6 +149,58 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
#define SERVICES_CR 0x50
#define SERVICES_SR 0x54
#define SERVICES_STATUS_SHIFT 16
static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t val = 0;
switch (offset) {
case SERVICES_SR:
/*
* Although some services have no error codes, most do. All services
* that do implement errors, begin their error codes at 1. Treat all
* service requests as failures & return 1.
* See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
* user guide for more information on service error codes.
*/
val = 1u << SERVICES_STATUS_SHIFT;
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
__func__, size, offset);
}
return val;
}
static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
MchpPfSoCIoscbState *s = opaque;
switch (offset) {
case SERVICES_CR:
qemu_irq_raise(s->irq);
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
"(size %d, value 0x%" PRIx64
", offset 0x%" HWADDR_PRIx ")\n",
__func__, size, value, offset);
}
}
static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
.read = mchp_pfsoc_ctrl_read,
.write = mchp_pfsoc_ctrl_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
{
MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
@@ -160,14 +220,26 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
"mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
"mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
"mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
"mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
"mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
"mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
"mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
"mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
@@ -216,6 +288,8 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
IOSCB_SUBMOD_REG_SIZE);
memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
&s->io_calib_sgmii);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
}
static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
hw/misc/mchp_pfsoc_sysreg.c
+14 -4
View File
@@ -24,10 +24,12 @@
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/misc/mchp_pfsoc_sysreg.h"
#define ENVM_CR 0xb8
#define MESSAGE_INT 0x118c
static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
unsigned size)
@@ -52,10 +54,17 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
"(size %d, value 0x%" PRIx64
", offset 0x%" HWADDR_PRIx ")\n",
__func__, size, value, offset);
MchpPfSoCSysregState *s = opaque;
switch (offset) {
case MESSAGE_INT:
qemu_irq_lower(s->irq);
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
"(size %d, value 0x%" PRIx64
", offset 0x%" HWADDR_PRIx ")\n",
__func__, size, value, offset);
}
}
static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
@@ -73,6 +82,7 @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
"mchp.pfsoc.sysreg",
MCHP_PFSOC_SYSREG_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
}
static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
hw/riscv/Kconfig
+10 -12
View File
@@ -4,6 +4,8 @@ config RISCV_NUMA
config IBEX
bool
# RISC-V machines in alphabetical order
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
@@ -11,7 +13,6 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_PDMA
select SIFIVE_PLIC
@@ -20,14 +21,8 @@ config MICROCHIP_PFSOC
config OPENTITAN
bool
select IBEX
select UNIMP
config SHAKTI_C
bool
select UNIMP
select SHAKTI_UART
select RISCV_ACLINT
select SIFIVE_PLIC
select UNIMP
config RISCV_VIRT
bool
@@ -37,7 +32,6 @@ config RISCV_VIRT
imply TPM_TIS_SYSBUS
select RISCV_NUMA
select GOLDFISH_RTC
select MSI_NONBROKEN
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
@@ -51,9 +45,15 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
config SHAKTI_C
bool
select RISCV_ACLINT
select SHAKTI_UART
select SIFIVE_PLIC
select UNIMP
config SIFIVE_E
bool
select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
@@ -64,7 +64,6 @@ config SIFIVE_E
config SIFIVE_U
bool
select CADENCE
select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
@@ -82,6 +81,5 @@ config SPIKE
bool
select RISCV_NUMA
select HTIF
select MSI_NONBROKEN
select RISCV_ACLINT
select SIFIVE_PLIC
hw/riscv/microchip_pfsoc.c
+69 -52
View File
@@ -86,58 +86,61 @@
* describes the complete IOSCB modules memory maps
*/
static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
[MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
[MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
[MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
[MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
[MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
[MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
[MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
[MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
[MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
[MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
[MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
[MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
[MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
[MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
[MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
[MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
[MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
[MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
[MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
[MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
[MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
[MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 },
[MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 },
[MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
[MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
};
static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -303,6 +306,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
memmap[MICROCHIP_PFSOC_SYSREG].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0,
qdev_get_gpio_in(DEVICE(s->plic),
MICROCHIP_PFSOC_MAILBOX_IRQ));
/* AXISW */
create_unimplemented_device("microchip.pfsoc.axisw",
@@ -456,11 +462,22 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
memmap[MICROCHIP_PFSOC_IOSCB].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0,
qdev_get_gpio_in(DEVICE(s->plic),
MICROCHIP_PFSOC_MAILBOX_IRQ));
/* FPGA Fabric */
create_unimplemented_device("microchip.pfsoc.fabricfic3",
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
/* FPGA Fabric */
create_unimplemented_device("microchip.pfsoc.fabricfic0",
memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base,
memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size);
/* FPGA Fabric */
create_unimplemented_device("microchip.pfsoc.fabricfic1",
memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base,
memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size);
/* QSPI Flash */
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
hw/riscv/opentitan.c
+16 -10
View File
@@ -28,8 +28,16 @@
#include "qemu/units.h"
#include "sysemu/sysemu.h"
/*
* This version of the OpenTitan machine currently supports
* OpenTitan RTL version:
* <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
*
* MMIO mapping as per (specified commit):
* lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
*/
static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
[IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
[IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
[IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
[IBEX_DEV_UART] = { 0x40000000, 0x1000 },
@@ -38,17 +46,18 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
[IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
[IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
[IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
[IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
[IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
[IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
[IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
@@ -59,10 +68,9 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
[IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
[IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
@@ -165,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
/* PLIC */
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
@@ -265,8 +271,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
hw/riscv/sifive_u.c
+2 -1
View File
@@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_DEV_PLIC].base,
0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
SIFIVE_U_PLIC_NUM_SOURCES - 1);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
hw/riscv/spike.c
-1
View File
@@ -8,7 +8,6 @@
*
* 0) HTIF Console and Poweroff
* 1) CLINT (Timer and IPI)
* 2) PLIC (Platform Level Interrupt Controller)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
hw/riscv/virt.c
+2 -5
View File
@@ -468,7 +468,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
VIRT_IRQCHIP_NUM_SOURCES - 1);
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
@@ -546,8 +547,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
VIRT_IRQCHIP_IPI_MSI);
if (riscv_socket_count(mc) > 1) {
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
@@ -597,8 +596,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
VIRT_IRQCHIP_IPI_MSI);
if (imsic_guest_bits) {
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
imsic_guest_bits);
include/hw/intc/sifive_plic.h
-1
View File
@@ -33,7 +33,6 @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
typedef enum PLICMode {
PLICMode_U,
PLICMode_S,
PLICMode_H,
PLICMode_M
} PLICMode;
include/hw/misc/mchp_pfsoc_ioscb.h
+4
View File
@@ -29,7 +29,10 @@ typedef struct MchpPfSoCIoscbState {
MemoryRegion lane01;
MemoryRegion lane23;
MemoryRegion ctrl;
MemoryRegion qspixip;
MemoryRegion mailbox;
MemoryRegion cfg;
MemoryRegion ccc;
MemoryRegion pll_mss;
MemoryRegion cfm_mss;
MemoryRegion pll_ddr;
@@ -40,6 +43,7 @@ typedef struct MchpPfSoCIoscbState {
MemoryRegion cfm_sgmii;
MemoryRegion bc_sgmii;
MemoryRegion io_calib_sgmii;
qemu_irq irq;
} MchpPfSoCIoscbState;
#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
include/hw/misc/mchp_pfsoc_sysreg.h
+1
View File
@@ -28,6 +28,7 @@
typedef struct MchpPfSoCSysregState {
SysBusDevice parent;
MemoryRegion sysreg;
qemu_irq irq;
} MchpPfSoCSysregState;
#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
include/hw/riscv/microchip_pfsoc.h
+5 -2
View File
@@ -121,6 +121,8 @@ enum {
MICROCHIP_PFSOC_USB,
MICROCHIP_PFSOC_QSPI_XIP,
MICROCHIP_PFSOC_IOSCB,
MICROCHIP_PFSOC_FABRIC_FIC0,
MICROCHIP_PFSOC_FABRIC_FIC1,
MICROCHIP_PFSOC_FABRIC_FIC3,
MICROCHIP_PFSOC_DRAM_LO,
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
@@ -145,14 +147,15 @@ enum {
MICROCHIP_PFSOC_MMUART2_IRQ = 92,
MICROCHIP_PFSOC_MMUART3_IRQ = 93,
MICROCHIP_PFSOC_MMUART4_IRQ = 94,
MICROCHIP_PFSOC_MAILBOX_IRQ = 96,
};
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
include/hw/riscv/opentitan.h
+5 -5
View File
@@ -81,7 +81,7 @@ enum {
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
IBEX_DEV_PINMUX,
IBEX_DEV_PADCTRL,
IBEX_DEV_AON_TIMER,
IBEX_DEV_USBDEV,
IBEX_DEV_FLASH_CTRL,
IBEX_DEV_PLIC,
@@ -109,10 +109,10 @@ enum {
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_TIMER_TIMEREXPIRED0_0 = 127,
IBEX_SPI_HOST0_ERR_IRQ = 151,
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152,
IBEX_SPI_HOST1_ERR_IRQ = 153,
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154,
IBEX_SPI_HOST0_ERR_IRQ = 134,
IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
IBEX_SPI_HOST1_ERR_IRQ = 136,
IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
};
#endif
include/hw/riscv/shakti_c.h
+1 -1
View File
@@ -65,7 +65,7 @@ enum {
#define SHAKTI_C_PLIC_NUM_SOURCES 28
/* Excluding Priority 0 */
#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
include/hw/riscv/sifive_e.h
+7 -2
View File
@@ -82,9 +82,14 @@ enum {
};
#define SIFIVE_E_PLIC_HART_CONFIG "M"
#define SIFIVE_E_PLIC_NUM_SOURCES 127
/*
* Freedom E310 G002 and G003 supports 52 interrupt sources while
* Freedom E310 G000 supports 51 interrupt sources. We use the value
* of G002 and G003, so it is 53 (including interrupt source 0).
*/
#define SIFIVE_E_PLIC_NUM_SOURCES 53
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
include/hw/riscv/sifive_u.h
+1 -1
View File
@@ -158,7 +158,7 @@ enum {
#define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
include/hw/riscv/virt.h
+3 -5
View File
@@ -87,20 +87,18 @@ enum {
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
};
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
#define VIRT_IRQCHIP_IPI_MSI 1
#define VIRT_IRQCHIP_NUM_MSIS 255
#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
#define VIRT_IRQCHIP_NUM_SOURCES 96
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
#define VIRT_PLIC_PRIORITY_BASE 0x04
#define VIRT_PLIC_PRIORITY_BASE 0x00
#define VIRT_PLIC_PENDING_BASE 0x1000
#define VIRT_PLIC_ENABLE_BASE 0x2000
#define VIRT_PLIC_ENABLE_STRIDE 0x80
target/riscv/cpu.c
+11
View File
@@ -76,6 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -382,6 +383,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CSR_MHARTID,
CSR_MSTATUS,
CSR_MSTATUSH,
/*
* CSR_SSTATUS is intentionally omitted here as its value
* can be figured out by looking at CSR_MSTATUS
*/
CSR_HSTATUS,
CSR_VSSTATUS,
CSR_MIP,
@@ -762,6 +767,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
@@ -1017,6 +1027,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),

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