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Revert "Use correct types to enable > 2G support" (r4238), it is

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not yet ready.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4240 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
2008-04-22 20:45:18 +00:00
parent 0ba5f006bb
commit 03875444d9
36 changed files with 98 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpu-all.h
+6 -10
View File
@@ -700,7 +700,7 @@ static inline void stfq_be_p(void *ptr, float64 v)
/* page related stuff */
#define TARGET_PAGE_SIZE (1UL << TARGET_PAGE_BITS)
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
@@ -806,16 +806,12 @@ int cpu_inw(CPUState *env, int addr);
int cpu_inl(CPUState *env, int addr);
#endif
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
/* memory API */
extern ram_addr_t phys_ram_size;
extern int phys_ram_size;
extern int phys_ram_fd;
extern uint8_t *phys_ram_base;
extern uint8_t *phys_ram_dirty;
extern ram_addr_t ram_size;
/* physical memory access */
#define TLB_INVALID_MASK (1 << 3)
@@ -837,10 +833,10 @@ typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset);
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
unsigned long size,
unsigned long phys_offset);
uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(unsigned int size);
void qemu_ram_free(ram_addr_t addr);
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
cpu-defs.h
+3
View File
@@ -76,6 +76,9 @@ typedef uint64_t target_phys_addr_t;
#error TARGET_PHYS_ADDR_BITS undefined
#endif
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
#define EXCP_INTERRUPT 0x10000 /* async interruption */
exec-all.h
+1 -1
View File
@@ -82,7 +82,7 @@ int cpu_restore_state_copy(struct TranslationBlock *tb,
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
exec.c
+20 -31
View File
@@ -74,10 +74,6 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 42
#elif defined(TARGET_PPC64)
#define TARGET_PHYS_ADDR_SPACE_BITS 42
#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
#define TARGET_PHYS_ADDR_SPACE_BITS 40
#elif defined(TARGET_I386) && !defined(USE_KQEMU)
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#else
/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
#define TARGET_PHYS_ADDR_SPACE_BITS 32
@@ -92,7 +88,7 @@ spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));
uint8_t *code_gen_ptr;
ram_addr_t phys_ram_size;
int phys_ram_size;
int phys_ram_fd;
uint8_t *phys_ram_base;
uint8_t *phys_ram_dirty;
@@ -117,7 +113,7 @@ typedef struct PageDesc {
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low 12 bits */
ram_addr_t phys_offset;
uint32_t phys_offset;
} PhysPageDesc;
#define L2_BITS 10
@@ -128,14 +124,9 @@ typedef struct PhysPageDesc {
*/
#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
#else
#define L1_BITS (TARGET_PHYS_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
#endif
#undef L1_BITS
#undef L2_BITS
#define L1_BITS 13
#define L2_BITS 13
#define L1_SIZE (1 << L1_BITS)
#define L2_SIZE (1 << L2_BITS)
@@ -243,7 +234,7 @@ static void page_init(void)
#endif
}
static inline PageDesc *page_find_alloc(target_ulong index)
static inline PageDesc *page_find_alloc(unsigned int index)
{
PageDesc **lp, *p;
@@ -258,7 +249,7 @@ static inline PageDesc *page_find_alloc(target_ulong index)
return p + (index & (L2_SIZE - 1));
}
static inline PageDesc *page_find(target_ulong index)
static inline PageDesc *page_find(unsigned int index)
{
PageDesc *p;
@@ -274,7 +265,6 @@ static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
PhysPageDesc *pd;
p = (void **)l1_phys_map;
#if 0
#if TARGET_PHYS_ADDR_SPACE_BITS > 32
#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
@@ -290,7 +280,6 @@ static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
memset(p, 0, sizeof(void *) * L1_SIZE);
*lp = p;
}
#endif
#endif
lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pd = *lp;
@@ -522,12 +511,12 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
}
static inline void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
static inline void tb_phys_invalidate(TranslationBlock *tb, unsigned int page_addr)
{
CPUState *env;
PageDesc *p;
unsigned int h, n1;
target_phys_addr_t phys_pc;
target_ulong phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
@@ -678,7 +667,7 @@ static void tb_gen_code(CPUState *env,
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
int is_cpu_write_access)
{
int n, current_tb_modified, current_tb_not_found, current_flags;
@@ -791,7 +780,7 @@ void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t
}
/* len must be <= 8 and start must be a multiple of len */
static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
{
PageDesc *p;
int offset, b;
@@ -820,7 +809,7 @@ static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int le
}
#if !defined(CONFIG_SOFTMMU)
static void tb_invalidate_phys_page(target_phys_addr_t addr,
static void tb_invalidate_phys_page(target_ulong addr,
unsigned long pc, void *puc)
{
int n, current_flags, current_tb_modified;
@@ -1997,7 +1986,7 @@ static inline void tlb_set_dirty(CPUState *env,
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
int memory);
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
int orig_memory);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
@@ -2023,13 +2012,13 @@ static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
io memory page */
void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
unsigned long size,
unsigned long phys_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
ram_addr_t orig_size = size;
unsigned long orig_size = size;
void *subpage;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
@@ -2037,7 +2026,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
ram_addr_t orig_memory = p->phys_offset;
unsigned long orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
@@ -2090,7 +2079,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
}
/* XXX: temporary until new memory mapping API */
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
@@ -2101,12 +2090,12 @@ ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
}
/* XXX: better than nothing */
ram_addr_t qemu_ram_alloc(ram_addr_t size)
ram_addr_t qemu_ram_alloc(unsigned int size)
{
ram_addr_t addr;
if ((phys_ram_alloc_offset + size) >= phys_ram_size) {
fprintf(stderr, "Not enough memory (requested_size = %lu, max memory = %" PRIu64 ")\n",
size, (uint64_t)phys_ram_size);
fprintf(stderr, "Not enough memory (requested_size = %u, max memory = %d)\n",
size, phys_ram_size);
abort();
}
addr = phys_ram_alloc_offset;
@@ -2449,7 +2438,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
return 0;
}
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
int orig_memory)
{
subpage_t *mmio;
hw/an5206.c
+1 -1
View File
@@ -30,7 +30,7 @@ void DMA_run (void)
/* Board init. */
static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
static void an5206_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/boards.h
+1 -1
View File
@@ -3,7 +3,7 @@
#ifndef HW_BOARDS_H
#define HW_BOARDS_H
typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
hw/dummy_m68k.c
+1 -1
View File
@@ -14,7 +14,7 @@
/* Board init. */
static void dummy_m68k_init(ram_addr_t ram_size, int vga_ram_size,
static void dummy_m68k_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/etraxfs.c
+1 -1
View File
@@ -41,7 +41,7 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);
static
void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
void bareetraxfs_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/gumstix.c
+2 -2
View File
@@ -41,7 +41,7 @@
static const int sector_len = 128 * 1024;
static void connex_init(ram_addr_t ram_size, int vga_ram_size,
static void connex_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -81,7 +81,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size,
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
static void verdex_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/integratorcp.c
+1 -1
View File
@@ -474,7 +474,7 @@ static struct arm_boot_info integrator_binfo = {
.board_id = 0x113,
};
static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
static void integratorcp_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mainstone.c
+2 -2
View File
@@ -64,7 +64,7 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
static void mainstone_common_init(int ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
@@ -133,7 +133,7 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
arm_load_kernel(cpu->env, &mainstone_binfo);
}
static void mainstone_init(ram_addr_t ram_size, int vga_ram_size,
static void mainstone_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mcf5208.c
+1 -1
View File
@@ -202,7 +202,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
}
static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
static void mcf5208evb_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mips_jazz.c
+3 -3
View File
@@ -116,7 +116,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
void mips_jazz_init (int ram_size, int vga_ram_size,
DisplayState *ds, const char *cpu_model,
enum jazz_model_e jazz_model)
{
@@ -256,7 +256,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
}
static
void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
void mips_magnum_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -265,7 +265,7 @@ void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
}
static
void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
void mips_pica61_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mips_malta.c
+1 -1
View File
@@ -763,7 +763,7 @@ static void main_cpu_reset(void *opaque)
}
static
void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
void mips_malta_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mips_mipssim.c
+1 -1
View File
@@ -106,7 +106,7 @@ static void main_cpu_reset(void *opaque)
}
static void
mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
mips_mipssim_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/mips_r4k.c
+1 -1
View File
@@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
static const int sector_len = 32 * 1024;
static
void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
void mips_r4k_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/nseries.c
+1 -1
View File
@@ -891,7 +891,7 @@ static struct arm_boot_info n800_binfo = {
.atag_board = n800_atag_setup,
};
static void n800_init(ram_addr_t ram_size, int vga_ram_size,
static void n800_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/palm.c
+1 -1
View File
@@ -192,7 +192,7 @@ static struct arm_boot_info palmte_binfo = {
.board_id = 0x331,
};
static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
static void palmte_init(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
hw/pc.c
+6 -27
View File
@@ -188,8 +188,7 @@ static int boot_device2nibble(char boot_device)
}
/* hd_table must contain 4 block drivers */
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device, BlockDriverState **hd_table)
static void cmos_init(int ram_size, const char *boot_device, BlockDriverState **hd_table)
{
RTCState *s = rtc_state;
int nbds, bds[3] = { 0, };
@@ -212,12 +211,6 @@ static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
if (above_4g_mem_size) {
rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
}
if (ram_size > (16 * 1024 * 1024))
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
else
@@ -683,7 +676,7 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
}
/* PC hardware initialisation */
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
static void pc_init1(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
@@ -692,7 +685,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
char buf[1024];
int ret, linux_boot, i;
ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size, vga_bios_size;
PCIBus *pci_bus;
int piix3_devfn = -1;
@@ -704,13 +696,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
if (ram_size >= 0xe0000000 ) {
above_4g_mem_size = ram_size - 0xe0000000;
below_4g_mem_size = 0xe0000000;
} else {
below_4g_mem_size = ram_size;
}
linux_boot = (kernel_filename != NULL);
/* init CPUs */
@@ -745,13 +730,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
/* allocate RAM */
ram_addr = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
/* above 4giga memory allocation */
if (above_4g_mem_size > 0) {
cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
ram_addr + below_4g_mem_size);
}
cpu_register_physical_memory(0, ram_size, ram_addr);
/* allocate VGA RAM */
vga_ram_addr = qemu_ram_alloc(vga_ram_size);
@@ -971,7 +950,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
}
floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
cmos_init(ram_size, boot_device, hd);
if (pci_enabled && usb_enabled) {
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
@@ -1011,7 +990,7 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
}
}
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
static void pc_init_pci(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -1023,7 +1002,7 @@ static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
initrd_filename, 1, cpu_model);
}
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
static void pc_init_isa(int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
hw/piix_pci.c
+1 -1
View File
@@ -55,7 +55,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
return (irq_num + slot_addend) & 3;
}
static target_phys_addr_t isa_page_descs[384 / 4];
static uint32_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];

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