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target/arm/tcg/cpu64: add the cortex-a78ae CPU

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Add support for the ARM Cortex-A78AE CPU.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-40-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
2025-10-07 10:35:36 +01:00
committed by Peter Maydell
parent 16aa53c971
commit 0252b88c79
1 changed files with 78 additions and 0 deletions
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target/arm/tcg/cpu64.c
+78
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@@ -406,6 +406,79 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.reset_pmcr_el0 = 0x410b3000;
}
static void aarch64_a78ae_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a78ae";
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU);
/* Ordered by 3.2.4 AArch64 registers by functional group */
SET_IDREG(isar, CLIDR, 0x82000023);
cpu->ctr = 0x9444c004;
cpu->dcz_blocksize = 4;
SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull);
SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull);
SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
SET_IDREG(isar, ID_AFR0, 0x00000000);
SET_IDREG(isar, ID_DFR0, 0x04010088);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
SET_IDREG(isar, ID_ISAR3, 0x01112131);
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x01011121);
SET_IDREG(isar, ID_ISAR6, 0x00000010);
SET_IDREG(isar, ID_MMFR0, 0x10201105);
SET_IDREG(isar, ID_MMFR1, 0x40000000);
SET_IDREG(isar, ID_MMFR2, 0x01260000);
SET_IDREG(isar, ID_MMFR3, 0x02122211);
SET_IDREG(isar, ID_MMFR4, 0x00021110);
SET_IDREG(isar, ID_PFR0, 0x10010131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x410fd423; /* r0p3 */
cpu->revidr = 0;
/* From 3.2.33 CCSIDR_EL1 */
/* 64KB L1 dcache */
cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
/* 64KB L1 icache */
cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
/* 512KB L2 cache */
cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7);
/* From 3.2.118 SCTLR_EL3 */
cpu->reset_sctlr = 0x30c50838;
/* From 3.4.23 ICH_VTR_EL2 */
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
/* From 3.4.8 ICC_CTLR_EL3 */
cpu->gic_pribits = 5;
/* From 3.5.1 AdvSIMD AArch64 register summary */
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
/* From 5.5.1 AArch64 PMU register summary */
cpu->isar.reset_pmcr_el0 = 0x41223000;
}
static void aarch64_a64fx_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1321,6 +1394,11 @@ static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a55", .initfn = aarch64_a55_initfn },
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
/*
* The Cortex-A78AE differs slightly from the plain Cortex-A78. We don't
* currently model the latter.
*/
{ .name = "cortex-a78ae", .initfn = aarch64_a78ae_initfn },
{ .name = "cortex-a710", .initfn = aarch64_a710_initfn },
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },