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Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging

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This commit is contained in:
Anthony Liguori
2011-12-05 08:43:38 -06:00
parent 4eb2d2d900 f44336c594
commit 01e7a53aed
168 changed files with 2391 additions and 2725 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/an5206.c
+1 -1
View File
@@ -53,7 +53,7 @@ static void an5206_init(ram_addr_t ram_size,
memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env);
mcf5206_init(address_space_mem, AN5206_MBAR_ADDR, env);
/* Load kernel. */
if (!kernel_filename) {
hw/apb_pci.c
+3 -3
View File
@@ -410,18 +410,18 @@ static int pci_pbm_init_device(SysBusDevice *dev)
memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
0x10000);
/* at region 0 */
sysbus_init_mmio_region(dev, &s->apb_config);
sysbus_init_mmio(dev, &s->apb_config);
memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
0x1000000);
/* at region 1 */
sysbus_init_mmio_region(dev, &s->pci_config);
sysbus_init_mmio(dev, &s->pci_config);
/* pci_ioport */
memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
"apb-pci-ioport", 0x10000);
/* at region 2 */
sysbus_init_mmio_region(dev, &s->pci_ioport);
sysbus_init_mmio(dev, &s->pci_ioport);
return 0;
}
hw/apic.c
+1 -1
View File
@@ -998,7 +998,7 @@ static int apic_init1(SysBusDevice *dev)
}
memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
MSI_ADDR_SIZE);
sysbus_init_mmio_region(dev, &s->io_memory);
sysbus_init_mmio(dev, &s->io_memory);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++;
hw/arm11mpcore.c
+1 -1
View File
@@ -73,7 +73,7 @@ static int realview_mpcore_init(SysBusDevice *dev)
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
sysbus_init_mmio_region(dev, sysbus_mmio_get_region(s->priv, 0));
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
return 0;
}
hw/arm_sysctl.c
+1 -1
View File
@@ -383,7 +383,7 @@ static int arm_sysctl_init1(SysBusDevice *dev)
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
return 0;
hw/arm_timer.c
+2 -2
View File
@@ -247,7 +247,7 @@ static int sp804_init(SysBusDevice *dev)
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
@@ -311,7 +311,7 @@ static int icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[2]->irq);
memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;
hw/armv7m.c
+1 -1
View File
@@ -126,7 +126,7 @@ static int bitband_init(SysBusDevice *dev)
memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
0x02000000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
hw/axis_dev88.c
+30 -33
View File
@@ -39,6 +39,7 @@
struct nand_state_t
{
DeviceState *nand;
MemoryRegion iomem;
unsigned int rdy:1;
unsigned int ale:1;
unsigned int cle:1;
@@ -46,7 +47,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@@ -61,31 +62,25 @@ static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
}
static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
int rdy;
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
nand_setio(s->nand, value);
nand_getpins(s->nand, &rdy);
s->rdy = rdy;
}
static CPUReadMemoryFunc * const nand_read[] = {
&nand_readl,
&nand_readl,
&nand_readl,
static const MemoryRegionOps nand_ops = {
.read = nand_read,
.write = nand_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const nand_write[] = {
&nand_writel,
&nand_writel,
&nand_writel,
};
struct tempsensor_t
{
unsigned int shiftreg;
@@ -165,12 +160,13 @@ static void tempsensor_clkedge(struct tempsensor_t *s,
static struct gpio_state_t
{
MemoryRegion iomem;
struct nand_state_t *nand;
struct tempsensor_t tempsensor;
uint32_t regs[0x5c / 4];
} gpio_state;
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@@ -199,10 +195,11 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
addr >>= 2;
switch (addr)
@@ -230,14 +227,14 @@ static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const gpio_read[] = {
NULL, NULL,
&gpio_readl,
};
static CPUWriteMemoryFunc * const gpio_write[] = {
NULL, NULL,
&gpio_writel,
static const MemoryRegionOps gpio_ops = {
.read = gpio_read,
.write = gpio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
#define INTMEM_SIZE (128 * 1024)
@@ -258,8 +255,6 @@ void axisdev88_init (ram_addr_t ram_size,
void *etraxfs_dmac;
struct etraxfs_dma_client *dma_eth;
int i;
int nand_regs;
int gpio_regs;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
@@ -283,14 +278,16 @@ void axisdev88_init (ram_addr_t ram_size,
nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
"nand", 0x05000000);
memory_region_add_subregion(address_space_mem, 0x10000000,
&nand_state.iomem);
gpio_state.nand = &nand_state;
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
"gpio", 0x5c);
memory_region_add_subregion(address_space_mem, 0x3001a000,
&gpio_state.iomem);
cpu_irq = cris_pic_init_cpu(env);
hw/bitbang_i2c.c
+3 -1
View File
@@ -184,6 +184,7 @@ bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus)
/* GPIO interface. */
typedef struct {
SysBusDevice busdev;
MemoryRegion dummy_iomem;
bitbang_i2c_interface *bitbang;
int last_level;
qemu_irq out;
@@ -205,7 +206,8 @@ static int gpio_i2c_init(SysBusDevice *dev)
GPIOI2CState *s = FROM_SYSBUS(GPIOI2CState, dev);
i2c_bus *bus;
sysbus_init_mmio(dev, 0x0, 0);
memory_region_init(&s->dummy_iomem, "gpio_i2c", 0);
sysbus_init_mmio(dev, &s->dummy_iomem);
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
hw/bonito.c
+87 -112
View File
@@ -201,17 +201,9 @@ typedef struct PCIBonitoState
} boncop;
/* Bonito registers */
target_phys_addr_t bonito_reg_start;
target_phys_addr_t bonito_reg_length;
int bonito_reg_handle;
target_phys_addr_t bonito_pciconf_start;
target_phys_addr_t bonito_pciconf_length;
int bonito_pciconf_handle;
target_phys_addr_t bonito_spciconf_start;
target_phys_addr_t bonito_spciconf_length;
int bonito_spciconf_handle;
MemoryRegion iomem;
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
@@ -221,19 +213,12 @@ typedef struct PCIBonitoState
target_phys_addr_t bonito_localio_length;
int bonito_localio_handle;
target_phys_addr_t bonito_ldma_start;
target_phys_addr_t bonito_ldma_length;
int bonito_ldma_handle;
target_phys_addr_t bonito_cop_start;
target_phys_addr_t bonito_cop_length;
int bonito_cop_handle;
} PCIBonitoState;
PCIBonitoState * bonito_state;
static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void bonito_writel(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@@ -295,7 +280,8 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@@ -311,20 +297,18 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
}
}
static CPUWriteMemoryFunc * const bonito_write[] = {
NULL,
NULL,
bonito_writel,
};
static CPUReadMemoryFunc * const bonito_read[] = {
NULL,
NULL,
bonito_readl,
static const MemoryRegionOps bonito_ops = {
.read = bonito_readl,
.write = bonito_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -332,7 +316,8 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
s->dev.config_write(&s->dev, addr, val, 4);
}
static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIBonitoState *s = opaque;
@@ -342,19 +327,19 @@ static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
NULL,
NULL,
bonito_pciconf_writel,
static const MemoryRegionOps bonito_pciconf_ops = {
.read = bonito_pciconf_readl,
.write = bonito_pciconf_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
NULL,
NULL,
bonito_pciconf_readl,
};
static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@@ -365,26 +350,25 @@ static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
NULL,
NULL,
bonito_ldma_writel,
static const MemoryRegionOps bonito_ldma_ops = {
.read = bonito_ldma_readl,
.write = bonito_ldma_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUReadMemoryFunc * const bonito_ldma_read[] = {
NULL,
NULL,
bonito_ldma_readl,
};
static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@@ -395,23 +379,21 @@ static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
static CPUWriteMemoryFunc * const bonito_cop_write[] = {
NULL,
NULL,
bonito_cop_writel,
};
static CPUReadMemoryFunc * const bonito_cop_read[] = {
NULL,
NULL,
bonito_cop_readl,
static const MemoryRegionOps bonito_cop_ops = {
.read = bonito_cop_readl,
.write = bonito_cop_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
@@ -602,16 +584,20 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
bonito_spciconf_writeb,
bonito_spciconf_writew,
bonito_spciconf_writel,
};
static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
bonito_spciconf_readb,
bonito_spciconf_readw,
bonito_spciconf_readl,
static const MemoryRegionOps bonito_spciconf_ops = {
.old_mmio = {
.read = {
bonito_spciconf_readb,
bonito_spciconf_readw,
bonito_spciconf_readl,
},
.write = {
bonito_spciconf_writeb,
bonito_spciconf_writew,
bonito_spciconf_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define BONITO_IRQ_BASE 32
@@ -690,51 +676,38 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
SysBusDevice *sysbus = &s->pcihost->busdev;
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
pci_config_set_prog_interface(dev->config, 0x00);
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
s->bonito_reg_handle);
memory_region_init_io(&s->iomem, &bonito_ops, s,
"north-bridge-register", BONITO_INTERNAL_REG_SIZE);
sysbus_init_mmio(sysbus, &s->iomem);
sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
/* set the north bridge pci configure mapping */
s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
bonito_pciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
s->bonito_pciconf_handle);
memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s,
"north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &s->pcihost->conf_mem);
sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
/* set the south bridge pci configure mapping */
s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
bonito_spciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
s->bonito_spciconf_handle);
memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s,
"south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &s->pcihost->data_mem);
sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
bonito_ldma_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_ldma_start = 0xbfe00200;
s->bonito_ldma_length = 0x100;
cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
s->bonito_ldma_handle);
memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s,
"ldma", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_ldma);
sysbus_mmio_map(sysbus, 3, 0xbfe00200);
s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
bonito_cop_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_cop_start = 0xbfe00300;
s->bonito_cop_length = 0x100;
cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
s->bonito_cop_handle);
memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s,
"cop", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_cop);
sysbus_mmio_map(sysbus, 4, 0xbfe00300);
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
s->bonito_pciio_start = BONITO_PCIIO_BASE;
@@ -780,10 +753,12 @@ PCIBus *bonito_init(qemu_irq *pic)
pcihost->bus = b;
qdev_init_nofail(dev);
d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito");
/* set the pcihost pointer before bonito_initfn is called */
d = pci_create(b, PCI_DEVFN(0, 0), "Bonito");
s = DO_UPCAST(PCIBonitoState, dev, d);
s->pcihost = pcihost;
bonito_state = s;
qdev_init_nofail(&d->qdev);
return b;
}
hw/cs4231.c
+11 -16
View File
@@ -35,6 +35,7 @@
typedef struct CSState {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[CS_REGS];
uint8_t dregs[CS_DREGS];
@@ -54,7 +55,8 @@ static void cs_reset(DeviceState *d)
s->dregs[25] = CS_VER;
}
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
CSState *s = opaque;
uint32_t saddr, ret;
@@ -80,7 +82,8 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void cs_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;
uint32_t saddr;
@@ -119,16 +122,10 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static CPUReadMemoryFunc * const cs_mem_read[3] = {
cs_mem_readl,
cs_mem_readl,
cs_mem_readl,
};
static CPUWriteMemoryFunc * const cs_mem_write[3] = {
cs_mem_writel,
cs_mem_writel,
cs_mem_writel,
static const MemoryRegionOps cs_mem_ops = {
.read = cs_mem_read,
.write = cs_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_cs4231 = {
@@ -145,12 +142,10 @@ static const VMStateDescription vmstate_cs4231 = {
static int cs4231_init1(SysBusDevice *dev)
{
int io;
CSState *s = FROM_SYSBUS(CSState, dev);
io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, CS_SIZE, io);
memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
return 0;
hw/dec_pci.c
+2 -2
View File
@@ -87,8 +87,8 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
sysbus_init_mmio(dev, &s->host_state.conf_mem);
sysbus_init_mmio(dev, &s->host_state.data_mem);
return 0;
}
hw/dp8393x.c
+15 -15
View File
@@ -156,7 +156,8 @@ typedef struct dp8393xState {
int64_t wt_last_update;
NICConf conf;
NICState *nic;
int mmio_index;
MemoryRegion *address_space;
MemoryRegion mmio;
/* Registers */
uint8_t cam[16][6];
@@ -664,16 +665,12 @@ static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
}
static CPUReadMemoryFunc * const dp8393x_read[3] = {
dp8393x_readb,
dp8393x_readw,
dp8393x_readl,
};
static CPUWriteMemoryFunc * const dp8393x_write[3] = {
dp8393x_writeb,
dp8393x_writew,
dp8393x_writel,
static const MemoryRegionOps dp8393x_ops = {
.old_mmio = {
.read = { dp8393x_readb, dp8393x_readw, dp8393x_readl, },
.write = { dp8393x_writeb, dp8393x_writew, dp8393x_writel, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int nic_can_receive(VLANClientState *nc)
@@ -865,7 +862,8 @@ static void nic_cleanup(VLANClientState *nc)
{
dp8393xState *s = DO_UPCAST(NICState, nc, nc)->opaque;
cpu_unregister_io_memory(s->mmio_index);
memory_region_del_subregion(s->address_space, &s->mmio);
memory_region_destroy(&s->mmio);
qemu_del_timer(s->watchdog);
qemu_free_timer(s->watchdog);
@@ -882,6 +880,7 @@ static NetClientInfo net_dp83932_info = {
};
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
@@ -891,6 +890,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
s = g_malloc0(sizeof(dp8393xState));
s->address_space = address_space;
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
@@ -908,7 +908,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_register_reset(nic_reset, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
memory_region_init_io(&s->mmio, &dp8393x_ops, s,
"dp8393x", 0x40 << it_shift);
memory_region_add_subregion(address_space, base, &s->mmio);
}
hw/ds1225y.c
+14 -48
View File
@@ -27,13 +27,14 @@
typedef struct {
DeviceState qdev;
MemoryRegion iomem;
uint32_t chip_size;
char *filename;
FILE *file;
uint8_t *contents;
} NvRamState;
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
@@ -43,25 +44,8 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
v |= nvram_readb(opaque, addr + 1) << 8;
return v;
}
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
v |= nvram_readb(opaque, addr + 1) << 8;
v |= nvram_readb(opaque, addr + 2) << 16;
v |= nvram_readb(opaque, addr + 3) << 24;
return v;
}
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
@@ -76,30 +60,14 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff);
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
};
static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
static const MemoryRegionOps nvram_ops = {
.read = nvram_read,
.write = nvram_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int nvram_post_load(void *opaque, int version_id)
@@ -146,13 +114,11 @@ static int nvram_sysbus_initfn(SysBusDevice *dev)
{
NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
FILE *file;
int s_io;
s->contents = g_malloc0(s->chip_size);
s_io = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->chip_size, s_io);
memory_region_init_io(&s->iomem, &nvram_ops, s, "nvram", s->chip_size);
sysbus_init_mmio(dev, &s->iomem);
/* Read current file */
file = fopen(s->filename, "rb");
hw/eccmemctl.c
+30 -33
View File
@@ -122,13 +122,15 @@
typedef struct ECCState {
SysBusDevice busdev;
MemoryRegion iomem, iomem_diag;
qemu_irq irq;
uint32_t regs[ECC_NREGS];
uint8_t diag[ECC_DIAG_SIZE];
uint32_t version;
} ECCState;
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
@@ -170,7 +172,8 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ECCState *s = opaque;
uint32_t ret = 0;
@@ -216,20 +219,18 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
return ret;
}
static CPUReadMemoryFunc * const ecc_mem_read[3] = {
NULL,
NULL,
ecc_mem_readl,
static const MemoryRegionOps ecc_mem_ops = {
.read = ecc_mem_read,
.write = ecc_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
NULL,
NULL,
ecc_mem_writel,
};
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
@@ -237,7 +238,8 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];
@@ -246,16 +248,14 @@ static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
return ret;
}
static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
ecc_diag_mem_readb,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
ecc_diag_mem_writeb,
NULL,
NULL,
static const MemoryRegionOps ecc_diag_mem_ops = {
.read = ecc_diag_mem_read,
.write = ecc_diag_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static const VMStateDescription vmstate_ecc = {
@@ -292,20 +292,17 @@ static void ecc_reset(DeviceState *d)
static int ecc_init1(SysBusDevice *dev)
{
int ecc_io_memory;
ECCState *s = FROM_SYSBUS(ECCState, dev);
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
memory_region_init_io(&s->iomem, &ecc_mem_ops, s, "ecc", ECC_SIZE);
sysbus_init_mmio(dev, &s->iomem);
if (s->version == ECC_MCC) { // SS-600MP only
ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
ecc_diag_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
memory_region_init_io(&s->iomem_diag, &ecc_diag_mem_ops, s,
"ecc.diag", ECC_DIAG_SIZE);
sysbus_init_mmio(dev, &s->iomem_diag);
}
return 0;
hw/empty_slot.c
+13 -19
View File
@@ -24,31 +24,27 @@
typedef struct EmptySlot {
SysBusDevice busdev;
MemoryRegion iomem;
uint64_t size;
} EmptySlot;
static uint32_t empty_slot_readl(void *opaque, target_phys_addr_t addr)
static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
static void empty_slot_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
static void empty_slot_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", val, addr);
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
}
CPUReadMemoryFunc * const empty_slot_read[3] = {
empty_slot_readl,
empty_slot_readl,
empty_slot_readl,
};
static CPUWriteMemoryFunc * const empty_slot_write[3] = {
empty_slot_writel,
empty_slot_writel,
empty_slot_writel,
static const MemoryRegionOps empty_slot_ops = {
.read = empty_slot_read,
.write = empty_slot_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
@@ -73,12 +69,10 @@ void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
ram_addr_t empty_slot_offset;
empty_slot_offset = cpu_register_io_memory(empty_slot_read,
empty_slot_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM);
memory_region_init_io(&s->iomem, &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
hw/escc.c
+1 -1
View File
@@ -888,7 +888,7 @@ static int escc_init1(SysBusDevice *dev)
memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
ESCC_SIZE << s->it_shift);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
if (s->chn[0].type == mouse) {
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
hw/esp.c
+20 -17
View File
@@ -45,6 +45,7 @@ typedef struct ESPState ESPState;
struct ESPState {
SysBusDevice busdev;
MemoryRegion iomem;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
qemu_irq irq;
@@ -504,7 +505,8 @@ static void esp_gpio_demux(void *opaque, int irq, int level)
}
}
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
@@ -545,7 +547,8 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
return s->rregs[saddr];
}
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void esp_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
ESPState *s = opaque;
uint32_t saddr;
@@ -641,7 +644,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[ESP_RINTR] = 0;
break;
default:
ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
break;
}
break;
@@ -656,22 +659,23 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[saddr] = val;
break;
default:
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
return;
}
s->wregs[saddr] = val;
}
static CPUReadMemoryFunc * const esp_mem_read[3] = {
esp_mem_readb,
NULL,
NULL,
};
static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
}
static CPUWriteMemoryFunc * const esp_mem_write[3] = {
esp_mem_writeb,
NULL,
esp_mem_writeb,
static const MemoryRegionOps esp_mem_ops = {
.read = esp_mem_read,
.write = esp_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = esp_mem_accepts,
};
static const VMStateDescription vmstate_esp = {
@@ -735,14 +739,13 @@ static const struct SCSIBusInfo esp_scsi_info = {
static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
memory_region_init_io(&s->iomem, &esp_mem_ops, s,
"esp", ESP_REGS << s->it_shift);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
hw/etraxfs_eth.c
+1 -1
View File
@@ -604,7 +604,7 @@ static int fs_eth_init(SysBusDevice *dev)
s->dma_in->client.pull = NULL;
memory_region_init_io(&s->mmio, &eth_ops, s, "etraxfs-eth", 0x5c);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
hw/etraxfs_pic.c
+1 -1
View File
@@ -147,7 +147,7 @@ static int etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_nmi);
memory_region_init_io(&s->mmio, &pic_ops, s, "etraxfs-pic", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_mmio(dev, &s->mmio);
return 0;
}

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