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Merge tag 'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

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target-arm queue:
 * Widen cnthctl_el2 to uint64_t
 * Unify checking for M Main Extension in MRS/MSR
 * bitbang_i2c, versatile_i2c: code cleanups
 * SME: refactor SME SM/ZA handling
 * Fix physical address resolution for MTE
 * Fix in_debug path in S1_ptw_translate
 * Don't set EXC_RETURN.ES if Security Extension not present
 * Implement DBGCLAIM registers
 * Provide stubs for more external debug registers
 * Look up ARMCPRegInfo at runtime, not translate time

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# =ubIU
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 23 Jan 2023 13:35:00 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230123' of https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
  target/arm: Look up ARMCPRegInfo at runtime
  target/arm: Reorg do_coproc_insn
  target/arm: provide stubs for more external debug registers
  target/arm: implement DBGCLAIM registers
  target/arm: Don't set EXC_RETURN.ES if Security Extension not present
  target/arm: Fix in_debug path in S1_ptw_translate
  target/arm: Fix physical address resolution for MTE
  target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr()
  target/arm/sme: Rebuild hflags in aarch64_set_svcr()
  target/arm/sme: Reset ZA state in aarch64_set_svcr()
  target/arm/sme: Reset SVE state in aarch64_set_svcr()
  target/arm/sme: Introduce aarch64_set_svcr()
  target/arm/sme: Rebuild hflags in set_pstate() helpers
  target/arm/sme: Reorg SME access handling in handle_msr_i()
  hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c
  hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro
  hw/i2c/versatile_i2c: Replace TYPE_VERSATILE_I2C -> TYPE_ARM_SBCON_I2C
  hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
  hw/i2c/versatile_i2c: Drop useless casts from void * to pointer
  hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
2023-01-23 13:40:28 +00:00
parent 65cc5ccf06 3b07a936d3
commit 00b1faea41
28 changed files with 506 additions and 383 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+1
View File
@@ -942,6 +942,7 @@ M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/*/versatile*
F: hw/i2c/arm_sbcon_i2c.c
F: include/hw/i2c/arm_sbcon_i2c.h
F: hw/misc/arm_sysctl.c
F: docs/system/arm/versatile.rst
hw/arm/Kconfig
+2 -2
View File
@@ -211,7 +211,7 @@ config REALVIEW
select PL110
select PL181 # display
select PL310 # cache controller
select VERSATILE_I2C
select ARM_SBCON_I2C
select DS1338 # I2C RTC+NVRAM
select USB_OHCI
@@ -481,7 +481,7 @@ config MPS2
select SPLIT_IRQ
select UNIMP
select CMSDK_APB_WATCHDOG
select VERSATILE_I2C
select ARM_SBCON_I2C
config FSL_IMX7
bool
hw/arm/musicpal.c
+2 -1
View File
@@ -26,6 +26,7 @@
#include "hw/block/flash.h"
#include "ui/console.h"
#include "hw/i2c/i2c.h"
#include "hw/i2c/bitbang_i2c.h"
#include "hw/irq.h"
#include "hw/or-irq.h"
#include "hw/audio/wm8750.h"
@@ -1303,7 +1304,7 @@ static void musicpal_init(MachineState *machine)
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
qdev_get_gpio_in(pic, MP_GPIO_IRQ));
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
i2c_dev = sysbus_create_simple(TYPE_GPIO_I2C, -1, NULL);
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL);
hw/arm/realview.c
+1 -1
View File
@@ -309,7 +309,7 @@ static void realview_init(MachineState *machine,
}
}
dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL);
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "ds1338", 0x68);
hw/arm/versatilepb.c
+1 -1
View File
@@ -336,7 +336,7 @@ static void versatile_init(MachineState *machine, int board_id)
/* Add PL031 Real Time Clock. */
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL);
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "ds1338", 0x68);
hw/arm/vexpress.c
+1 -1
View File
@@ -646,7 +646,7 @@ static void vexpress_common_init(MachineState *machine)
sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, map[VE_SERIALDVI], NULL);
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_slave_create_simple(i2c, "sii9022", 0x39);
hw/i2c/Kconfig
+1 -1
View File
@@ -14,7 +14,7 @@ config SMBUS_EEPROM
bool
select SMBUS
config VERSATILE_I2C
config ARM_SBCON_I2C
bool
select BITBANG_I2C
hw/i2c/versatile_i2c.c → hw/i2c/arm_sbcon_i2c.c
+17 -22
View File
@@ -29,11 +29,6 @@
#include "qemu/module.h"
#include "qom/object.h"
typedef ArmSbconI2CState VersatileI2CState;
DECLARE_INSTANCE_CHECKER(VersatileI2CState, VERSATILE_I2C,
TYPE_VERSATILE_I2C)
REG32(CONTROL_GET, 0)
REG32(CONTROL_SET, 0)
@@ -42,10 +37,10 @@ REG32(CONTROL_CLR, 4)
#define SCL BIT(0)
#define SDA BIT(1)
static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
static uint64_t arm_sbcon_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
ArmSbconI2CState *s = opaque;
switch (offset) {
case A_CONTROL_SET:
@@ -57,10 +52,10 @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
}
}
static void versatile_i2c_write(void *opaque, hwaddr offset,
static void arm_sbcon_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
ArmSbconI2CState *s = opaque;
switch (offset) {
case A_CONTROL_SET:
@@ -77,36 +72,36 @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
}
static const MemoryRegionOps versatile_i2c_ops = {
.read = versatile_i2c_read,
.write = versatile_i2c_write,
static const MemoryRegionOps arm_sbcon_i2c_ops = {
.read = arm_sbcon_i2c_read,
.write = arm_sbcon_i2c_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void versatile_i2c_init(Object *obj)
static void arm_sbcon_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
VersatileI2CState *s = VERSATILE_I2C(obj);
ArmSbconI2CState *s = ARM_SBCON_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
I2CBus *bus;
bus = i2c_init_bus(dev, "i2c");
bitbang_i2c_init(&s->bitbang, bus);
memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
memory_region_init_io(&s->iomem, obj, &arm_sbcon_i2c_ops, s,
"arm_sbcon_i2c", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
}
static const TypeInfo versatile_i2c_info = {
.name = TYPE_VERSATILE_I2C,
static const TypeInfo arm_sbcon_i2c_info = {
.name = TYPE_ARM_SBCON_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(VersatileI2CState),
.instance_init = versatile_i2c_init,
.instance_size = sizeof(ArmSbconI2CState),
.instance_init = arm_sbcon_i2c_init,
};
static void versatile_i2c_register_types(void)
static void arm_sbcon_i2c_register_types(void)
{
type_register_static(&versatile_i2c_info);
type_register_static(&arm_sbcon_i2c_info);
}
type_init(versatile_i2c_register_types)
type_init(arm_sbcon_i2c_register_types)
hw/i2c/bitbang_i2c.c
+50 -30
View File
@@ -16,30 +16,57 @@
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "qom/object.h"
#include "trace.h"
//#define DEBUG_BITBANG_I2C
#ifdef DEBUG_BITBANG_I2C
#define DPRINTF(fmt, ...) \
do { printf("bitbang_i2c: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#endif
/* bitbang_i2c_state enum to name */
static const char * const sname[] = {
#define NAME(e) [e] = stringify(e)
NAME(STOPPED),
[SENDING_BIT7] = "SENDING_BIT7 (START)",
NAME(SENDING_BIT6),
NAME(SENDING_BIT5),
NAME(SENDING_BIT4),
NAME(SENDING_BIT3),
NAME(SENDING_BIT2),
NAME(SENDING_BIT1),
NAME(SENDING_BIT0),
NAME(WAITING_FOR_ACK),
[RECEIVING_BIT7] = "RECEIVING_BIT7 (ACK)",
NAME(RECEIVING_BIT6),
NAME(RECEIVING_BIT5),
NAME(RECEIVING_BIT4),
NAME(RECEIVING_BIT3),
NAME(RECEIVING_BIT2),
NAME(RECEIVING_BIT1),
NAME(RECEIVING_BIT0),
NAME(SENDING_ACK),
NAME(SENT_NACK)
#undef NAME
};
static void bitbang_i2c_set_state(bitbang_i2c_interface *i2c,
bitbang_i2c_state state)
{
trace_bitbang_i2c_state(sname[i2c->state], sname[state]);
i2c->state = state;
}
static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c)
{
DPRINTF("STOP\n");
if (i2c->current_addr >= 0)
i2c_end_transfer(i2c->bus);
i2c->current_addr = -1;
i2c->state = STOPPED;
bitbang_i2c_set_state(i2c, STOPPED);
}
/* Set device data pin. */
static int bitbang_i2c_ret(bitbang_i2c_interface *i2c, int level)
{
trace_bitbang_i2c_data(i2c->last_clock, i2c->last_data,
i2c->device_out, level);
i2c->device_out = level;
//DPRINTF("%d %d %d\n", i2c->last_clock, i2c->last_data, i2c->device_out);
return level & i2c->last_data;
}
@@ -67,9 +94,8 @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
return bitbang_i2c_nop(i2c);
}
if (level == 0) {
DPRINTF("START\n");
/* START condition. */
i2c->state = SENDING_BIT7;
bitbang_i2c_set_state(i2c, SENDING_BIT7);
i2c->current_addr = -1;
} else {
/* STOP condition. */
@@ -96,7 +122,7 @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
case SENDING_BIT7 ... SENDING_BIT0:
i2c->buffer = (i2c->buffer << 1) | data;
/* will end up in WAITING_FOR_ACK */
i2c->state++;
bitbang_i2c_set_state(i2c, i2c->state + 1);
return bitbang_i2c_ret(i2c, 1);
case WAITING_FOR_ACK:
@@ -105,47 +131,45 @@ int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level)
if (i2c->current_addr < 0) {
i2c->current_addr = i2c->buffer;
DPRINTF("Address 0x%02x\n", i2c->current_addr);
trace_bitbang_i2c_addr(i2c->current_addr);
ret = i2c_start_transfer(i2c->bus, i2c->current_addr >> 1,
i2c->current_addr & 1);
} else {
DPRINTF("Sent 0x%02x\n", i2c->buffer);
trace_bitbang_i2c_send(i2c->buffer);
ret = i2c_send(i2c->bus, i2c->buffer);
}
if (ret) {
/* NACK (either addressing a nonexistent device, or the
* device we were sending to decided to NACK us).
*/
DPRINTF("Got NACK\n");
bitbang_i2c_set_state(i2c, SENT_NACK);
bitbang_i2c_enter_stop(i2c);
return bitbang_i2c_ret(i2c, 1);
}
if (i2c->current_addr & 1) {
i2c->state = RECEIVING_BIT7;
bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
} else {
i2c->state = SENDING_BIT7;
bitbang_i2c_set_state(i2c, SENDING_BIT7);
}
return bitbang_i2c_ret(i2c, 0);
}
case RECEIVING_BIT7:
i2c->buffer = i2c_recv(i2c->bus);
DPRINTF("RX byte 0x%02x\n", i2c->buffer);
trace_bitbang_i2c_recv(i2c->buffer);
/* Fall through... */
case RECEIVING_BIT6 ... RECEIVING_BIT0:
data = i2c->buffer >> 7;
/* will end up in SENDING_ACK */
i2c->state++;
bitbang_i2c_set_state(i2c, i2c->state + 1);
i2c->buffer <<= 1;
return bitbang_i2c_ret(i2c, data);
case SENDING_ACK:
i2c->state = RECEIVING_BIT7;
if (data != 0) {
DPRINTF("NACKED\n");
i2c->state = SENT_NACK;
bitbang_i2c_set_state(i2c, SENT_NACK);
i2c_nack(i2c->bus);
} else {
DPRINTF("ACKED\n");
bitbang_i2c_set_state(i2c, RECEIVING_BIT7);
}
return bitbang_i2c_ret(i2c, 1);
}
@@ -162,13 +186,13 @@ void bitbang_i2c_init(bitbang_i2c_interface *s, I2CBus *bus)
/* GPIO interface. */
#define TYPE_GPIO_I2C "gpio_i2c"
OBJECT_DECLARE_SIMPLE_TYPE(GPIOI2CState, GPIO_I2C)
struct GPIOI2CState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion dummy_iomem;
bitbang_i2c_interface bitbang;
int last_level;
qemu_irq out;
@@ -189,12 +213,8 @@ static void gpio_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
GPIOI2CState *s = GPIO_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
I2CBus *bus;
memory_region_init(&s->dummy_iomem, obj, "gpio_i2c", 0);
sysbus_init_mmio(sbd, &s->dummy_iomem);
bus = i2c_init_bus(dev, "i2c");
bitbang_i2c_init(&s->bitbang, bus);
hw/i2c/meson.build
+1 -1
View File
@@ -12,7 +12,7 @@ i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c'))
i2c_ss.add(when: 'CONFIG_ARM_SBCON_I2C', if_true: files('arm_sbcon_i2c.c'))
i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c'))
i2c_ss.add(when: 'CONFIG_PPC4XX', if_true: files('ppc4xx_i2c.c'))
i2c_ss.add(when: 'CONFIG_PCA954X', if_true: files('i2c_mux_pca954x.c'))
hw/i2c/trace-events
+7
View File
@@ -1,5 +1,12 @@
# See docs/devel/tracing.rst for syntax documentation.
# bitbang_i2c.c
bitbang_i2c_state(const char *old_state, const char *new_state) "state %s -> %s"
bitbang_i2c_addr(uint8_t addr) "Address 0x%02x"
bitbang_i2c_send(uint8_t byte) "TX byte 0x%02x"
bitbang_i2c_recv(uint8_t byte) "RX byte 0x%02x"
bitbang_i2c_data(unsigned dat, unsigned clk, unsigned old_out, unsigned new_out) "dat %u clk %u out %u -> %u"
# core.c
i2c_event(const char *event, uint8_t address) "%s(addr:0x%02x)"
include/hw/i2c/arm_sbcon_i2c.h
+2 -4
View File
@@ -17,12 +17,10 @@
#include "hw/i2c/bitbang_i2c.h"
#include "qom/object.h"
#define TYPE_VERSATILE_I2C "versatile_i2c"
#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C
#define TYPE_ARM_SBCON_I2C "versatile_i2c"
typedef struct ArmSbconI2CState ArmSbconI2CState;
DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C,
TYPE_ARM_SBCON_I2C)
DECLARE_INSTANCE_CHECKER(ArmSbconI2CState, ARM_SBCON_I2C, TYPE_ARM_SBCON_I2C)
struct ArmSbconI2CState {
/*< private >*/
include/hw/i2c/bitbang_i2c.h
+2
View File
@@ -3,6 +3,8 @@
#include "hw/i2c/i2c.h"
#define TYPE_GPIO_I2C "gpio_i2c"
typedef struct bitbang_i2c_interface bitbang_i2c_interface;
#define BITBANG_I2C_SDA 0
linux-user/aarch64/cpu_loop.c
+2 -9
View File
@@ -89,15 +89,8 @@ void cpu_loop(CPUARMState *env)
switch (trapnr) {
case EXCP_SWI:
/*
* On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
* PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
*/
if (FIELD_EX64(env->svcr, SVCR, SM)) {
env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
arm_rebuild_hflags(env);
arm_reset_sve_state(env);
}
/* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
ret = do_syscall(env,
env->xregs[8],
env->xregs[0],
linux-user/aarch64/signal.c
+2 -11
View File
@@ -665,17 +665,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
env->btype = 2;
}
/*
* Invoke the signal handler with both SM and ZA disabled.
* When clearing SM, ResetSVEState, per SMSTOP.
*/
if (FIELD_EX64(env->svcr, SVCR, SM)) {
arm_reset_sve_state(env);
}
if (env->svcr) {
env->svcr = 0;
arm_rebuild_hflags(env);
}
/* Invoke the signal handler with both SM and ZA disabled. */
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
if (info) {
tswap_siginfo(&frame->info, info);
target/arm/cpu.h
+3 -2
View File
@@ -479,7 +479,7 @@ typedef struct CPUArchState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
@@ -495,6 +495,7 @@ typedef struct CPUArchState {
uint64_t dbgbcr[16]; /* breakpoint control registers */
uint64_t dbgwvr[16]; /* watchpoint value registers */
uint64_t dbgwcr[16]; /* watchpoint control registers */
uint64_t dbgclaim; /* DBGCLAIM bits */
uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */
uint64_t osdlr_el1; /* OS DoubleLock status */
@@ -1123,7 +1124,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
void arm_reset_sve_state(CPUARMState *env);
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
/*
* SVE registers are encoded in KVM's memory in an endianness-invariant format.
target/arm/debug_helper.c
+54
View File
@@ -632,6 +632,24 @@ static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.dbgclaim |= (value & 0xFF);
}
static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* CLAIM bits are RAO */
return 0xFF;
}
static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.dbgclaim &= ~(value & 0xFF);
}
static const ARMCPRegInfo debug_cp_reginfo[] = {
/*
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
@@ -664,6 +682,27 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL0_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
* OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
* It is a component of the Debug Communications Channel, which is not implemented.
*/
{ .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
* OSECCR_EL1 provides a mechanism for an operating system
* to access the contents of EDECCR. EDECCR is not implemented though,
* as is the rest of external device mechanism.
*/
{ .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
* it is unlikely a guest will care.
@@ -715,6 +754,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
/*
* Dummy DBGCLAIM registers.
* "The architecture does not define any functionality for the CLAIM tag bits.",
* so we only keep the raw bits
*/
{ .name = "DBGCLAIMSET_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
.type = ARM_CP_ALIAS,
.access = PL1_RW, .accessfn = access_tda,
.writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
.access = PL1_RW, .accessfn = access_tda,
.writefn = dbgclaimclr_write, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
target/arm/helper-sme.h
+1 -2
View File
@@ -17,8 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_3(set_svcr, TCG_CALL_NO_RWG, void, env, i32, i32)
DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
target/arm/helper.c
+38 -3
View File
@@ -6725,12 +6725,47 @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
/* ResetSVEState */
static void arm_reset_sve_state(CPUARMState *env)
{
memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
/* Recall that FFR is stored as pregs[16]. */
memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
vfp_set_fpcr(env, 0x0800009f);
}
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
{
uint64_t change = (env->svcr ^ new) & mask;
if (change == 0) {
return;
}
env->svcr ^= change;
if (change & R_SVCR_SM_MASK) {
arm_reset_sve_state(env);
}
/*
* ResetSMEState.
*
* SetPSTATE_ZA zeros on enable and disable. We can zero this only
* on enable: while disabled, the storage is inaccessible and the
* value does not matter. We're not saving the storage in vmstate
* when disabled either.
*/
if (change & new & R_SVCR_ZA_MASK) {
memset(env->zarray, 0, sizeof(env->zarray));
}
arm_rebuild_hflags(env);
}
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM));
helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA));
arm_rebuild_hflags(env);
aarch64_set_svcr(env, value, -1);
}
static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
target/arm/helper.h
+6 -5
View File
@@ -79,11 +79,12 @@ DEF_HELPER_2(v8m_stackcheck, void, env, i32)
DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32)
DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32)
DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32)
DEF_HELPER_3(set_cp_reg, void, env, cptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, cptr)
DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64)
DEF_HELPER_2(get_cp_reg64, i64, env, cptr)
DEF_HELPER_2(get_r13_banked, i32, env, i32)
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)

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