mirror of
https://github.com/izzy2lost/ppsspp.git
synced 2026-03-10 12:43:04 -07:00
1cb7965cb1
When these are invalidated, the block they point to gets invalidated too. Will be useful to implement various types of block merging and function inlining without affecting correctness of cache clears etc. Also, with this commit we can now fully inline replaced functions. fabsf() boils down to 1-2 instructions and the block continues, for example.
574 lines
16 KiB
C++
574 lines
16 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Reporting.h"
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#include "Core/Config.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/HLETables.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/ARM/ArmJit.h"
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#include "Core/MIPS/ARM/ArmRegCache.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#include "Common/ArmEmitter.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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#define LOOPOPTIMIZATION 0
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// We can disable nice delay slots.
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// #define CONDITIONAL_NICE_DELAYSLOT delaySlotIsNice = false;
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#define CONDITIONAL_NICE_DELAYSLOT ;
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using namespace MIPSAnalyst;
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namespace MIPSComp
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{
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void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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if (jo.immBranches && gpr.IsImm(rs) && gpr.IsImm(rt) && js.numInstructions < jo.continueMaxInstructions) {
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 rsImm = (s32)gpr.GetImm(rs);
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s32 rtImm = (s32)gpr.GetImm(rt);
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switch (cc) {
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case CC_EQ: skipBranch = rsImm == rtImm; break;
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case CC_NEQ: skipBranch = rsImm != rtImm; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSRTComp().");
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}
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if (skipBranch) {
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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// We might be able to flip the condition (EQ/NEQ are easy.)
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const bool canFlip = cc == CC_EQ || cc == CC_NEQ;
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Operand2 op2;
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bool negated;
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if (gpr.IsImm(rt) && TryMakeOperand2_AllowNegation(gpr.GetImm(rt), op2, &negated)) {
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gpr.MapReg(rs);
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if (!negated)
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CMP(gpr.R(rs), op2);
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else
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CMN(gpr.R(rs), op2);
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} else {
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if (gpr.IsImm(rs) && TryMakeOperand2_AllowNegation(gpr.GetImm(rs), op2, &negated) && canFlip) {
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gpr.MapReg(rt);
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if (!negated)
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CMP(gpr.R(rt), op2);
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else
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CMN(gpr.R(rt), op2);
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} else {
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gpr.MapInIn(rs, rt);
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CMP(gpr.R(rs), gpr.R(rt));
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}
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}
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ArmGen::FixupBranch ptr;
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if (!likely) {
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_CC(cc);
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} else {
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FlushAll();
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ptr = B_CC(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC+8, js.nextExit++);
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js.compiling = false;
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}
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void Jit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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if (jo.immBranches && gpr.IsImm(rs) && js.numInstructions < jo.continueMaxInstructions) {
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 imm = (s32)gpr.GetImm(rs);
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switch (cc) {
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case CC_GT: skipBranch = imm > 0; break;
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case CC_GE: skipBranch = imm >= 0; break;
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case CC_LT: skipBranch = imm < 0; break;
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case CC_LE: skipBranch = imm <= 0; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSZeroComp().");
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}
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if (skipBranch) {
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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if (andLink)
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.MapReg(rs);
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CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
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ArmGen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_CC(cc);
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}
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else
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{
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FlushAll();
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ptr = B_CC(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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if (andLink)
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{
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gpr.SetRegImm(R0, js.compilerPC + 8);
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STR(R0, CTXREG, MIPS_REG_RA * 4);
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}
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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void Jit::Comp_RelBranch(MIPSOpcode op)
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{
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// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
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switch (op >> 26)
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{
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case 4: BranchRSRTComp(op, CC_NEQ, false); break;//beq
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case 5: BranchRSRTComp(op, CC_EQ, false); break;//bne
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case 6: BranchRSZeroComp(op, CC_GT, false, false); break;//blez
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case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz
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case 20: BranchRSRTComp(op, CC_NEQ, true); break;//beql
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case 21: BranchRSRTComp(op, CC_EQ, true); break;//bnel
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case 22: BranchRSZeroComp(op, CC_GT, false, true); break;//blezl
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case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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void Jit::Comp_RelBranchRI(MIPSOpcode op)
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{
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, CC_LT, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, CC_LT, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
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case 17: BranchRSZeroComp(op, CC_LT, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
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case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
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case 19: BranchRSZeroComp(op, CC_LT, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.MapReg(MIPS_REG_FPCOND);
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TST(gpr.R(MIPS_REG_FPCOND), Operand2(1, TYPE_IMM));
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ArmGen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_CC(cc);
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}
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else
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{
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FlushAll();
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ptr = B_CC(cc);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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void Jit::Comp_FPUBranch(MIPSOpcode op)
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{
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, CC_NEQ, false); break; // bc1f
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case 1: BranchFPFlag(op, CC_EQ, false); break; // bc1t
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case 2: BranchFPFlag(op, CC_NEQ, true); break; // bc1fl
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case 3: BranchFPFlag(op, CC_EQ, true); break; // bc1tl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
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// The behavior is undefined - the CPU may take the second branch even if the first one passes.
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// However, it does consistently try each branch, which these games seem to expect.
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bool delaySlotIsBranch = MIPSCodeUtils::IsVFPUBranch(delaySlotOp);
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bool delaySlotIsNice = !delaySlotIsBranch && IsDelaySlotNiceVFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
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ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", js.compilerPC);
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int imm3 = (op >> 18) & 7;
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gpr.MapReg(MIPS_REG_VFPUCC);
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TST(gpr.R(MIPS_REG_VFPUCC), Operand2(1 << imm3, TYPE_IMM));
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ArmGen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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if (!delaySlotIsNice && !delaySlotIsBranch)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = B_CC(cc);
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}
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else
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{
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FlushAll();
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ptr = B_CC(cc);
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if (!delaySlotIsBranch)
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8);
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WriteExit(notTakenTarget, js.nextExit++);
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js.compiling = false;
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}
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void Jit::Comp_VBranch(MIPSOpcode op)
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{
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switch ((op >> 16) & 3)
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{
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case 0: BranchVFPUFlag(op, CC_NEQ, false); break; // bvf
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case 1: BranchVFPUFlag(op, CC_EQ, false); break; // bvt
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case 2: BranchVFPUFlag(op, CC_NEQ, true); break; // bvfl
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case 3: BranchVFPUFlag(op, CC_EQ, true); break; // bvtl
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}
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}
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void Jit::Comp_Jump(MIPSOpcode op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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u32 off = _IMM26 << 2;
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u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
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// Might be a stubbed address or something?
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if (!Memory::IsValidAddress(targetAddr))
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{
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if (js.nextExit == 0)
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ERROR_LOG_REPORT(JIT, "Jump to invalid address: %08x", targetAddr)
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else
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js.compiling = false;
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// TODO: Mark this block dirty or something? May be indication it will be changed by imports.
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return;
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}
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switch (op >> 26)
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{
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case 2: //j
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CompileDelaySlot(DELAYSLOT_NICE);
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if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions) {
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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FlushAll();
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WriteExit(targetAddr, js.nextExit++);
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break;
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case 3: //jal
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if (ReplaceJalTo(targetAddr))
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return;
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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CompileDelaySlot(DELAYSLOT_NICE);
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if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions) {
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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FlushAll();
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WriteExit(targetAddr, js.nextExit++);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_JumpReg(MIPSOpcode op)
|
|
{
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
MIPSGPReg rs = _RS;
|
|
MIPSGPReg rd = _RD;
|
|
bool andLink = (op & 0x3f) == 9;
|
|
|
|
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
|
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
|
|
if (andLink && rs == rd)
|
|
delaySlotIsNice = false;
|
|
CONDITIONAL_NICE_DELAYSLOT;
|
|
|
|
ARMReg destReg = R8;
|
|
if (IsSyscall(delaySlotOp)) {
|
|
gpr.MapReg(rs);
|
|
MovToPC(gpr.R(rs)); // For syscall to be able to return.
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_FLUSH);
|
|
return; // Syscall wrote exit code.
|
|
} else if (delaySlotIsNice) {
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
|
|
if (!andLink && rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {
|
|
// According to the MIPS ABI, there are some regs we don't need to preserve.
|
|
// Let's discard them so we don't need to write them back.
|
|
// NOTE: Not all games follow the MIPS ABI! Tekken 6, for example, will crash
|
|
// with this enabled.
|
|
gpr.DiscardR(MIPS_REG_COMPILER_SCRATCH);
|
|
for (int i = MIPS_REG_A0; i <= MIPS_REG_T7; i++)
|
|
gpr.DiscardR((MIPSGPReg)i);
|
|
gpr.DiscardR(MIPS_REG_T8);
|
|
gpr.DiscardR(MIPS_REG_T9);
|
|
}
|
|
|
|
if (jo.continueJumps && gpr.IsImm(rs) && js.numInstructions < jo.continueMaxInstructions) {
|
|
// Account for the increment in the loop.
|
|
js.compilerPC = gpr.GetImm(rs) - 4;
|
|
// In case the delay slot was a break or something.
|
|
js.compiling = true;
|
|
return;
|
|
}
|
|
|
|
gpr.MapReg(rs);
|
|
destReg = gpr.R(rs); // Safe because FlushAll doesn't change any regs
|
|
FlushAll();
|
|
} else {
|
|
// Delay slot - this case is very rare, might be able to free up R8.
|
|
gpr.MapReg(rs);
|
|
MOV(R8, gpr.R(rs));
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
FlushAll();
|
|
}
|
|
|
|
switch (op & 0x3f)
|
|
{
|
|
case 8: //jr
|
|
break;
|
|
case 9: //jalr
|
|
break;
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
|
|
WriteExitDestInR(destReg);
|
|
js.compiling = false;
|
|
}
|
|
|
|
|
|
void Jit::Comp_Syscall(MIPSOpcode op)
|
|
{
|
|
// If we're in a delay slot, this is off by one.
|
|
const int offset = js.inDelaySlot ? -1 : 0;
|
|
WriteDownCount(offset);
|
|
js.downcountAmount = -offset;
|
|
|
|
// TODO: Maybe discard v0, v1, and some temps? Definitely at?
|
|
FlushAll();
|
|
|
|
SaveDowncount();
|
|
// Skip the CallSyscall where possible.
|
|
void *quickFunc = GetQuickSyscallFunc(op);
|
|
if (quickFunc)
|
|
{
|
|
gpr.SetRegImm(R0, (u32)(intptr_t)GetSyscallInfo(op));
|
|
QuickCallFunction(R1, quickFunc);
|
|
}
|
|
else
|
|
{
|
|
gpr.SetRegImm(R0, op.encoding);
|
|
QuickCallFunction(R1, (void *)&CallSyscall);
|
|
}
|
|
RestoreDowncount();
|
|
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_Break(MIPSOpcode op)
|
|
{
|
|
Comp_Generic(op);
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
} // namespace Mipscomp
|