Henrik Rydgard
1cb7965cb1
Jit feature preparation: Introduce "proxy blocks".
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When these are invalidated, the block they point to gets invalidated too.
Will be useful to implement various types of block merging and function inlining
without affecting correctness of cache clears etc.
Also, with this commit we can now fully inline replaced functions. fabsf() boils
down to 1-2 instructions and the block continues, for example.
2013-12-19 00:39:49 +01:00
Unknown W. Brackets
763eff181d
Fix handling of jalr when delay slot changes rd.
2013-11-14 23:39:13 -08:00
Henrik Rydgård
ef8631c57f
Cache VFPU_CTRL_CC in a register
2013-11-12 17:58:29 +01:00
Henrik Rydgård
17074f5a7f
Cache fpcond in a register to avoid store/load between compare and branch
2013-11-12 10:33:38 +01:00
Unknown W. Brackets
bb960480c8
x86/armjit: Stop compiling on a jump to invalid.
2013-11-10 21:59:50 -08:00
Unknown W. Brackets
359110f010
x86/armjit: Add jump following (off by default.)
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Inlines function calls up to a certain extent. Allows us to get
immediates all the way to a syscall, for example, usually.
Not sure if faster.
2013-11-10 21:59:49 -08:00
Unknown W. Brackets
aacb31bc18
armjit: Copy over (disabled) immbranch optim.
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This does a little loop unrolling. Costs a bit more cache space, but
avoids flushing regs for longer.
Not enabled.
2013-11-10 21:59:48 -08:00
Unknown W. Brackets
7e46ee0b0f
armjit: Replace MOVI2R with using the regcache.
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So that it can optimize the value with existing imms.
Not actually optimizing yet.
2013-11-10 15:50:45 -08:00
Unknown W. Brackets
1cc68f50ca
armjit: Small optimization to syscall instr.
2013-11-10 14:38:10 -08:00
Unknown W. Brackets
b30928036e
armjit: Avoid flushing an imm in beq/bne/etc.
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We might be able to STMIA it instead.
2013-11-10 14:38:10 -08:00
Henrik Rydgard
5a95e267fb
Add an optimization to discard registers at the end of functions when possible.
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Works in some games but crashes many so hiding it for now. Do not add UI.
2013-11-08 12:43:48 +01:00
Henrik Rydgard
91393093bc
Re-enable the "nice delay slot" optimization on ARM
2013-11-07 15:29:12 +01:00
Henrik Rydgård
1e158fa652
ARM vtx dec: Preserving our FP scratch register appears to improve
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stability.
Also added some logging.
2013-11-06 11:47:26 +01:00
Henrik Rydgard
6483c0c2cd
Two minor armjit optimizations
2013-11-05 16:25:01 +01:00
Unknown W. Brackets
732ae13ebb
Fast path CallSyscall where possible.
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It seems we're spending a decent amount of time there, which isn't
entirely unexpected. We can eliminate some things easily.
2013-11-04 07:59:37 -08:00
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9a707f6c00
Fix typo, ARM build.
2013-10-17 15:28:50 -07:00
Unknown W. Brackets
2e8ef3027f
Write the retaddr to rd, not always ra, in jalr.
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Thanks go entirely to @Kingcom for pointing this out.
Don't know of any games not using RA as the rd.
2013-10-17 07:39:33 -07:00
Unknown W. Brackets
3a1b6fb269
Fix some sign comparison warnings.
2013-10-05 11:13:41 -07:00
Unknown W. Brackets
97aa1a631e
Improve typesafety in the x86 regalloc.
2013-08-24 19:41:10 -07:00
Unknown W. Brackets
109ad17ac6
Use a typesafe struct for opcodes.
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Also, correctly read delayslots using Read_Instruction on ARM.
2013-08-24 15:36:24 -07:00
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8327cd0f8e
Clean up some inconsistency in jit branches on arm.
2013-08-16 02:02:56 -07:00
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2758634a0f
Avoid overhead calling __KernelIdle().
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~1.8% improvement in Zettai Hero Project.
2013-08-15 01:35:17 -07:00
Unknown W. Brackets
5387e5c717
Oops, typo.
2013-08-15 00:38:53 -07:00
Unknown W. Brackets
df50e03146
Add a safety log for cases we don't handle right.
2013-08-14 23:14:25 -07:00
Unknown W. Brackets
e639f8d15f
Handle branches in VFPU delay slots better.
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Based on tests on a PSP, all branches are attempted. The behavior is
technically undefined.
It seems to take the delay slot's target if they differ and both pass.
This is the behavior the interpreter has, but it's more work in jit.
Since only a couple games seem to do this, and clearly expect this
behavior, this fixes all known cases of #1926 .
2013-08-14 22:56:02 -07:00
