mirror of
https://github.com/izzy2lost/ppsspp.git
synced 2026-03-10 12:43:04 -07:00
60bcc5b083
Otherwise, we don't actually break until later, which isn't great. Could be more optimal, "rewinding" regcache state.
313 lines
8.1 KiB
C++
313 lines
8.1 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Common/Profiler/Profiler.h"
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#include "Core/Core.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/ReplaceTables.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/IR/IRInterpreter.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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void X64JitBackend::CompIR_Basic(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Downcount:
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// As long as we don't care about flags, just use LEA.
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if (jo.downcountInRegister)
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LEA(32, DOWNCOUNTREG, MDisp(DOWNCOUNTREG, -(s32)inst.constant));
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else
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SUB(32, MDisp(CTXREG, downcountOffset), SImmAuto((s32)inst.constant));
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break;
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case IROp::SetConst:
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regs_.SetGPRImm(inst.dest, inst.constant);
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break;
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case IROp::SetConstF:
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regs_.Map(inst);
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if (inst.constant == 0) {
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XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));
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} else {
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MOV(32, R(SCRATCH1), Imm32(inst.constant));
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MOVD_xmm(regs_.FX(inst.dest), R(SCRATCH1));
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}
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break;
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case IROp::SetPC:
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regs_.Map(inst);
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MovToPC(regs_.RX(inst.src1));
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break;
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case IROp::SetPCConst:
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MOV(32, R(SCRATCH1), Imm32(inst.constant));
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MovToPC(SCRATCH1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_Breakpoint(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Breakpoint:
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FlushAll();
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// Note: the constant could be a delay slot.
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ABI_CallFunctionC((const void *)&IRRunBreakpoint, inst.constant);
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TEST(32, R(EAX), R(EAX));
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J_CC(CC_NZ, dispatcherCheckCoreState_, true);
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break;
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case IROp::MemoryCheck:
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{
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X64Reg addrBase = regs_.MapGPR(inst.src1);
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FlushAll();
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LEA(32, addrBase, MDisp(addrBase, inst.constant));
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MovFromPC(SCRATCH1);
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LEA(32, SCRATCH1, MDisp(SCRATCH1, inst.dest));
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ABI_CallFunctionRR((const void *)&IRRunMemCheck, SCRATCH1, addrBase);
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TEST(32, R(EAX), R(EAX));
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J_CC(CC_NZ, dispatcherCheckCoreState_, true);
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break;
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}
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_System(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Syscall:
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FlushAll();
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SaveStaticRegisters();
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#ifdef USE_PROFILER
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// When profiling, we can't skip CallSyscall, since it times syscalls.
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ABI_CallFunctionC((const u8 *)&CallSyscall, inst.constant);
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#else
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// Skip the CallSyscall where possible.
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{
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MIPSOpcode op(inst.constant);
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void *quickFunc = GetQuickSyscallFunc(op);
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if (quickFunc) {
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ABI_CallFunctionP((const u8 *)quickFunc, (void *)GetSyscallFuncPointer(op));
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} else {
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ABI_CallFunctionC((const u8 *)&CallSyscall, inst.constant);
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}
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}
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#endif
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LoadStaticRegisters();
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// This is always followed by an ExitToPC, where we check coreState.
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break;
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case IROp::CallReplacement:
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FlushAll();
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SaveStaticRegisters();
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ABI_CallFunction(GetReplacementFunc(inst.constant)->replaceFunc);
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LoadStaticRegisters();
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//SUB(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG), R(EAX));
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SUB(32, MDisp(CTXREG, downcountOffset), R(EAX));
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break;
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case IROp::Break:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_Transfer(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::SetCtrlVFPU:
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regs_.SetGPRImm(IRREG_VFPU_CTRL_BASE + inst.dest, (int32_t)inst.constant);
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break;
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case IROp::SetCtrlVFPUReg:
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regs_.Map(inst);
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MOV(32, regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1));
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break;
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case IROp::SetCtrlVFPUFReg:
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regs_.Map(inst);
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MOVD_xmm(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.FX(inst.src1));
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break;
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case IROp::FpCondFromReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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MOV(32, regs_.R(IRREG_FPCOND), regs_.R(inst.src1));
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break;
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case IROp::FpCondToReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });
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MOV(32, regs_.R(inst.dest), regs_.R(IRREG_FPCOND));
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break;
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case IROp::FpCtrlFromReg:
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case IROp::FpCtrlToReg:
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CompIR_Generic(inst);
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break;
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case IROp::VfpuCtrlToReg:
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regs_.Map(inst);
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MOV(32, regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1));
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break;
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case IROp::FMovFromGPR:
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if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));
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} else {
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regs_.Map(inst);
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MOVD_xmm(regs_.FX(inst.dest), regs_.R(inst.src1));
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}
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break;
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case IROp::FMovToGPR:
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regs_.Map(inst);
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MOVD_xmm(regs_.R(inst.dest), regs_.FX(inst.src1));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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int ReportBadAddress(uint32_t addr, uint32_t alignment, uint32_t isWrite) {
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const auto toss = [&](MemoryExceptionType t) {
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Core_MemoryException(addr, alignment, currentMIPS->pc, t);
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return coreState != CORE_RUNNING ? 1 : 0;
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};
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if (!Memory::IsValidRange(addr, alignment)) {
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MemoryExceptionType t = isWrite == 1 ? MemoryExceptionType::WRITE_WORD : MemoryExceptionType::READ_WORD;
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if (alignment > 4)
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t = isWrite ? MemoryExceptionType::WRITE_BLOCK : MemoryExceptionType::READ_BLOCK;
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return toss(t);
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} else if (alignment > 1 && (addr & (alignment - 1)) != 0) {
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return toss(MemoryExceptionType::ALIGNMENT);
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}
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return 0;
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};
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void X64JitBackend::CompIR_ValidateAddress(IRInst inst) {
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CONDITIONAL_DISABLE;
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bool isWrite = inst.src2 & 1;
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int alignment = 0;
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switch (inst.op) {
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case IROp::ValidateAddress8:
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alignment = 1;
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break;
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case IROp::ValidateAddress16:
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alignment = 2;
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break;
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case IROp::ValidateAddress32:
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alignment = 4;
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break;
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case IROp::ValidateAddress128:
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alignment = 16;
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break;
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default:
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INVALIDOP;
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break;
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}
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// This is unfortunate...
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FlushAll();
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regs_.Map(inst);
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LEA(PTRBITS, SCRATCH1, MDisp(regs_.RX(inst.src1), inst.constant));
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AND(32, R(SCRATCH1), Imm32(0x3FFFFFFF));
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std::vector<FixupBranch> validJumps;
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FixupBranch unaligned;
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if (alignment != 1) {
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TEST(32, R(SCRATCH1), Imm32(alignment - 1));
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unaligned = J_CC(CC_NZ);
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}
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CMP(32, R(SCRATCH1), Imm32(PSP_GetUserMemoryEnd() - alignment));
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FixupBranch tooHighRAM = J_CC(CC_A);
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CMP(32, R(SCRATCH1), Imm32(PSP_GetKernelMemoryBase()));
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validJumps.push_back(J_CC(CC_AE));
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CMP(32, R(SCRATCH1), Imm32(PSP_GetVidMemEnd() - alignment));
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FixupBranch tooHighVid = J_CC(CC_A);
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CMP(32, R(SCRATCH1), Imm32(PSP_GetVidMemBase()));
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validJumps.push_back(J_CC(CC_AE));
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CMP(32, R(SCRATCH1), Imm32(PSP_GetScratchpadMemoryEnd() - alignment));
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FixupBranch tooHighScratch = J_CC(CC_A);
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CMP(32, R(SCRATCH1), Imm32(PSP_GetScratchpadMemoryBase()));
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validJumps.push_back(J_CC(CC_AE));
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SetJumpTarget(tooHighRAM);
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SetJumpTarget(tooHighVid);
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SetJumpTarget(tooHighScratch);
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ABI_CallFunctionACC((const void *)&ReportBadAddress, R(SCRATCH1), alignment, isWrite);
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TEST(32, R(EAX), R(EAX));
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validJumps.push_back(J_CC(CC_Z));
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JMP(dispatcherCheckCoreState_, true);
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for (FixupBranch &b : validJumps)
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SetJumpTarget(b);
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}
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} // namespace MIPSComp
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#endif
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