Unknown W. Brackets
|
df313bd296
|
riscv: Fix rounding mode setting.
|
2023-07-25 20:33:56 -07:00 |
|
Unknown W. Brackets
|
05360d5c7a
|
riscv: Implement simplest float ops.
|
2023-07-25 20:33:56 -07:00 |
|
Unknown W. Brackets
|
7071884a47
|
riscv: Handle rounding mode and ctrl transfers.
|
2023-07-25 20:33:56 -07:00 |
|
Unknown W. Brackets
|
a8edf5fa24
|
riscv: Reduce bloat in jit fallbacks.
|
2023-07-25 19:42:04 -07:00 |
|
Unknown W. Brackets
|
4100767b5e
|
riscv: Optimize SetConst a bit.
|
2023-07-23 18:01:00 -07:00 |
|
Unknown W. Brackets
|
34bfe93ea5
|
riscv: Fix block lookup issues.
|
2023-07-23 18:01:00 -07:00 |
|
Unknown W. Brackets
|
c2da7d18bb
|
riscv: Stub out more IR compilation categories.
|
2023-07-23 18:01:00 -07:00 |
|
Unknown W. Brackets
|
bf7a6eb2cd
|
riscv: Add jit for some initial instructions.
|
2023-07-23 18:01:00 -07:00 |
|