mirror of
https://github.com/izzy2lost/ppsspp.git
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144 lines
3.2 KiB
C++
144 lines
3.2 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/MemMap.h"
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#include "Core/MIPS/RiscV/RiscVJit.h"
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#include "Core/MIPS/RiscV/RiscVRegCache.h"
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// This file contains compilation for basic PC/downcount accounting, debug funcs, etc.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace RiscVGen;
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using namespace RiscVJitConstants;
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void RiscVJit::CompIR_Basic(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::SetConst:
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gpr.SetImm(inst.dest, inst.constant);
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break;
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case IROp::SetConstF:
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CompIR_Generic(inst);
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break;
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case IROp::Downcount:
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if (inst.constant <= 2048) {
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ADDI(DOWNCOUNTREG, DOWNCOUNTREG, -(s32)inst.constant);
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} else {
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LI(SCRATCH1, inst.constant, SCRATCH2);
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SUB(DOWNCOUNTREG, DOWNCOUNTREG, SCRATCH1);
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}
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break;
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case IROp::SetPC:
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gpr.MapIn(inst.src1);
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MovToPC(gpr.R(inst.src1));
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break;
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case IROp::SetPCConst:
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LI(SCRATCH1, inst.constant, SCRATCH2);
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MovToPC(SCRATCH1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJit::CompIR_Transfer(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::SetCtrlVFPU:
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case IROp::SetCtrlVFPUReg:
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case IROp::SetCtrlVFPUFReg:
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case IROp::FpCondToReg:
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case IROp::VfpuCtrlToReg:
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case IROp::FMovFromGPR:
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case IROp::FMovToGPR:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJit::CompIR_System(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Interpret:
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case IROp::Syscall:
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case IROp::CallReplacement:
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case IROp::Break:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJit::CompIR_Breakpoint(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Breakpoint:
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case IROp::MemoryCheck:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJit::CompIR_ValidateAddress(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::ValidateAddress8:
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case IROp::ValidateAddress16:
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case IROp::ValidateAddress32:
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case IROp::ValidateAddress128:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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