Henrik Rydgård
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a7bc70834c
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Merge pull request #17907 from unknownbrackets/riscv-minor
riscv: Implement vs2i
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2023-08-14 07:41:45 +02:00 |
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Unknown W. Brackets
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52cc38bf2a
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riscv: Implement vs2i.
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2023-08-13 18:27:19 -07:00 |
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Unknown W. Brackets
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3f8f8d36d9
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riscv: Fix crash on clear icache.
Oops, can't avoid marking all blocks invalid. Luckily a syscall should
always take more bytes than the bail invalidated block code.
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2023-08-13 18:25:46 -07:00 |
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Unknown W. Brackets
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159b41a0fa
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irjit: Fuse unaligned svl.q/svr.q together.
They're almost never used outside paired, which we can do on most
platforms easily.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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5729de90d2
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irjit: Use more partial Vec4s / Vec4Blend.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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2e6dbab5fa
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irjit: Add flag to prefer Vec4, use for add/sub.
This will improve things when using SIMD.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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e0be6858b8
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irjit: Implement vcrs.t.
As used in Jeanne d'Arc.
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2023-08-13 18:10:12 -07:00 |
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Unknown W. Brackets
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217a1837ed
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irjit: Allow typical prefixes in vdiv/vasin/etc.
Some of these behave strangely, but there are some common usages that work
fine.
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2023-08-13 18:10:07 -07:00 |
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Bashar Astifan
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07c119a80c
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Merge branch 'master' of https://github.com/hrydgard/ppsspp
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2023-08-14 02:45:28 +04:00 |
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Unknown W. Brackets
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87668a5720
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Merge pull request #17902 from hrydgard/ui-bugfixes
Some debug overlays don't make sense when not in-game, disable them
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2023-08-13 13:13:16 -07:00 |
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Henrik Rydgård
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dc4de340b3
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Some debug overlays don't make sense when not in-game, disable them. Minor feedback fixes.
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2023-08-13 21:54:24 +02:00 |
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Henrik Rydgård
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5a9a2bf6fe
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Merge pull request #17779 from EmulatorJS/master
Cleanup emscripten libretro target
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2023-08-13 21:40:24 +02:00 |
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Henrik Rydgård
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2cdcc413b7
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Merge pull request #17898 from unknownbrackets/irjit-vfputemps
irjit: Cleanup/purge FPU/VFPU temps
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2023-08-13 21:08:00 +02:00 |
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Henrik Rydgård
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5dcd14b17a
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Merge pull request #17901 from unknownbrackets/riscv-disasm
riscv: Add debug log of block disasm
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2023-08-13 21:07:37 +02:00 |
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Unknown W. Brackets
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f03cd0b2ad
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Merge pull request #17899 from unknownbrackets/riscv-minor
Minor RISC-V cleanups, frame profiler fix
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2023-08-13 11:19:42 -07:00 |
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Henrik Rydgård
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d6cdb6e5d9
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Merge pull request #17900 from unknownbrackets/irjit-vsgelt
irjit: Implement vsge/vslt
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2023-08-13 19:59:14 +02:00 |
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Unknown W. Brackets
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23c79f8e7f
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irjit: Implement vsge/vslt.
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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5d20f2aabd
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irjit: Simplify VecDo3.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2bb67db43c
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riscv: Switch to the logBlocks model for disasm.
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2023-08-13 10:37:21 -07:00 |
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Unknown W. Brackets
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8c036a889d
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riscv: Add debug log of block disasm.
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2023-08-13 10:32:04 -07:00 |
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Unknown W. Brackets
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7cc6c5fa62
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riscv: Fix load error w/o pointerify.
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2023-08-13 10:20:28 -07:00 |
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Unknown W. Brackets
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be938a850b
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riscv: Remove FMul safety check.
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
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2023-08-13 10:20:20 -07:00 |
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Unknown W. Brackets
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fa53b80574
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irjit: Cleanup/purge FPU/VFPU temps.
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
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2023-08-13 10:14:10 -07:00 |
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Henrik Rydgård
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7bb1914fd3
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Add FrameTiming.cpp/h (with no real contents)
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2023-08-13 17:57:43 +02:00 |
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