Henrik Rydgard
6702f0c78c
Tiny optimization and bugfix
2013-03-07 00:47:48 +01:00
Henrik Rydgard
963a6603fc
Fix two armjit bugs the testrunner found.
2013-03-07 00:37:00 +01:00
Henrik Rydgard
a69b09a831
More work on TestRunner, now runs all the CPU tests.
2013-03-07 00:22:39 +01:00
Sacha
94a11ef3c0
Armjit: Implement movn, movz
2013-03-07 04:11:48 +10:00
Sacha
87de6be239
Fix the shift regs in ARM JIT that were causing graphical issues in some games. Set avoidload flag.
2013-03-07 02:39:28 +10:00
Sacha
d77632bfb0
Fix literal pools on games with very large code blocks (eg. Zero no Kieski).
...
Was flushing after an offset of 4088 which did not take in to account that a single MIPS instruction can turn in to numerous ARM instructions. Chose a safer value of 4020.
Was insta-flushing after reaching this offset value. Some code blocks are over 8K in size. Use a partialFlushOffset to keep track of when the next flush is required.
Was protecting flush branch manually. Can use B_CC(CC_AL) for this instead.
2013-03-07 02:25:27 +10:00
Sacha
8125d96ce1
Small update for shifted load/stores. Still disabled.
2013-03-07 01:04:41 +10:00
Sacha
a8b6fca61b
Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs.
2013-03-07 00:59:07 +10:00
Sacha
ae3b881a7f
Use correct args for Operand2(..) through armjit. Fix STR(..).
2013-03-07 00:59:07 +10:00
Sacha
268d16bd24
Use correct args for STR(..) throughout armjit.
2013-03-07 00:59:07 +10:00
Sacha
23fb88c5fe
Enable optimisation codepath (left+right combines).
2013-03-07 00:59:07 +10:00
Henrik Rydgard
9f327985fc
armjit: disable lwl/lwr/swl/swr
2013-03-05 23:09:26 +01:00
Sacha
5a134243a7
Armjit: Fix lwl, lwr and enable again. Thanks Sonic.
2013-03-06 03:28:28 +10:00
Sacha
7e67de3334
Armjit: Implement lwl, lwr, swl, swr in ARM JIT. lwr is currently disabled as it isn't working.
2013-03-06 02:11:36 +10:00
Sacha
9152d2f2bb
Armjit: Optimise swl+swr and lwl+lwr cases that can be combined to a single sw or lw. Add shift flags to STR/LDR. Add EatInstruction to ArmJit.
2013-03-06 02:11:36 +10:00
Sacha
33c6df55db
Build fix
2013-03-05 15:20:14 +10:00
Sacha
65a83d70c7
Armjit: Implement clo as well. Fix up the reg usage in div/divu comment.
2013-03-05 15:14:22 +10:00
Sacha
60b84e71d5
Armjit: Re-enable reg shifts. Thanks [Unknown] for finding the issue.
2013-03-05 14:55:33 +10:00
Sacha
4641cf376f
Armjit: Implement CLZ instruction. Disable reg shifts for now (breaks Wipeout Pure).
2013-03-05 14:16:35 +10:00
Sacha
4a56ebd0a0
Armjit: Add sllv, srlv, srav instructions (reg shift).
2013-03-05 13:52:03 +10:00
Sacha
10ad797c6d
Armjit stubs.
...
Add a double encoding for VCVT. Implement integer divide (but not working yet). Stubs for msub/msubu. Don't detect vfpv3 on Symbian.
2013-03-05 13:16:08 +10:00
Henrik Rydgard
3714eebbbe
Actually register scePspNpDrm_user
2013-03-04 23:54:03 +01:00
Henrik Rydgard
062c975b46
Ignore cache function 24.
2013-03-04 23:51:19 +01:00
Sacha
d5feb4d3ff
Quick build fix
2013-03-05 03:13:33 +10:00
Sacha
1089a31a45
Armjit: add reverse bit instruction.
2013-03-05 02:58:51 +10:00
