Unknown W. Brackets
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c085413326
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irjit: Consistently check vec4 safety.
Just to prevent confusion/surprises, this is clearer.
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2022-11-18 19:06:50 -08:00 |
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Unknown W. Brackets
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ada0674415
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irjit: Allow VV2Op SIMD with exact overlap.
None of these look at other lanes.
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2022-11-18 17:54:58 -08:00 |
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Unknown W. Brackets
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2419e5680a
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irjit: Correct VV2Op SIMD check.
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
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2022-11-18 17:53:53 -08:00 |
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Unknown W. Brackets
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0f79afa172
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interp: Support memory breakpoints too.
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2022-11-13 17:45:43 -08:00 |
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Unknown W. Brackets
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f9da9e6b60
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interp: Centralize memory size handling.
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2022-11-13 17:38:53 -08:00 |
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Unknown W. Brackets
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76cf4dbf12
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interp: Allow breakpoints in release mode.
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2022-11-13 16:52:40 -08:00 |
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Unknown W. Brackets
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1662bd3bb8
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interp: Allow resume from breakpoint.
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2022-11-13 16:03:29 -08:00 |
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Unknown W. Brackets
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46182990cf
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GPU: Hook US version of Marvel Alliance upload.
See #9852. Appears to be the same basic func, but something resulted in a
different hash. Register use for from/to seems the same.
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2022-11-11 21:51:25 -08:00 |
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Henrik Rydgård
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e97d5498c6
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Merge pull request #16306 from unknownbrackets/ir-prefixes
irjit: Correct prefix validation
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2022-10-31 09:11:52 +01:00 |
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Unknown W. Brackets
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eef29d5e95
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irjit: Correct prefix validation.
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
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2022-10-30 23:15:54 -07:00 |
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Unknown W. Brackets
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2da1bf7ffc
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interp: Correct dprefix accuracy for vrot.
Ignores cosine lane, not always x.
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2022-10-30 21:47:28 -07:00 |
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Unknown W. Brackets
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56ff555309
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irjit: Fix unordered float compares.
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2022-10-30 21:12:59 -07:00 |
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Henrik Rydgård
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ba32ef5ea5
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Merge pull request #16302 from unknownbrackets/vrot-overlap
Handle vrot overlap and vscl/vmscl prefixes more accurately
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2022-10-30 07:24:23 +01:00 |
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Unknown W. Brackets
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bbdc8a8f98
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interp: Correct vscl/vmscl t prefix handling.
This makes more sense. Fixes Dissidia 012 issues.
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2022-10-29 22:43:30 -07:00 |
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Unknown W. Brackets
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3f997518f3
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irjit: Handle vrot overlap more correctly.
Sine ignores overlap, cosine does not.
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2022-10-29 22:25:25 -07:00 |
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Unknown W. Brackets
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17d94cd358
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SaveState: Restore replacements in only one place.
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2022-10-29 17:59:35 -07:00 |
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Unknown W. Brackets
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0a98ac43fa
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Debugger: Allow currently-invalid memory reference.
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2022-10-29 17:43:35 -07:00 |
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Unknown W. Brackets
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b9de1a44df
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jit: Reduce some include pollution.
Usually no need for all of MIPSAnalyst.
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2022-10-27 23:26:44 -07:00 |
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Unknown W. Brackets
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813bfded92
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x86jit: Correct vh2f NAN handling (#16275)
* x86jit: Correct vh2f NAN handling.
Allows another test to pass.
* x86jit: Reuse MAccessibleDisp().
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2022-10-23 10:09:29 +02:00 |
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Henrik Rydgård
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0719f1d4ea
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Merge branch 'cheat-icache' (PR #16234)
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2022-10-16 09:55:30 +02:00 |
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Unknown W. Brackets
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0226d95000
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jit: Run invalidates immediately.
Previously, I thought we might clear native code when invalidating - we
don't. We only do that when clearing.
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2022-10-15 18:52:46 -07:00 |
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Unknown W. Brackets
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fa5f9d5e74
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jit: Consistently check range on invalidate.
We did this on x86, we should do it everywhere or nowhere.
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2022-10-15 18:30:13 -07:00 |
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Unknown W. Brackets
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c4bf2cb5c0
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jit: Ignore zero byte icache invalidates.
These were getting marked pending and were clearing all cache, causing
performance concerns in for example LittleBigPlanet.
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2022-10-15 18:27:52 -07:00 |
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Henrik Rydgård
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26f6afbfa7
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Followup to #16205, fix one more instance of the problem.
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2022-10-12 01:02:54 +02:00 |
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Henrik Rydgård
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df5b51990d
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ArmJit: Save/restore downcount where needed, we missed a few cases.
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2022-10-11 15:50:37 +02:00 |
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