135 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	624caa2dea	riscv: Implement the simplest exits.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	1dfedde741	riscv: Avoid needless save/load around compile.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	165169eb31	riscv: Implement load and store ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	05a2789cf4	riscv: Implement some simple assign instructions.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c6c25af484	riscv: Add some safety to pointerifying. ... We have to clear the upper bits in case of sign extension or other things.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	4c1cc2dfdc	riscv: Add a register cache for jit. ... Not yet actually used. Might be buggy.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	47b81985bd	riscv: Initial untested dispatcher. ... The minimum to actually, probably, running code. Pretty slow.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	e271e43ec5	riscv: Initial staffolding for IR based jit.	2023-07-23 18:01:00 -07:00