Unknown W. Brackets
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8dfc2f04d7
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riscv: Use a single reg for LO/HI.
This is the same optimization we have for arm64, basically.
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2023-08-20 14:49:09 -07:00 |
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Unknown W. Brackets
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36b6aa4728
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riscv: Allow GPR "SIMD" without FPR SIMD.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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cc4bc406d5
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riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e30fb82a64
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riscv: Remove some unused reg funcs.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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161465ab66
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riscv: Centralize register FlushAll().
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2023-08-19 21:30:03 -07:00 |
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Unknown W. Brackets
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f3d4bd8c11
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riscv: Centralize reg-as-pointer.
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2023-08-19 21:24:36 -07:00 |
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Unknown W. Brackets
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92f7374c89
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riscv: Centralize reg mapping itself.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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718a1b3944
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riscv: Centralize MarkDirty flagging.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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ebab0e1591
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riscv: Centralize reg allocation.
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2023-08-17 18:50:33 -07:00 |
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Unknown W. Brackets
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b30daa5760
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riscv: Centralize state of regcaches.
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2023-08-15 21:51:38 -07:00 |
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Henrik Rydgård
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a7bc70834c
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Merge pull request #17907 from unknownbrackets/riscv-minor
riscv: Implement vs2i
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2023-08-14 07:41:45 +02:00 |
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Unknown W. Brackets
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52cc38bf2a
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riscv: Implement vs2i.
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2023-08-13 18:27:19 -07:00 |
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Henrik Rydgård
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5dcd14b17a
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Merge pull request #17901 from unknownbrackets/riscv-disasm
riscv: Add debug log of block disasm
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2023-08-13 21:07:37 +02:00 |
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Unknown W. Brackets
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f03cd0b2ad
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Merge pull request #17899 from unknownbrackets/riscv-minor
Minor RISC-V cleanups, frame profiler fix
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2023-08-13 11:19:42 -07:00 |
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Henrik Rydgård
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d6cdb6e5d9
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Merge pull request #17900 from unknownbrackets/irjit-vsgelt
irjit: Implement vsge/vslt
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2023-08-13 19:59:14 +02:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2bb67db43c
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riscv: Switch to the logBlocks model for disasm.
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2023-08-13 10:37:21 -07:00 |
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Unknown W. Brackets
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8c036a889d
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riscv: Add debug log of block disasm.
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2023-08-13 10:32:04 -07:00 |
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Unknown W. Brackets
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7cc6c5fa62
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riscv: Fix load error w/o pointerify.
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2023-08-13 10:20:28 -07:00 |
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