36 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	067a033dc0	riscv: Add FPU regcache.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	b97b7f3663	riscv: Make some regcache methods private.	2023-07-25 19:42:04 -07:00
Unknown W. Brackets	b6f83ca969	riscv: Cleanup some pointerification flags.	2023-07-23 21:17:55 -07:00
Unknown W. Brackets	2c7da94bd1	riscv: Implement shifts and compares.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	8ee73264bf	riscv: Correct depointerify on FlushAll().	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	720f868a10	riscv: Use R_RA as a temporary for calls. ... This is the most logical thing, since we're about to write it anyway.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	d31eded9ba	riscv: Allow dirty pointers, explicitly.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	165169eb31	riscv: Implement load and store ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c6c25af484	riscv: Add some safety to pointerifying. ... We have to clear the upper bits in case of sign extension or other things.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	4c1cc2dfdc	riscv: Add a register cache for jit. ... Not yet actually used. Might be buggy.	2023-07-23 18:01:00 -07:00