Henrik Rydgård
|
2f300c2023
|
Merge pull request #18060 from unknownbrackets/x86-jitbase
x86jit: Bake emuhack mask into jitbase
|
2023-09-03 22:53:23 +02:00 |
|
Unknown W. Brackets
|
1d152a1486
|
x86jit: Bake emuhack mask into jitbase.
|
2023-09-03 12:49:36 -07:00 |
|
Unknown W. Brackets
|
1b756ff8c1
|
arm64jit: Add initial base for IR jit.
This works, but very slowly at this point.
|
2023-09-03 12:14:28 -07:00 |
|
Unknown W. Brackets
|
4b1c809886
|
x86jit: Implement a few more float ops, shuffle.
|
2023-08-27 23:24:30 -07:00 |
|
Unknown W. Brackets
|
07fa1ed573
|
x86jit: Automatically flush incompatible regs.
|
2023-08-21 21:16:54 -07:00 |
|
Unknown W. Brackets
|
db34b85107
|
irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
|
2023-08-21 20:46:05 -07:00 |
|
Unknown W. Brackets
|
36b6aa4728
|
riscv: Allow GPR "SIMD" without FPR SIMD.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
6a75e6712e
|
riscv: Use automapping for special cases too.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
a190793ad2
|
riscv: Simplify mapping for more instructions.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
cc4bc406d5
|
riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
e40ae60029
|
riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
f9bf7de701
|
riscv: Use a single reg cache.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
e30fb82a64
|
riscv: Remove some unused reg funcs.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
a23ade8f75
|
riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
|
2023-08-20 12:42:11 -07:00 |
|
Unknown W. Brackets
|
161465ab66
|
riscv: Centralize register FlushAll().
|
2023-08-19 21:30:03 -07:00 |
|
Unknown W. Brackets
|
f3d4bd8c11
|
riscv: Centralize reg-as-pointer.
|
2023-08-19 21:24:36 -07:00 |
|
Unknown W. Brackets
|
92f7374c89
|
riscv: Centralize reg mapping itself.
|
2023-08-19 16:15:49 -07:00 |
|
Unknown W. Brackets
|
718a1b3944
|
riscv: Centralize MarkDirty flagging.
|
2023-08-19 16:15:49 -07:00 |
|
Unknown W. Brackets
|
4e41f83ecc
|
riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
|
2023-08-17 23:03:31 -07:00 |
|
Unknown W. Brackets
|
ebab0e1591
|
riscv: Centralize reg allocation.
|
2023-08-17 18:50:33 -07:00 |
|
Unknown W. Brackets
|
b30daa5760
|
riscv: Centralize state of regcaches.
|
2023-08-15 21:51:38 -07:00 |
|
Unknown W. Brackets
|
b03398a46c
|
Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
|
2023-07-30 14:49:37 -07:00 |
|
Unknown W. Brackets
|
f870271011
|
riscv: Spill registers more intelligently.
|
2023-07-30 14:24:12 -07:00 |
|
Unknown W. Brackets
|
5ef4b2b5fa
|
riscv: Fix assert when flushing not mapped reg.
|
2023-07-30 14:19:28 -07:00 |
|
Unknown W. Brackets
|
c24e3ef831
|
riscv: Implement ll/sc.
|
2023-07-30 00:45:51 -07:00 |
|