38 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	8e8081c686	riscv: Implement VFPU compares.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	9c9330a207	riscv: Implement float conditional move.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	6d4fb949c2	riscv: Implement float compare ops.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	6b632a103d	riscv: Implement FSin/similar.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	e228748449	irjit: Add FCvtScaledSW to safely scale vi2f.	2023-07-29 18:30:15 -07:00
Unknown W. Brackets	a5a2671af3	irjit: Implement vf2ix. ... Used in LittleBigPlanet when playing intro movies.	2023-07-29 18:01:08 -07:00
Unknown W. Brackets	a181f6d5b8	riscv: Add a comment for FMUL testing later.	2023-07-27 22:16:29 -07:00
Unknown W. Brackets	ca7a520a19	riscv: Implement FMul.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	9a9b371856	riscv: Implement FSign using FCLASS.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	05360d5c7a	riscv: Implement simplest float ops.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	7071884a47	riscv: Handle rounding mode and ctrl transfers.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00