Unknown W. Brackets
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7a5cdafdf3
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arm64jit: Implement convert/int conversions.
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2023-09-08 00:03:12 -07:00 |
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Unknown W. Brackets
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a1304f6ac8
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arm64jit: Implement VFPU compare in IR.
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2023-09-06 19:02:24 -07:00 |
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Unknown W. Brackets
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97d9a7f07f
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arm64jit: Implement FCmp.
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2023-09-06 00:09:26 -07:00 |
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Unknown W. Brackets
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61a99b4bac
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x86jit: Implement trig/reciprocals.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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4b1c809886
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x86jit: Implement a few more float ops, shuffle.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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4e3f3860f9
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x86jit: Stub out op categories to files.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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b30daa5760
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riscv: Centralize state of regcaches.
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2023-08-15 21:51:38 -07:00 |
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Unknown W. Brackets
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be938a850b
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riscv: Remove FMul safety check.
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
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2023-08-13 10:20:20 -07:00 |
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Unknown W. Brackets
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4b9011e475
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riscv: Reduce call bloat using temps.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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268adf1aa1
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riscv: Implement scaled float/int convert.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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b03398a46c
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Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
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2023-07-30 14:49:37 -07:00 |
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Henrik Rydgård
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fa558b5b71
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Merge pull request #17813 from unknownbrackets/riscv-jit-fixes
Fix some typos and mistakes in RISC-V jit
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2023-07-30 23:41:13 +02:00 |
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Unknown W. Brackets
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020706f545
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riscv: Implement float saturate clamping.
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2023-07-30 14:24:12 -07:00 |
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Unknown W. Brackets
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09f3842a32
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riscv: Fix VFPU compare typos.
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2023-07-30 14:19:28 -07:00 |
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Unknown W. Brackets
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5db6b11ef2
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irjit: Cleanup self-fmovs.
These were sometimes getting emitted.
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2023-07-30 14:16:17 -07:00 |
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Unknown W. Brackets
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26a527bdf8
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riscv: Implement float/int conversion.
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2023-07-30 00:45:51 -07:00 |
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Henrik Rydgård
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b93275bb35
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Merge pull request #17800 from unknownbrackets/riscv-jit
More RISC-V jit ops
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2023-07-30 09:26:22 +02:00 |
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Unknown W. Brackets
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0036f3c494
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riscv: Implement FMin/FMax.
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2023-07-30 00:02:10 -07:00 |
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