Sacha
cc65b0add9
Fix rounding. Was disabling wrong rounding mode. Previous one wasn't merge-ready but should be OK now. Only tests that fail are VFPU now.
2013-03-07 22:34:20 +10:00
Sacha
b9ec281c55
Disable rounding methods that aren't working in hardware. Add some notes. Fix compare fall-through and choose right round method.
2013-03-07 21:33:30 +10:00
Unknown W. Brackets
cea396e901
armjit: Don't use R1 in the regcache.
...
This way it can be used in swl/swr/ins as a temp reg.
Note: those instructions are currently DISABLEd, though.
2013-03-07 02:09:13 -08:00
Unknown W. Brackets
925e4e42bd
armjit: Disable ext for now, breaks Disgaea?
2013-03-07 02:08:45 -08:00
Unknown W. Brackets
d525abbcad
Cleanup some indentation, more compares to 0.
2013-03-07 02:08:45 -08:00
Unknown W. Brackets
028e85dc92
Cleanup some differences between the two jits.
2013-03-07 02:08:44 -08:00
Sacha
2a9074d92f
Fix FPU comp UEQ case.
2013-03-07 14:46:11 +10:00
Henrik Rydgard
6702f0c78c
Tiny optimization and bugfix
2013-03-07 00:47:48 +01:00
Henrik Rydgard
963a6603fc
Fix two armjit bugs the testrunner found.
2013-03-07 00:37:00 +01:00
Henrik Rydgard
a69b09a831
More work on TestRunner, now runs all the CPU tests.
2013-03-07 00:22:39 +01:00
Sacha
94a11ef3c0
Armjit: Implement movn, movz
2013-03-07 04:11:48 +10:00
Sacha
87de6be239
Fix the shift regs in ARM JIT that were causing graphical issues in some games. Set avoidload flag.
2013-03-07 02:39:28 +10:00
Sacha
d77632bfb0
Fix literal pools on games with very large code blocks (eg. Zero no Kieski).
...
Was flushing after an offset of 4088 which did not take in to account that a single MIPS instruction can turn in to numerous ARM instructions. Chose a safer value of 4020.
Was insta-flushing after reaching this offset value. Some code blocks are over 8K in size. Use a partialFlushOffset to keep track of when the next flush is required.
Was protecting flush branch manually. Can use B_CC(CC_AL) for this instead.
2013-03-07 02:25:27 +10:00
Sacha
8125d96ce1
Small update for shifted load/stores. Still disabled.
2013-03-07 01:04:41 +10:00
Sacha
a8b6fca61b
Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs.
2013-03-07 00:59:07 +10:00
Sacha
ae3b881a7f
Use correct args for Operand2(..) through armjit. Fix STR(..).
2013-03-07 00:59:07 +10:00
Sacha
268d16bd24
Use correct args for STR(..) throughout armjit.
2013-03-07 00:59:07 +10:00
Sacha
23fb88c5fe
Enable optimisation codepath (left+right combines).
2013-03-07 00:59:07 +10:00
Henrik Rydgard
9f327985fc
armjit: disable lwl/lwr/swl/swr
2013-03-05 23:09:26 +01:00
Sacha
5a134243a7
Armjit: Fix lwl, lwr and enable again. Thanks Sonic.
2013-03-06 03:28:28 +10:00
Sacha
7e67de3334
Armjit: Implement lwl, lwr, swl, swr in ARM JIT. lwr is currently disabled as it isn't working.
2013-03-06 02:11:36 +10:00
Sacha
9152d2f2bb
Armjit: Optimise swl+swr and lwl+lwr cases that can be combined to a single sw or lw. Add shift flags to STR/LDR. Add EatInstruction to ArmJit.
2013-03-06 02:11:36 +10:00
Sacha
33c6df55db
Build fix
2013-03-05 15:20:14 +10:00
Sacha
65a83d70c7
Armjit: Implement clo as well. Fix up the reg usage in div/divu comment.
2013-03-05 15:14:22 +10:00
Sacha
60b84e71d5
Armjit: Re-enable reg shifts. Thanks [Unknown] for finding the issue.
2013-03-05 14:55:33 +10:00
