Unknown W. Brackets
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e783627947
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armjit: Use our I2R funcs on reg/reg math too.
When one is a known immediate. This should catch more cases, like:
ori v0, $0, 0xFFFF
and v1, v1, v0
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2014-03-14 19:15:43 -07:00 |
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Unknown W. Brackets
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8e979da0f9
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armjit: Use our I2R arm optimizations.
Should help cases of ori and andi most, but also addiu. They will all try
to use an optimized immediate (from another nearby value) if possible.
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2014-03-14 19:15:43 -07:00 |
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Unknown W. Brackets
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c229232236
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armjit: Specifically optimize check for negative.
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2014-03-14 19:15:39 -07:00 |
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Unknown W. Brackets
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628390f3fa
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armjit: Tiny optimization for cast to short.
See these sometimes in code, skip the load of R0 when we can.
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2014-03-14 19:15:39 -07:00 |
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Henrik Rydgard
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23e57b71e0
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Revert "Shave one instruction off slti and slt on ARM."
This reverts commit 04742e00fc.
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2013-11-30 16:06:16 +01:00 |
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Henrik Rydgard
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04742e00fc
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Shave one instruction off slti and slt on ARM.
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2013-11-30 15:53:21 +01:00 |
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Unknown W. Brackets
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dffa35ef2f
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When ins is used with a zero argument, don't OR.
Seems it's used effectively to mask out bits with rs=zero. Makes sense...
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2013-11-29 09:17:12 -08:00 |
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Unknown W. Brackets
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c50ab6d6aa
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armjit: Fix divu when divisor is a constant 1.
Fixes #4539 and #4520.
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2013-11-19 13:24:15 -08:00 |
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Henrik Rydgard
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4e0520131a
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Tiny optimization
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2013-11-15 20:32:23 +01:00 |
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Henrik Rydgard
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d17a5fefea
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ARM: Fix divide by 0 in software divide used on CPUs without HW divide.
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2013-11-15 20:24:20 +01:00 |
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Sacha
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20e8a81268
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Switch to compile-time ARMV7 define.
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2013-11-15 11:20:39 +10:00 |
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Henrik Rydgard
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9a14d33372
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Disable software divide that appears to be buggy, see #4539
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2013-11-14 17:25:02 +01:00 |
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Unknown W. Brackets
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ca7b2b554b
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armjit: fix major typo breaking mult/multu.
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2013-11-10 21:54:44 -08:00 |
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Unknown W. Brackets
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7e46ee0b0f
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armjit: Replace MOVI2R with using the regcache.
So that it can optimize the value with existing imms.
Not actually optimizing yet.
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2013-11-10 15:50:45 -08:00 |
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Unknown W. Brackets
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285ec1fad5
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armjit: Implement mult/multu for immediates.
Uncommon, but may reduce instructions a bit.
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2013-11-10 14:38:09 -08:00 |
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Unknown W. Brackets
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9bec82873c
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armjit: inline byteswaps of imm values.
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2013-11-10 14:38:08 -08:00 |
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Unknown W. Brackets
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06c8cb9174
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armjit: Do shifts with imms as much as possible.
This may even make an imm operand2 safe that wasn't before.
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2013-11-10 14:38:08 -08:00 |
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Unknown W. Brackets
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a3a061a69f
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armjit: Optimize a division by a power of two.
These really happen.
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2013-11-09 08:43:53 -08:00 |
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Unknown W. Brackets
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1776c85882
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armjit: Implement a software divide for divu.
It's not actually that much code.
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2013-11-09 08:43:52 -08:00 |
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Unknown W. Brackets
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b2a240d105
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armjit: Implement msub/msubu.
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2013-11-09 08:43:52 -08:00 |
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Unknown W. Brackets
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cb3bb73148
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armjit: Improve GPR typesafety.
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2013-11-09 08:24:15 -08:00 |
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Unknown W. Brackets
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945b8bf5c5
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armjit: optimize reverse subtract, avoid temp imms.
If we have a non-op2 imm, get rid of it asap. If we have a op2 friendly
imm, keep it.
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2013-11-09 08:18:43 -08:00 |
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Unknown W. Brackets
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415f22ecac
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armjit: Preserve imms on min/max as well.
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2013-11-09 08:18:43 -08:00 |
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Unknown W. Brackets
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5d46a82f43
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armjit: Use a MOV for add/or with 0.
Might skip the ALU, so might be faster.
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2013-11-08 11:41:57 -08:00 |
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Unknown W. Brackets
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b8e126e7ce
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armjit: Preserve imms in slt/sltu as possible.
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2013-11-08 11:41:57 -08:00 |
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