Unknown W. Brackets
df2462b1d9
irjit: Implement ll/sc.
...
These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
Unknown W. Brackets
6df939034a
Core: Cleanup some sign extensions for clarity.
2023-04-05 17:16:51 -07:00
Unknown W. Brackets
d3c06266c5
jit: Fix conditional disable flags.
2021-01-09 11:50:32 -08:00
Henrik Rydgård
4c034ce988
Make all the Comp_Cache implementations the same.
...
We have the informative comments in the interpreter implementation
anyway.
2020-10-16 09:13:41 +02:00
Henrik Rydgård
c5e0b799d9
Remove category from _assert_msg_ functions. We don't filter these by category anyway.
...
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
2020-07-19 20:33:25 +02:00
Henrik Rydgård
c80dd44da8
ARM/ARM64: Ignore invalid immediate addresses in delay slots, which may be conditional.
...
Should do something in x86's safe mem too, but leaving for later.
Replaces #11824
2019-02-23 10:15:09 +01:00
Unknown W. Brackets
419c1fbd73
Jit: Respect flags for jit types and features.
...
Left some free space for more.
2019-02-03 14:57:08 -08:00
Unknown W. Brackets
5510a69d41
armjit: Enable breakpoints.
2018-06-06 17:31:56 -07:00
Henrik Rydgård
ed776d8c0b
ARM: Delete obsolete comments and check
2017-08-18 13:48:11 +02:00
Florent Castelli
8c3552de74
cmake: Detect features at compile time
...
Instead of relying on manually passed down flags from CMake,
we now have ppsspp_config.h file to create the platform defines for us.
This improves support for multiplatform builds (such as iOS).
2016-10-19 12:31:19 +02:00
Henrik Rydgard
dc2f6a30fb
ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction.
2015-07-11 16:25:22 +02:00
Henrik Rydgård
a897723e6a
Separate out jit reading nearby instructions.
...
This makes it easier to use an IR for these things, or remove them.
2015-04-11 00:53:24 -07:00
Henrik Rydgard
05a8e2e35d
Some work towards being able to build two JITs together
...
This will be useful for testing/debugging, but not there yet.
2014-12-13 21:13:54 +01:00
Henrik Rydgard
51d55bd645
Namespacing cleanup (it's bad to do "using namespace" in a header)
2014-12-07 14:44:15 +01:00
Henrik Rydgard
4457dca4c9
Rename the ARM Jit class to ArmJit
2014-12-07 14:25:22 +01:00
Unknown W. Brackets
f6f943de63
jit: MAP_NOINIT should always mean MAP_DIRTY.
2014-11-29 00:14:08 -08:00
Unknown W. Brackets
5a89c17cf0
armjit: Allow R1 in regalloc, use LR as temp.
...
LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
2014-03-28 18:38:38 -07:00
Unknown W. Brackets
ca0a8d0269
armjit: fix lwl/lwr from an imm address.
...
Can't skip loading the reg value. Likely cause of #5057 , possibly other
bugs as well.
2014-03-13 00:23:00 -07:00
Henrik Rydgård
b2260149ae
ARM Jit: Avoid materializing some unnecessary immediates in loads/stores
2014-03-03 14:33:22 +01:00
Henrik Rydgard
5a02ea9ff4
Fix cache instruction on ARM
2013-12-10 13:26:32 +01:00
Unknown W. Brackets
98fb2e0402
armjit: Refer to R11 as MEMBASEREG for clarity.
2013-11-14 23:37:48 -08:00
Unknown W. Brackets
67eaa2fd1c
armjit: Optimize immediate load/stores in a row.
2013-11-10 16:32:48 -08:00
Unknown W. Brackets
7e46ee0b0f
armjit: Replace MOVI2R with using the regcache.
...
So that it can optimize the value with existing imms.
Not actually optimizing yet.
2013-11-10 15:50:45 -08:00
Unknown W. Brackets
455a7e090d
Compile the cache instruction to nothing.
...
Was showing up in a few profiles, does nothing currently.
2013-11-10 14:38:10 -08:00
Unknown W. Brackets
b2c2a87511
Fix omitted CC_AL reset, fixes #4498 .
...
Was breaking non-fastmem lwl/lwr/etc.
2013-11-10 09:24:40 -08:00
