mirror of
https://github.com/izzy2lost/libultraship.git
synced 2026-06-19 01:16:13 -07:00
louist103
@@ -21,7 +21,6 @@
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#include "libultra/r4300.h"
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#include "libultra/rcp.h"
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#include "libultra/rdp.h"
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#include "libultra/rsp.h"
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#include "libultra/sptask.h"
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#include "libultra/thread.h"
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#include "libultra/time.h"
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@@ -1,57 +1,219 @@
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#ifndef ULTRA64_RCP_H
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#define ULTRA64_RCP_H
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#define HW_REG(reg, type) *(volatile type*)((reg) | 0xA0000000)
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#define IO_READ(addr) (*(vu32*)PHYS_TO_K1(addr))
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#define IO_WRITE(addr, data) (*(vu32*)PHYS_TO_K1(addr) = (u32)(data))
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/**
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* PIF Physical memory map (total size = 2 KB)
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*
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* Size Description Mode
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* 1FC007FF +-------+-----------------+-----+
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* | 64 B | JoyChannel RAM | R/W |
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* 1FC007C0 +-------+-----------------+-----+
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* |1984 B | Boot ROM | * | * = Reserved
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* 1FC00000 +-------+-----------------+-----+
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*/
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#define PIF_ROM_START 0x1FC00000
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#define PIF_ROM_END 0x1FC007BF
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#define PIF_RAM_START 0x1FC007C0
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#define PIF_RAM_END 0x1FC007FF
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#define AI_DRAM_ADDR_REG 0x04500000
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#define AI_LEN_REG 0x04500004
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#define AI_CONTROL_REG 0x04500008
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#define AI_STATUS_REG 0x0450000C
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#define AI_DACRATE_REG 0x04500010
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#define AI_BITRATE_REG 0x04500014
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/*
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* Patterns to interpret VI_CONTROL_REG
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*/
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#define VI_CTRL_TYPE_16 0x00002 /* [1:0] pixel size: 16 bit */
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#define VI_CTRL_TYPE_32 0x00003 /* [1:0] pixel size: 32 bit */
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#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* 2: default = on */
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#define VI_CTRL_GAMMA_ON 0x00008 /* 3: default = on */
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#define VI_CTRL_DIVOT_ON 0x00010 /* 4: default = on */
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#define VI_CTRL_SERRATE_ON 0x00040 /* 6: on if interlaced */
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#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* [9:8] anti-alias mode */
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#define VI_CTRL_ANTIALIAS_MODE_1 0x00100 /* Bit [9:8] anti-alias mode */
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#define VI_CTRL_ANTIALIAS_MODE_2 0x00200 /* Bit [9:8] anti-alias mode */
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#define VI_CTRL_ANTIALIAS_MODE_3 0x00300 /* Bit [9:8] anti-alias mode */
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#define VI_CTRL_PIXEL_ADV_MASK 0x01000 /* [15:12] pixel advance mode? */
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#define VI_CTRL_PIXEL_ADV_1 0x01000 /* Bit [15:12] pixel advance mode? */
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#define VI_CTRL_PIXEL_ADV_2 0x02000 /* Bit [15:12] pixel advance mode? */
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#define VI_CTRL_PIXEL_ADV_3 0x03000 /* Bit [15:12] pixel advance mode? */
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#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* 16: dither-filter mode */
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#define AI_CONTROL_DMA_ON 0x01
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#define AI_CONTROL_DMA_OFF 0x00
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#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
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#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
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#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
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#define AI_STATUS_AI_FULL (1 << 31)
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#define AI_STATUS_AI_BUSY (1 << 30)
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/**
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* Audio Interface (AI) Registers
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*/
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#define AI_BASE_REG 0x04500000
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#define VI_STATUS_REG 0x04400000
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#define VI_CONTROL_REG VI_STATUS_REG
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#define VI_ORIGIN_REG 0x04400004
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#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
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#define VI_WIDTH_REG 0x04400008
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#define VI_H_WIDTH_REG VI_WIDTH_REG
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#define VI_INTR_REG 0x0440000C
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#define VI_V_INTER_REG VI_H_WIDTH_REG
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#define VI_CURRENT_REG 0x04400010
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#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
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#define VI_BURST_REG 0x04400014
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#define VI_TIMING_REG VI_BURST_REG
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#define VI_V_SYNC_REG 0x04400018 // VI vertical sync
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#define VI_H_SYNC_REG 0x0440001C // VI horizontal sync
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#define VI_LEAP_REG 0x04400020 // VI horizontal sync leap
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#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
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#define VI_H_START_REG 0x04400024 // VI horizontal video
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#define VI_H_VIDEO_REG VI_H_START_REG
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#define VI_V_START_REG 0x04400028 // VI vertical video
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#define VI_V_VIDEO_REG VI_V_START_REG
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#define VI_V_BURST_REG 0x0440002C // VI vertical burst
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#define VI_X_SCALE_REG 0x04400030 // VI x-scale
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#define VI_Y_SCALE_REG 0x04400034 // VI y-scale
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/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
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#define AI_DRAM_ADDR_REG (AI_BASE_REG + 0x00) /* R0: DRAM address */
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#define SP_IMEM_START 0x04001000
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/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
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/* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
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#define AI_LEN_REG (AI_BASE_REG + 0x04) /* R1: Length */
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/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
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#define AI_CONTROL_REG (AI_BASE_REG + 0x08) /* R2: DMA Control */
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/* Value for control register */
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#define AI_CONTROL_DMA_ON 1 /* LSB = 1: DMA enable*/
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#define AI_CONTROL_DMA_OFF 0 /* LSB = 1: DMA enable*/
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/*
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* AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy
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* Note that a 1->0 transition in ai_full will set interrupt
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* (W): clear audio interrupt
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*/
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#define AI_STATUS_REG (AI_BASE_REG + 0x0C) /* R3: Status */
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/* Value for status register */
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#define AI_STATUS_FIFO_FULL (1 << 31)
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#define AI_STATUS_DMA_BUSY (1 << 30)
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/*
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* AI DAC sample period register (W): [13:0] dac rate
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* - vid_clock/(dperiod + 1) is the DAC sample rate
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* - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
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*/
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#define AI_DACRATE_REG (AI_BASE_REG + 0x10) /* R4: DAC rate 14-lsb*/
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/* DAC rate = video clock / audio frequency
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* - DAC rate >= (66 * Bit rate) must be true
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*/
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#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */
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#define AI_MIN_DAC_RATE 132
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/*
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* AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
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* - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
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* - The abus clock stops if aclockhp is zero
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*/
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#define AI_BITRATE_REG (AI_BASE_REG + 0x14) /* R5: Bit rate 4-lsb */
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/* Bit rate <= (DAC rate / 66) */
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#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */
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#define AI_MIN_BIT_RATE 2
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#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
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#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
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#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
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#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
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#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
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#define DEVICE_TYPE_CART 0 /* ROM cartridge */
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#define DEVICE_TYPE_BULK 1 /* ROM bulk */
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#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
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#define DEVICE_TYPE_SRAM 3 /* SRAM */
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#define DEVICE_TYPE_INIT 7 /* initial value */
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/**
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* Signal Processor (SP) Memory
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*/
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#define SP_DMEM_START 0x04000000
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#define SP_DMEM_END 0x04000FFF
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#define SP_IMEM_START 0x04001000
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#define SP_IMEM_END 0x04001FFF
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#define SP_MEM_ADDR_REG 0x04040000
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#define SP_DRAM_ADDR_REG 0x04040004
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#define SP_RD_LEN_REG 0x04040008
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#define SP_WR_LEN_REG 0x0404000C
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#define SP_STATUS_REG 0x04040010
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#define SP_DMA_FULL_REG 0x04040014
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#define SP_DMA_BUSY_REG 0x04040018
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#define SP_PC_REG 0x04080000
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/**
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* SP_STATUS_REG: write bits
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*/
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#define SP_CLR_HALT (1 << 0)
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#define SP_SET_HALT (1 << 1)
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#define SP_CLR_BROKE (1 << 2)
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#define SP_CLR_INTR (1 << 3)
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#define SP_SET_INTR (1 << 4)
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#define SP_CLR_SSTEP (1 << 5)
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#define SP_SET_SSTEP (1 << 6)
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#define SP_CLR_INTR_BREAK (1 << 7)
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#define SP_SET_INTR_BREAK (1 << 8)
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#define SP_CLR_SIG0 (1 << 9)
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#define SP_SET_SIG0 (1 << 10)
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#define SP_CLR_SIG1 (1 << 11)
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#define SP_SET_SIG1 (1 << 12)
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#define SP_CLR_SIG2 (1 << 13)
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#define SP_SET_SIG2 (1 << 14)
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#define SP_CLR_SIG3 (1 << 15)
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#define SP_SET_SIG3 (1 << 16)
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#define SP_CLR_SIG4 (1 << 17)
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#define SP_SET_SIG4 (1 << 18)
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#define SP_CLR_SIG5 (1 << 19)
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#define SP_SET_SIG5 (1 << 20)
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#define SP_CLR_SIG6 (1 << 21)
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#define SP_SET_SIG6 (1 << 22)
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#define SP_CLR_SIG7 (1 << 23)
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#define SP_SET_SIG7 (1 << 24)
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/*
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* SP_STATUS_REG: read bits
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*/
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#define SP_STATUS_HALT (1 << 0)
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#define SP_STATUS_BROKE (1 << 1)
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#define SP_STATUS_DMA_BUSY (1 << 2)
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#define SP_STATUS_DMA_FULL (1 << 3)
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#define SP_STATUS_IO_FULL (1 << 4)
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#define SP_STATUS_SSTEP (1 << 5)
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#define SP_STATUS_INTR_BREAK (1 << 6)
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#define SP_STATUS_SIG0 (1 << 7)
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#define SP_STATUS_SIG1 (1 << 8)
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#define SP_STATUS_SIG2 (1 << 9)
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#define SP_STATUS_SIG3 (1 << 10)
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#define SP_STATUS_SIG4 (1 << 11)
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#define SP_STATUS_SIG5 (1 << 12)
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#define SP_STATUS_SIG6 (1 << 13)
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#define SP_STATUS_SIG7 (1 << 14)
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/**
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* SP_STATUS_REG: use of SIG bits
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*/
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#define SP_CLR_YIELD SP_CLR_SIG0
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#define SP_SET_YIELD SP_SET_SIG0
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#define SP_STATUS_YIELD SP_STATUS_SIG0
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#define SP_CLR_YIELDED SP_CLR_SIG1
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#define SP_SET_YIELDED SP_SET_SIG1
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#define SP_STATUS_YIELDED SP_STATUS_SIG1
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#define SP_CLR_TASKDONE SP_CLR_SIG2
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#define SP_SET_TASKDONE SP_SET_SIG2
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#define SP_STATUS_TASKDONE SP_STATUS_SIG2
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#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
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#define SP_SET_RSPSIGNAL SP_SET_SIG3
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#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
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#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
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#define SP_SET_CPUSIGNAL SP_SET_SIG4
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#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
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#define VI_STATUS_REG 0x04400000
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#define VI_CONTROL_REG 0x04400000
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#define VI_ORIGIN_REG 0x04400004
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#define VI_DRAM_ADDR_REG 0x04400004
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#define VI_WIDTH_REG 0x04400008
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#define VI_H_WIDTH_REG 0x04400008
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#define VI_INTR_REG 0x0440000C
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#define VI_V_INTER_REG 0x0440000C
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#define VI_CURRENT_REG 0x04400010
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#define VI_V_CURRENT_LINE_REG 0x04400010
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#define VI_BURST_REG 0x04400014
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#define VI_TIMING_REG 0x04400014
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#define VI_V_SYNC_REG 0x04400018 // VI vertical sync
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#define VI_H_SYNC_REG 0x0440001C // VI horizontal sync
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#define VI_LEAP_REG 0x04400020 // VI horizontal sync leap
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||||
#define VI_H_SYNC_LEAP_REG 0x04400020
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#define VI_H_START_REG 0x04400024 // VI horizontal video
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#define VI_H_VIDEO_REG 0x04400024
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#define VI_V_START_REG 0x04400028 // VI vertical video
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||||
#define VI_V_VIDEO_REG 0x04400028
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#define VI_V_BURST_REG 0x0440002C // VI vertical burst
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||||
#define VI_X_SCALE_REG 0x04400030 // VI x-scale
|
||||
#define VI_Y_SCALE_REG 0x04400034 // VI y-scale
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||||
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||||
#define PI_DRAM_ADDR_REG 0x04600000 // PI DRAM address
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||||
#define PI_CART_ADDR_REG 0x04600004 // PI pbus (cartridge) address
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||||
#define PI_RD_LEN_REG 0x04600008 // PI read length
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@@ -68,33 +230,43 @@
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#define PI_BSD_DOM2_PGS_REG 0x0460002C // PI dom2 page size
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||||
#define PI_BSD_DOM2_RLS_REG 0x04600030 // PI dom2 release
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||||
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||||
#define PI_STATUS_BUSY 0x1
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#define PI_STATUS_IOBUSY 0x2
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#define PI_STATUS_ERROR 0x4
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#define PI_STATUS_DMA_BUSY (1 << 0)
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#define PI_STATUS_IO_BUSY (1 << 1)
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#define PI_STATUS_ERROR (1 << 2)
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||||
#define PI_STATUS_RESET_CONTROLLER 0x1
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#define PI_STATUS_CLEAR_INTR 0x2
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/*
|
||||
* PI_STATUS_REG: write bits
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||||
*/
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||||
#define PI_STATUS_RESET (1 << 0)
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||||
#define PI_SET_RESET PI_STATUS_RESET
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#define SI_DRAM_ADDR_REG 0x04800000
|
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#define SI_PIF_ADDR_RD64B_REG 0x04800004
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#define SI_PIF_ADDR_WR64B_REG 0x04800010
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||||
#define SI_STATUS_REG 0x04800018
|
||||
#define PI_STATUS_CLR_INTR (1 << 1)
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||||
#define PI_CLR_INTR PI_STATUS_CLR_INTR
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||||
|
||||
#define SI_STATUS_DMA_BUSY 0x1
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||||
#define SI_STATUS_IO_READ_BUSY 0x2
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||||
#define SI_STATUS_DMA_ERROR 0x8
|
||||
#define PI_DMA_BUFFER_SIZE 128
|
||||
|
||||
#define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */
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||||
#define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */
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||||
#define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */
|
||||
#define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */
|
||||
#define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */
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||||
|
||||
/**
|
||||
* Serial Interface (SI) Registers
|
||||
*/
|
||||
#define SI_BASE_REG 0x04800000
|
||||
|
||||
#define SI_DRAM_ADDR_REG (SI_BASE_REG + 0x00)
|
||||
#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG + 0x04)
|
||||
#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG + 0x10)
|
||||
#define SI_STATUS_REG (SI_BASE_REG + 0x18)
|
||||
|
||||
#define SI_STATUS_DMA_BUSY (1 << 0)
|
||||
#define SI_STATUS_IO_READ_BUSY (1 << 1)
|
||||
#define SI_STATUS_DMA_ERROR (1 << 3)
|
||||
#define SI_STATUS_INTERRUPT (1 << 12)
|
||||
|
||||
#define PIF_RAM_START 0x1FC007C0
|
||||
|
||||
#define MI_INIT_MODE_REG 0x04300000
|
||||
#define MI_MODE_REG MI_INIT_MODE_REG
|
||||
#define MI_VERSION_REG 0x04300004
|
||||
#define MI_INTR_REG 0x04300008
|
||||
#define MI_INTR_MASK_REG 0x0430000C
|
||||
|
||||
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
|
||||
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
|
||||
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
|
||||
#define IO_READ(addr) (*(vu32*)PHYS_TO_K1(addr))
|
||||
#define IO_WRITE(addr, data) (*(vu32*)PHYS_TO_K1(addr) = (u32)(data))
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
#ifndef ULTRA64_RSP_H
|
||||
#define ULTRA64_RSP_H
|
||||
|
||||
/* SP Status Flags */
|
||||
#define SP_STATUS_HALT 0x001
|
||||
#define SP_STATUS_BROKE 0x002
|
||||
#define SP_STATUS_DMA_BUSY 0x004
|
||||
#define SP_STATUS_DMA_FULL 0x008
|
||||
#define SP_STATUS_IO_FULL 0x010
|
||||
#define SP_STATUS_SSTEP 0x020
|
||||
#define SP_STATUS_INTR_BREAK 0x040
|
||||
#define SP_STATUS_YIELD 0x080
|
||||
#define SP_STATUS_YIELDED 0x100
|
||||
#define SP_STATUS_TASKDONE 0x200
|
||||
// #define SP_STATUS_SIG0 0x080
|
||||
// #define SP_STATUS_SIG1 0x100
|
||||
// #define SP_STATUS_SIG2 0x200
|
||||
#define SP_STATUS_SIG3 0x400
|
||||
#define SP_STATUS_SIG4 0x800
|
||||
#define SP_STATUS_SIG5 0x1000
|
||||
#define SP_STATUS_SIG6 0x2000
|
||||
#define SP_STATUS_SIG7 0x4000
|
||||
|
||||
#define SP_CLR_HALT 0x00001
|
||||
#define SP_SET_HALT 0x00002
|
||||
#define SP_CLR_BROKE 0x00004
|
||||
#define SP_CLR_INTR 0x00008
|
||||
#define SP_SET_INTR 0x00010
|
||||
#define SP_CLR_SSTEP 0x00020
|
||||
#define SP_SET_SSTEP 0x00040
|
||||
#define SP_CLR_INTR_BREAK 0x00080
|
||||
#define SP_SET_INTR_BREAK 0x00100
|
||||
#define SP_CLR_SIG0 0x00200
|
||||
#define SP_SET_SIG0 0x00400
|
||||
#define SP_CLR_SIG1 0x00800
|
||||
#define SP_SET_SIG1 0x01000
|
||||
#define SP_CLR_SIG2 0x02000
|
||||
#define SP_SET_SIG2 0x04000
|
||||
#define SP_CLR_SIG3 0x08000
|
||||
#define SP_SET_SIG3 0x10000
|
||||
#define SP_CLR_SIG4 0x20000
|
||||
#define SP_SET_SIG4 0x40000
|
||||
#define SP_CLR_SIG5 0x80000
|
||||
#define SP_SET_SIG5 0x100000
|
||||
#define SP_CLR_SIG6 0x200000
|
||||
#define SP_SET_SIG6 0x400000
|
||||
#define SP_CLR_SIG7 0x800000
|
||||
#define SP_SET_SIG7 0x1000000
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user