139 Commits

Author SHA1 Message Date
JosJuice
58487f1633 Jit: Implement error-free transformation for single-precision FMA
This implements the equivalent of 07443e2d41 in Jit64 and JitArm64.
Aims to fix https://bugs.dolphin-emu.org/issues/13865.
2026-01-18 20:02:49 +01:00
Joshua Vandaƫle
2383e68fd8 x64Emitter: Fix missing-declarations warning 2025-10-30 12:35:22 +01:00
Martino Fontana
f6e5448b43 Jit64: Dynamic length of regular jump instruction (for known addresses)
Conditional jumps already do that, so let's be consistent.
2025-10-08 00:15:57 +02:00
Martino Fontana
4f737b7aaf dcbz: Fix AVX path 2025-10-01 21:09:18 +02:00
Martino Fontana
d1ba849876 Jit64: dcbz, use VMOVAPS with YMM registers on AVX CPUs
LLVM does this, so let's do it as well.
2025-09-02 23:15:27 +02:00
Martino Fontana
5e69da7eba x64Emitter: Support YMM registers
This is accomplished by adding a 0x100 bit the the register.
Made sure that, on AVX instructions, that bit is trucated.
2025-09-02 22:15:16 +02:00
mitaclaw
ffc7bcfbf8 Emitters: Define Trivial Getters Inline 2024-07-21 21:35:29 -07:00
Dentomologist
04fcf68176 xEmitter: Convert PrefetchLevel to enum class 2023-06-17 16:41:32 -07:00
Dentomologist
4c2759f541 XEmitter: Add enum class Jump
Replace the bool parameter force5bytes in J, JMP, and J_CC with an enum
class Jump::Short/Near. Many callers set that parameter to the literal
'true', which was unclear if you didn't already know what it did.
2023-06-12 13:04:18 -07:00
Pokechu22
44e93e91d7 Common/Assert: Switch to fmt 2022-01-09 12:43:11 -08:00
Pokechu22
2025763420 Treewide: Adjust order of includes 2021-12-10 14:49:57 -08:00
Pierre Bourdon
e149ad4f0a treewide: convert GPLv2+ license info to SPDX tags
SPDX standardizes how source code conveys its copyright and licensing
information. See https://spdx.github.io/spdx-spec/1-rationale/ . SPDX
tags are adopted in many large projects, including things like the Linux
kernel.
2021-07-05 04:35:56 +02:00
Tillmann Karras
afb9398059 x64Emitter: remove unused x87 instructions 2021-06-28 02:56:37 +01:00
Lioncash
139d4fc76e General: Convert PanicAlerts over to fmt equivalent
Converts lingering panic alert calls over to the fmt-capable ones.
2020-12-02 13:38:33 -05:00
Lioncash
4e8df93f41 Common: Migrate logging to fmt
Continues the migration of our code over to the fmt logger.
2020-10-23 14:58:03 -04:00
Admiral H. Curtiss
5b52b3e9cb x64Emitter: Check end of allocated space when emitting code. 2020-08-24 19:31:32 +02:00
Sintendo
f82c38e156 X64Emitter: Remove obsolete TODO
TODO was already taken care of in PR #941.
2020-01-13 08:43:42 +01:00
Sintendo
bdfc472751 x64Emitter: Refactor OpArg::WriteRest
Shorter, displacement is now handled in one location.
2020-01-13 08:43:42 +01:00
Sintendo
cde3a3b448 x64Emitter: Avoid 8-bit displacement when possible
Due to the way the ModRM encoding works on x86, memory addressing
combinations involving RBP or R13 need an additional byte for an 8-bit
displacement of zero.

However, this was also applied in cases where it is unnecessary,
effectively wasting a byte.

- MatR with RSP or R12

8B 44 24 00          mov         eax,dword ptr [rsp]
8B 04 24             mov         eax,dword ptr [rsp]

- MRegSum with base != RBP or R13

46 8D 7C 37 00       lea         r15d,[rdi+r14]
46 8D 3C 37          lea         r15d,[rdi+r14]

- MComplex without offset

8B 4C CA 00          mov         ecx,dword ptr [rdx+rcx*8]
8B 0C CA             mov         ecx,dword ptr [rdx+rcx*8]
2020-01-13 08:43:42 +01:00
Sintendo
c84f34bd50 x64Emitter: Short MOVs for 32bit immediates
Prior to this commit, the emitter would emit a 7-byte instruction when
loading a 32-bit immediate to a 64-bit register.

0:  48 c7 c0 ff ff ff 7f    mov    rax,0x7fffffff

With this change, it will check if it can instead emit a load to a
32-bit register, which takes only 5 or 6 bytes.

0:  b8 ff ff ff 7f          mov    eax,0x7fffffff
2019-05-29 01:04:09 +02:00
Connor McLaughlin
68877c52d1 Merge pull request #8027 from MerryMage/MOVAPS
Jit64: Prefer MOVAPS where possible
2019-05-22 15:05:17 +10:00
Techjar
ff972e3673 Reformat repo to clang-format 7.0 rules 2019-05-06 18:48:04 +00:00
MerryMage
1baa8ee970 x64Emitter: Prefer MOVAPS to MOVSD
* The high half of regOp is immediately overwritten so the value in it is irrelevant.
* MOVSD produces an unnecessary dependency on the high half of regOp.
* MOVAPS is implemented as a register rename on modern microarchitectures.
2019-04-27 12:56:05 +01:00
MerryMage
2d4dd8cdc1 x64Emitter: Prefer MOVAPS to MOVAPD
There is no reason to use MOVAPD over MOVAPS, for two reasons:
* There has never been a microarchitecture with separate single and double domains.
* MOVAPD is one byte longer than MOVAPS
2019-04-27 12:54:43 +01:00
MerryMage
da7608ff9f x64Emitter: Add some single-precision instructions 2018-12-26 00:23:42 +00:00