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Core: Clean up brace placements

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This commit is contained in:
Lioncash
2014-08-30 18:06:49 -04:00
parent 8553b0f27b
commit eb535be874
46 changed files with 262 additions and 206 deletions
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Source/Core/Core/Boot/ElfReader.h
+2 -1
View File
@@ -69,7 +69,8 @@ public:
int GetSectionSize(SectionID section) const { return sections[section].sh_size; }
SectionID GetSectionByName(const char *name, int firstSection = 0) const; //-1 for not found
bool DidRelocate() {
bool DidRelocate()
{
return bRelocate;
}
};
Source/Core/Core/CoreTiming.cpp
+2 -1
View File
@@ -275,7 +275,8 @@ bool IsScheduled(int event_type)
if (!first)
return false;
Event *e = first;
while (e) {
while (e)
{
if (e->type == event_type)
return true;
e = e->next;
Source/Core/Core/DSP/DSPAssembler.cpp
+31 -8
View File
@@ -539,7 +539,9 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
if ((int)par[i].val < value ||
(int)par[i].val > value + get_mask_shifted_down(opc->params[i].mask))
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
fprintf(stderr, "%s (param %i)", cur_line.c_str(), current_param);
ShowError(ERR_INVALID_REGISTER);
}
@@ -547,7 +549,9 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
case P_PRG:
if ((int)par[i].val < 0 || (int)par[i].val > 0x3)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
fprintf(stderr, "%s (param %i)", cur_line.c_str(), current_param);
ShowError(ERR_INVALID_REGISTER);
}
@@ -555,52 +559,71 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
case P_ACC:
if ((int)par[i].val < 0x20 || (int)par[i].val > 0x21)
{
if (ext) fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f) {
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f)
{
fprintf(stderr, "%i : %s ", code_line, cur_line.c_str());
fprintf(stderr, "WARNING: $ACM%d register used instead of $ACC%d register Line: %d Param: %d Ext: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param, ext);
}
else if (par[i].val >= 0x1c && par[i].val <= 0x1d) {
else if (par[i].val >= 0x1c && par[i].val <= 0x1d)
{
fprintf(stderr, "WARNING: $ACL%d register used instead of $ACC%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
case P_ACCM:
if ((int)par[i].val < 0x1e || (int)par[i].val > 0x1f)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1c && par[i].val <= 0x1d)
{
fprintf(stderr, "WARNING: $ACL%d register used instead of $ACM%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else if (par[i].val >= 0x20 && par[i].val <= 0x21)
{
fprintf(stderr, "WARNING: $ACC%d register used instead of $ACM%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
case P_ACCL:
if ((int)par[i].val < 0x1c || (int)par[i].val > 0x1d)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f)
{
fprintf(stderr, "%s ", cur_line.c_str());
fprintf(stderr, "WARNING: $ACM%d register used instead of $ACL%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else if (par[i].val >= 0x20 && par[i].val <= 0x21) {
else if (par[i].val >= 0x20 && par[i].val <= 0x21)
{
fprintf(stderr, "%s ", cur_line.c_str());
fprintf(stderr, "WARNING: $ACC%d register used instead of $ACL%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
/* case P_ACCM_D: //P_ACC_MID:
Source/Core/Core/DSP/DSPCore.cpp
+3 -1
View File
@@ -185,10 +185,12 @@ void DSPCore_Shutdown()
core_state = DSPCORE_STOP;
if (dspjit) {
if (dspjit)
{
delete dspjit;
dspjit = nullptr;
}
DSPCore_FreeMemoryPages();
g_dsp_cap.reset();
Source/Core/Core/DSP/DSPCore.h
+13 -5
View File
@@ -192,25 +192,33 @@ struct DSP_Regs
u16 st[4];
u16 cr;
u16 sr;
union {
union
{
u64 val;
struct {
struct
{
u16 l;
u16 m;
u16 h;
u16 m2;//if this gets in the way, drop it.
};
} prod;
union {
union
{
u32 val;
struct {
u16 l;
u16 h;
};
} ax[2];
union {
union
{
u64 val;
struct {
struct
{
u16 l;
u16 m;
u16 h;
Source/Core/Core/DSP/DSPIntArithmetic.cpp
+8 -2
View File
@@ -370,7 +370,9 @@ void addr(const UDSPInstruction opc)
s64 acc = dsp_get_long_acc(dreg);
s64 ax = 0;
switch (sreg) {
switch (sreg)
{
case DSP_REG_AXL0:
case DSP_REG_AXL1:
ax = (s16)g_dsp.r.ax[sreg-DSP_REG_AXL0].l;
@@ -383,6 +385,7 @@ void addr(const UDSPInstruction opc)
ax = 0;
break;
}
ax <<= 16;
s64 res = acc + ax;
@@ -569,7 +572,9 @@ void subr(const UDSPInstruction opc)
s64 acc = dsp_get_long_acc(dreg);
s64 ax = 0;
switch (sreg) {
switch (sreg)
{
case DSP_REG_AXL0:
case DSP_REG_AXL1:
ax = (s16)g_dsp.r.ax[sreg-DSP_REG_AXL0].l;
@@ -582,6 +587,7 @@ void subr(const UDSPInstruction opc)
ax = 0;
break;
}
ax <<= 16;
s64 res = acc - ax;
Source/Core/Core/DSP/DSPIntCCUtil.cpp
+14 -7
View File
@@ -111,31 +111,38 @@ inline int GetMultiplyModifier()
return (g_dsp.r.sr & SR_MUL_MODIFY)?1:2;
}
inline bool isCarry() {
inline bool isCarry()
{
return (g_dsp.r.sr & SR_CARRY) ? true : false;
}
inline bool isOverflow() {
inline bool isOverflow()
{
return (g_dsp.r.sr & SR_OVERFLOW) ? true : false;
}
inline bool isOverS32() {
inline bool isOverS32()
{
return (g_dsp.r.sr & SR_OVER_S32) ? true : false;
}
inline bool isLess() {
inline bool isLess()
{
return (!(g_dsp.r.sr & SR_OVERFLOW) != !(g_dsp.r.sr & SR_SIGN));
}
inline bool isZero() {
inline bool isZero()
{
return (g_dsp.r.sr & SR_ARITH_ZERO) ? true : false;
}
inline bool isLogicZero() {
inline bool isLogicZero()
{
return (g_dsp.r.sr & SR_LOGIC_ZERO) ? true : false;
}
inline bool isConditionA() {
inline bool isConditionA()
{
return (((g_dsp.r.sr & SR_OVER_S32) || (g_dsp.r.sr & SR_TOP2BITS)) && !(g_dsp.r.sr & SR_ARITH_ZERO)) ? true : false;
}
Source/Core/Core/DSP/DSPIntCCUtil.h
+12 -7
View File
@@ -10,7 +10,8 @@
#include "Common/Common.h"
namespace DSPInterpreter {
namespace DSPInterpreter
{
bool CheckCondition(u8 _Condition);
@@ -20,19 +21,23 @@ void Update_SR_Register16(s16 _Value, bool carry = false, bool overflow = false,
void Update_SR_Register64(s64 _Value, bool carry = false, bool overflow = false);
void Update_SR_LZ(bool value);
inline bool isCarry(u64 val, u64 result) {
return (val>result);
inline bool isCarry(u64 val, u64 result)
{
return (val > result);
}
inline bool isCarry2(u64 val, u64 result) {
return (val>=result);
inline bool isCarry2(u64 val, u64 result)
{
return (val >= result);
}
inline bool isOverflow(s64 val1, s64 val2, s64 res) {
inline bool isOverflow(s64 val1, s64 val2, s64 res)
{
return ((val1 ^ res) & (val2 ^ res)) < 0;
}
inline bool isOverS32(s64 acc) {
inline bool isOverS32(s64 acc)
{
return (acc != (s32)acc) ? true : false;
}
Source/Core/Core/DSP/Jit/DSPJitArithmetic.cpp
+15 -6
View File
@@ -1358,9 +1358,12 @@ void DSPEmitter::lsrn(const UDSPInstruction opc)
// else
// shift = accm & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc >>= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc <<= -shift;
// }
@@ -1414,9 +1417,12 @@ void DSPEmitter::asrn(const UDSPInstruction opc)
// else
// shift = accm & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc >>= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc <<= -shift;
// }
@@ -1474,9 +1480,12 @@ void DSPEmitter::lsrnrx(const UDSPInstruction opc)
// else
// shift = axh & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc <<= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc >>= -shift;
// }
Source/Core/Core/DSP/Jit/DSPJitCCUtil.cpp
-93
View File
@@ -133,16 +133,6 @@ void DSPEmitter::Update_SR_Register64_Carry2(X64Reg val, X64Reg carry_ovfl)
Update_SR_Register();
}
//void DSPEmitter::Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32)
//{
// // 0x20 - Checks if top bits of m are equal
// if ((((u16)_Value >> 14) == 0) || (((u16)_Value >> 14) == 3))
// {
// g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
// }
//}
// In: RAX: s64 _Value
// Clobbers RDX
void DSPEmitter::Update_SR_Register16(X64Reg val)
@@ -205,86 +195,3 @@ void DSPEmitter::Update_SR_Register16_OverS32(Gen::X64Reg val)
//AND(32, R(val), Imm32(0xc0000000));
Update_SR_Register16(val);
}
//void DSPEmitter::Update_SR_LZ(bool value) {
// if (value == true)
// g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO;
// else
// g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO;
//}
//inline int GetMultiplyModifier()
//{
// return (g_dsp.r[DSP_REG_SR] & SR_MUL_MODIFY)?1:2;
//}
//inline bool isCarry() {
// return (g_dsp.r[DSP_REG_SR] & SR_CARRY) ? true : false;
//}
//inline bool isOverflow() {
// return (g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) ? true : false;
//}
//inline bool isOverS32() {
// return (g_dsp.r[DSP_REG_SR] & SR_OVER_S32) ? true : false;
//}
//inline bool isLess() {
// return (!(g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) != !(g_dsp.r[DSP_REG_SR] & SR_SIGN));
//}
//inline bool isZero() {
// return (g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO) ? true : false;
//}
//inline bool isLogicZero() {
// return (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO) ? true : false;
//}
//inline bool isConditionA() {
// return (((g_dsp.r[DSP_REG_SR] & SR_OVER_S32) || (g_dsp.r[DSP_REG_SR] & SR_TOP2BITS)) && !(g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO)) ? true : false;
//}
//see DSPCore.h for flags
//bool CheckCondition(u8 _Condition)
//{
// switch (_Condition & 0xf)
// {
// case 0xf: // Always true.
// return true;
// case 0x0: // GE - Greater Equal
// return !isLess();
// case 0x1: // L - Less
// return isLess();
// case 0x2: // G - Greater
// return !isLess() && !isZero();
// case 0x3: // LE - Less Equal
// return isLess() || isZero();
// case 0x4: // NZ - Not Zero
// return !isZero();
// case 0x5: // Z - Zero
// return isZero();
// case 0x6: // NC - Not carry
// return !isCarry();
// case 0x7: // C - Carry
// return isCarry();
// case 0x8: // ? - Not over s32
// return !isOverS32();
// case 0x9: // ? - Over s32
// return isOverS32();
// case 0xa: // ?
// return isConditionA();
// case 0xb: // ?
// return !isConditionA();
// case 0xc: // LNZ - Logic Not Zero
// return !isLogicZero();
// case 0xd: // LZ - Logic Zero
// return isLogicZero();
// case 0xe: // 0 - Overflow
// return isOverflow();
// default:
// return true;
// }
//}
Source/Core/Core/DSP/Jit/DSPJitExtOps.cpp
+4 -2
View File
@@ -115,7 +115,8 @@ void DSPEmitter::l(const UDSPInstruction opc)
pushExtValueFromMem(dreg, sreg);
if (dreg >= DSP_REG_ACM0) {
if (dreg >= DSP_REG_ACM0)
{
//save SR too, so we can decide later.
//even if only for one bit, can only
//store (up to) two registers in EBX,
@@ -139,7 +140,8 @@ void DSPEmitter::ln(const UDSPInstruction opc)
pushExtValueFromMem(dreg, sreg);
if (dreg >= DSP_REG_ACM0) {
if (dreg >= DSP_REG_ACM0)
{
//save SR too, so we can decide later.
//even if only for one bit, can only
//store (up to) two registers in EBX,
Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
+4 -2
View File
@@ -263,7 +263,8 @@ void DSPJitRegCache::flushRegs(DSPJitRegCache &cache, bool emit)
}
// sync the freely used xregs
if (!emit) {
if (!emit)
{
for (i = 0; i < NUMXREGS; i++)
{
if (cache.xregs[i].guest_reg == DSP_REG_USED &&
@@ -501,7 +502,8 @@ void DSPJitRegCache::pushRegs()
emitter.MOV(64, R(RBP), M(&ebp_store));
}
void DSPJitRegCache::popRegs() {
void DSPJitRegCache::popRegs()
{
emitter.MOV(64, M(&ebp_store), R(RBP));
int push_count = 0;
for (X64CachedReg& xreg : xregs)
Source/Core/Core/Debugger/Debugger_SymbolMap.cpp
+8 -2
View File
@@ -103,13 +103,16 @@ void PrintCallstack()
{
printf("== STACK TRACE - SP = %08x ==", PowerPC::ppcState.gpr[1]);
if (LR == 0) {
if (LR == 0)
{
printf(" LR = 0 - this is bad");
}
if (g_symbolDB.GetDescription(PC) != g_symbolDB.GetDescription(LR))
{
printf(" * %s [ LR = %08x ]", g_symbolDB.GetDescription(LR).c_str(), LR);
}
WalkTheStack([](u32 func_addr) {
std::string func_desc = g_symbolDB.GetDescription(func_addr);
if (func_desc.empty() || func_desc == "Invalid")
@@ -123,14 +126,17 @@ void PrintCallstack(LogTypes::LOG_TYPE type, LogTypes::LOG_LEVELS level)
GENERIC_LOG(type, level, "== STACK TRACE - SP = %08x ==",
PowerPC::ppcState.gpr[1]);
if (LR == 0) {
if (LR == 0)
{
GENERIC_LOG(type, level, " LR = 0 - this is bad");
}
if (g_symbolDB.GetDescription(PC) != g_symbolDB.GetDescription(LR))
{
GENERIC_LOG(type, level, " * %s [ LR = %08x ]",
g_symbolDB.GetDescription(LR).c_str(), LR);
}
WalkTheStack([type, level](u32 func_addr) {
std::string func_desc = g_symbolDB.GetDescription(func_addr);
if (func_desc.empty() || func_desc == "Invalid")
Source/Core/Core/Debugger/PPCDebugInterface.h
+3 -1
View File
@@ -28,9 +28,11 @@ public:
virtual void ToggleMemCheck(unsigned int address) override;
virtual unsigned int ReadMemory(unsigned int address) override;
enum {
enum
{
EXTRAMEM_ARAM = 1,
};
virtual unsigned int ReadExtraMemory(int memory, unsigned int address) override;
virtual unsigned int ReadInstruction(unsigned int address) override;
virtual unsigned int GetPC() override;
Source/Core/Core/HLE/HLE_OS.cpp
+2 -1
View File
@@ -76,7 +76,8 @@ void GetStringVA(std::string& _rOutBuffer, u32 strReg)
{
char* pArgument = ArgumentBuffer;
*pArgument++ = *pString++;
if (*pString == '%') {
if (*pString == '%')
{
_rOutBuffer += "%";
pString++;
continue;
Source/Core/Core/HW/DSP.cpp
+2 -1
View File
@@ -269,7 +269,8 @@ void Shutdown()
void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
// Declare all the boilerplate direct MMIOs.
struct {
struct
{
u32 addr;
u16* ptr;
bool align_writes_on_32_bytes;
Source/Core/Core/HW/DSPHLE/DSPHLE.cpp
+2 -1
View File
@@ -82,7 +82,8 @@ u32 DSPHLE::DSP_UpdateRate()
void DSPHLE::SendMailToDSP(u32 _uMail)
{
if (m_pUCode != nullptr) {
if (m_pUCode != nullptr)
{
DEBUG_LOG(DSP_MAIL, "CPU writes 0x%08x", _uMail);
m_pUCode->HandleMail(_uMail);
}
Source/Core/Core/HW/DSPHLE/UCodes/AXWii.cpp
+2 -1
View File
@@ -252,7 +252,8 @@ void AXWiiUCode::SetupProcessing(u32 init_addr)
init_data[i] = HLEMemory_Read_U16(init_addr + 2 * i);
// List of all buffers we have to initialize
struct {
struct
{
int* ptr;
u32 samples;
} buffers[] = {
Source/Core/Core/HW/DSPHLE/UCodes/ROM.cpp
+2 -1
View File
@@ -62,7 +62,8 @@ void ROMUCode::HandleMail(u32 mail)
case 0x80F3B002:
m_current_ucode.m_dmem_length = mail & 0xffff;
if (m_current_ucode.m_dmem_length) {
if (m_current_ucode.m_dmem_length)
{
NOTICE_LOG(DSPHLE,"m_current_ucode.m_dmem_length = 0x%04x.", m_current_ucode.m_dmem_length);
}
break;
Source/Core/Core/HW/DSPHLE/UCodes/ZeldaADPCM.cpp
+3 -1
View File
@@ -22,7 +22,9 @@ void ZeldaUCode::AFCdecodebuffer(const s16 *coef, const char *src, signed short
nibbles[i + 1] = *src & 15;
src++;
}
for (auto& nibble : nibbles) {
for (auto& nibble : nibbles)
{
if (nibble >= 8)
nibble = nibble - 16;
nibble <<= 11;

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