Rewrites ARMv7 fastmem entirely.

This is a fairly lengthy change that can't be separated out to multiple commits well due to the nature of fastmem being a bit of an intertangled mess.
This makes my life easier for maintaining fastmem on ARMv7 because I now don't have to do any terrible instruction counting and NOP padding. Really
makes my brain stop hurting when working with it.

This enables fastmem for a whole bunch of new instructions, which basically means that all instructions now have fastmem working for them. This also
rewrites the floating point loadstores again because the last implementation was pretty crap when it comes to performance, even if they were the
cleanest implementation from my point of view.

This initially started with me rewriting the fastmem routines to work just like the previous/current implementation of floating loadstores. That was
when I noticed that the performance tanked and decided to rewrite all of it.

This also happens to implement gatherpipe optimizations alongside constant address optimization.

Overall this comment brings a fairly large speedboost when using fastmem.

Source/Core/Core/PowerPC/JitArm32/Jit.cpp

@@ -40,6 +40,7 @@ void JitArm::Init()
 	code_block.m_gpa = &js.gpa;
 	code_block.m_fpa = &js.fpa;
 	analyzer.SetOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE);
+	InitBackpatch();
 }
 
 void JitArm::ClearCache()

Source/Core/Core/PowerPC/JitArm32/Jit.h

@@ -48,6 +48,26 @@ private:
 	ArmFPRCache fpr;
 
 	PPCAnalyst::CodeBuffer code_buffer;
+	struct BackPatchInfo
+	{
+		enum
+		{
+			FLAG_STORE    = (1 << 0),
+			FLAG_LOAD     = (1 << 1),
+			FLAG_SIZE_8   = (1 << 2),
+			FLAG_SIZE_16  = (1 << 3),
+			FLAG_SIZE_32  = (1 << 4),
+			FLAG_SIZE_F32 = (1 << 5),
+			FLAG_SIZE_F64 = (1 << 6),
+			FLAG_REVERSE  = (1 << 7),
+		};
+
+		u32 m_fastmem_size;
+		u32 m_fastmem_trouble_inst_offset;
+		u32 m_slowmem_size;
+	};
+	// The key is the flags
+	std::map<u32, BackPatchInfo> m_backpatch_info;
 
 	void DoDownCount();
 
@@ -57,11 +77,19 @@ private:
 
 	ArmGen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
 
-	bool BackPatch(SContext* ctx);
-
 	void BeginTimeProfile(JitBlock* b);
 	void EndTimeProfile(JitBlock* b);
 
+	bool BackPatch(SContext* ctx);
+	bool DisasmLoadStore(const u8* ptr, u32* flags, ArmGen::ARMReg* rD, ArmGen::ARMReg* V1);
+	// Initializes the information that backpatching needs
+	// This is required so we know the backpatch routine sizes and trouble offsets
+	void InitBackpatch();
+
+	// Returns the trouble instruction offset
+	// Zero if it isn't a fastmem routine
+	u32 EmitBackpatchRoutine(ARMXEmitter* emit, u32 flags, bool fastmem, bool do_padding, ArmGen::ARMReg RS, ArmGen::ARMReg V1 = ArmGen::ARMReg::INVALID_REG);
+
 public:
 	JitArm() : code_buffer(32000) {}
 	~JitArm() {}
@@ -118,13 +146,8 @@ public:
 	void GetCarryAndClear(ArmGen::ARMReg reg);
 	void FinalizeCarry(ArmGen::ARMReg reg);
 
-	// TODO: This shouldn't be here
-	void UnsafeStoreFromReg(ArmGen::ARMReg dest, ArmGen::ARMReg value, int accessSize, s32 offset);
-	void SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset);
-
-	void UnsafeLoadToReg(ArmGen::ARMReg dest, ArmGen::ARMReg addr, int accessSize, s32 offsetReg, s32 offset);
-	void SafeLoadToReg(bool fastmem, u32 dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse);
-
+	void SafeStoreFromReg(s32 dest, u32 value, s32 offsetReg, int accessSize, s32 offset);
+	void SafeLoadToReg(ArmGen::ARMReg dest, s32 addr, s32 offsetReg, int accessSize, s32 offset, bool signExtend, bool reverse, bool update);
 
 	// OPCODES
 	void unknown_instruction(UGeckoInstruction _inst);