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Merge pull request #6438 from lioncash/assert

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Assert: Uppercase assertion macros
This commit is contained in:
Mat M
2018-03-16 11:59:14 -04:00
committed by GitHub
parent 1259370cdf 50a476c371
commit 9f4d5122a2
135 changed files with 719 additions and 741 deletions
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Source/Core/AudioCommon/OpenSLESStream.cpp
+1 -1
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@@ -46,7 +46,7 @@ static void bqPlayerCallback(SLAndroidSimpleBufferQueueItf bq, void* context)
// Comment from sample code:
// the most likely other result is SL_RESULT_BUFFER_INSUFFICIENT,
// which for this code example would indicate a programming error
_assert_msg_(AUDIO, SL_RESULT_SUCCESS == result, "Couldn't enqueue audio stream.");
ASSERT_MSG(AUDIO, SL_RESULT_SUCCESS == result, "Couldn't enqueue audio stream.");
}
bool OpenSLESStream::Init()
Source/Core/Common/Arm64Emitter.cpp
+152 -160
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File diff suppressed because it is too large Load Diff
Source/Core/Common/Arm64Emitter.h
+2 -2
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@@ -490,7 +490,7 @@ public:
return (m_shifttype << 22) | (m_shift << 10);
break;
default:
_dbg_assert_msg_(DYNA_REC, false, "Invalid type in GetData");
DEBUG_ASSERT_MSG(DYNA_REC, false, "Invalid type in GetData");
break;
}
return 0;
@@ -846,7 +846,7 @@ public:
template <class P>
void MOVP2R(ARM64Reg Rd, P* ptr)
{
_assert_msg_(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
ASSERT_MSG(DYNA_REC, Is64Bit(Rd), "Can't store pointers in 32-bit registers");
MOVI2R(Rd, (uintptr_t)ptr);
}
Source/Core/Common/Assert.h
+10 -10
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@@ -10,14 +10,14 @@
#include "Common/MsgHandler.h"
#ifdef _WIN32
#define _assert_msg_(_t_, _a_, _fmt_, ...) \
#define ASSERT_MSG(_t_, _a_, _fmt_, ...) \
if (!(_a_)) \
{ \
if (!PanicYesNo(_fmt_ "\n\nIgnore and continue?", __VA_ARGS__)) \
Crash(); \
}
#define _dbg_assert_msg_(_t_, _a_, _msg_, ...) \
#define DEBUG_ASSERT_MSG(_t_, _a_, _msg_, ...) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG && !(_a_)) \
{ \
ERROR_LOG(_t_, _msg_, __VA_ARGS__); \
@@ -25,14 +25,14 @@
Crash(); \
}
#else
#define _assert_msg_(_t_, _a_, _fmt_, ...) \
#define ASSERT_MSG(_t_, _a_, _fmt_, ...) \
if (!(_a_)) \
{ \
if (!PanicYesNo(_fmt_, ##__VA_ARGS__)) \
Crash(); \
}
#define _dbg_assert_msg_(_t_, _a_, _msg_, ...) \
#define DEBUG_ASSERT_MSG(_t_, _a_, _msg_, ...) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG && !(_a_)) \
{ \
ERROR_LOG(_t_, _msg_, ##__VA_ARGS__); \
@@ -41,11 +41,11 @@
}
#endif
#define _assert_(_a_) \
_assert_msg_(MASTER_LOG, _a_, \
_trans("An error occurred.\n\n Line: %d\n File: %s\n\nIgnore and continue?"), \
__LINE__, __FILE__)
#define ASSERT(_a_) \
ASSERT_MSG(MASTER_LOG, _a_, \
_trans("An error occurred.\n\n Line: %d\n File: %s\n\nIgnore and continue?"), \
__LINE__, __FILE__)
#define _dbg_assert_(_t_, _a_) \
#define DEBUG_ASSERT(_t_, _a_) \
if (MAX_LOGLEVEL >= LogTypes::LOG_LEVELS::LDEBUG) \
_assert_(_a_)
ASSERT(_a_)
Source/Core/Common/ChunkFile.h
+1 -1
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@@ -285,7 +285,7 @@ private:
break;
case MODE_VERIFY:
_dbg_assert_msg_(COMMON, !memcmp(data, *ptr, size),
DEBUG_ASSERT_MSG(COMMON, !memcmp(data, *ptr, size),
"Savestate verification failure: buf %p != %p (size %u).\n", data, *ptr,
size);
break;
Source/Core/Common/CodeBlock.h
+3 -3
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@@ -67,7 +67,7 @@ public:
// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
void FreeCodeSpace()
{
_assert_(!m_is_child);
ASSERT(!m_is_child);
Common::FreeMemoryPages(region, total_region_size);
region = nullptr;
region_size = 0;
@@ -87,7 +87,7 @@ public:
void ResetCodePtr() { T::SetCodePtr(region); }
size_t GetSpaceLeft() const
{
_assert_(static_cast<size_t>(T::GetCodePtr() - region) < region_size);
ASSERT(static_cast<size_t>(T::GetCodePtr() - region) < region_size);
return region_size - (T::GetCodePtr() - region);
}
@@ -100,7 +100,7 @@ public:
bool HasChildren() const { return region_size != total_region_size; }
u8* AllocChildCodeSpace(size_t child_size)
{
_assert_msg_(DYNA_REG, child_size < GetSpaceLeft(), "Insufficient space for child allocation.");
ASSERT_MSG(DYNA_REG, child_size < GetSpaceLeft(), "Insufficient space for child allocation.");
u8* child_region = region + region_size - child_size;
region_size -= child_size;
return child_region;
Source/Core/Common/FileUtil.cpp
+1 -1
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@@ -715,7 +715,7 @@ std::string GetSysDirectory()
sysDir = GetExeDirectory() + DIR_SEP + SYSDATA_DIR;
#elif defined ANDROID
sysDir = s_android_sys_directory;
_assert_msg_(COMMON, !sysDir.empty(), "Sys directory has not been set");
ASSERT_MSG(COMMON, !sysDir.empty(), "Sys directory has not been set");
#else
sysDir = SYSDATA_DIR;
#endif
Source/Core/Common/SysConf.cpp
+1 -1
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@@ -31,7 +31,7 @@ static size_t GetNonArrayEntrySize(SysConf::Entry::Type type)
case SysConf::Entry::Type::LongLong:
return 8;
default:
_assert_(false);
ASSERT(false);
return 0;
}
}
Source/Core/Common/SysConf.h
+1 -1
View File
@@ -55,7 +55,7 @@ public:
template <typename T>
void SetData(T value)
{
_assert_(sizeof(value) == bytes.size());
ASSERT(sizeof(value) == bytes.size());
std::memcpy(bytes.data(), &value, bytes.size());
}
Source/Core/Common/x64Emitter.cpp
+70 -70
View File
@@ -122,8 +122,8 @@ void XEmitter::ReserveCodeSpace(int bytes)
const u8* XEmitter::AlignCodeTo(size_t alignment)
{
_assert_msg_(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
ASSERT_MSG(DYNA_REC, alignment != 0 && (alignment & (alignment - 1)) == 0,
"Alignment must be power of two");
u64 c = reinterpret_cast<u64>(code) & (alignment - 1);
if (c)
ReserveCodeSpace(static_cast<int>(alignment - c));
@@ -150,7 +150,7 @@ const u8* XEmitter::AlignCodePage()
// causing a subtle JIT bug.
void XEmitter::CheckFlags()
{
_assert_msg_(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
ASSERT_MSG(DYNA_REC, !flags_locked, "Attempt to modify flags while flags locked!");
}
void XEmitter::WriteModRM(int mod, int reg, int rm)
@@ -187,8 +187,8 @@ void OpArg::WriteREX(XEmitter* emit, int opBits, int bits, int customOp) const
{
emit->Write8(op);
// Check the operation doesn't access AH, BH, CH, or DH.
_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
DEBUG_ASSERT(DYNA_REC, (customOp & 0x100) == 0);
}
}
@@ -236,9 +236,9 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
// TODO : add some checks
u64 ripAddr = (u64)emit->GetCodePtr() + 4 + extraBytes;
s64 distance = (s64)offset - (s64)ripAddr;
_assert_msg_(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
ASSERT_MSG(DYNA_REC,
(distance < 0x80000000LL && distance >= -0x80000000LL) || !warn_64bit_offset,
"WriteRest: op out of range (0x%" PRIx64 " uses 0x%" PRIx64 ")", ripAddr, offset);
s32 offs = (s32)distance;
emit->Write32((u32)offs);
return;
@@ -351,7 +351,7 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
ss = 0;
break;
default:
_assert_msg_(DYNA_REC, 0, "Invalid scale for SIB byte");
ASSERT_MSG(DYNA_REC, 0, "Invalid scale for SIB byte");
ss = 0;
break;
}
@@ -389,8 +389,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
if (!force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 2));
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
// 8 bits will do
Write8(0xEB);
Write8((u8)(s8)distance);
@@ -399,8 +399,8 @@ void XEmitter::JMP(const u8* addr, bool force5Bytes)
{
s64 distance = (s64)(fn - ((u64)code + 5));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0xE9);
Write32((u32)(s32)distance);
}
@@ -410,7 +410,7 @@ void XEmitter::JMPptr(const OpArg& arg2)
{
OpArg arg = arg2;
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "JMPptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "JMPptr - Imm argument");
arg.operandReg = 4;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@@ -428,7 +428,7 @@ void XEmitter::JMPself()
void XEmitter::CALLptr(OpArg arg)
{
if (arg.IsImm())
_assert_msg_(DYNA_REC, 0, "CALLptr - Imm argument");
ASSERT_MSG(DYNA_REC, 0, "CALLptr - Imm argument");
arg.operandReg = 2;
arg.WriteREX(this, 0, 0);
Write8(0xFF);
@@ -438,8 +438,8 @@ void XEmitter::CALLptr(OpArg arg)
void XEmitter::CALL(const void* fnptr)
{
u64 distance = u64(fnptr) - (u64(code) + 5);
_assert_msg_(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
ASSERT_MSG(DYNA_REC, distance < 0x0000000080000000ULL || distance >= 0xFFFFFFFF80000000ULL,
"CALL out of range (%p calls %p)", code, fnptr);
Write8(0xE8);
Write32(u32(distance));
}
@@ -500,8 +500,8 @@ void XEmitter::J_CC(CCFlags conditionCode, const u8* addr)
if (distance < -0x80 || distance >= 0x80)
{
distance = (s64)(fn - ((u64)code + 6));
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
Write8(0x0F);
Write8(0x80 + conditionCode);
Write32((u32)(s32)distance);
@@ -518,15 +518,15 @@ void XEmitter::SetJumpTarget(const FixupBranch& branch)
if (branch.type == 0)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
ASSERT_MSG(DYNA_REC, distance >= -0x80 && distance < 0x80,
"Jump target too far away, needs force5Bytes = true");
branch.ptr[-1] = (u8)(s8)distance;
}
else if (branch.type == 1)
{
s64 distance = (s64)(code - branch.ptr);
_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
ASSERT_MSG(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL,
"Jump target too far away, needs indirect register");
s32 valid_distance = static_cast<s32>(distance);
std::memcpy(&branch.ptr[-4], &valid_distance, sizeof(s32));
@@ -553,7 +553,7 @@ void XEmitter::RET_FAST()
// The first sign of decadence: optimized NOPs.
void XEmitter::NOP(size_t size)
{
_dbg_assert_(DYNA_REC, (int)size > 0);
DEBUG_ASSERT(DYNA_REC, (int)size > 0);
while (true)
{
switch (size)
@@ -792,7 +792,7 @@ void XEmitter::PUSH(int bits, const OpArg& reg)
Write32((u32)reg.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "PUSH - Bad imm bits");
ASSERT_MSG(DYNA_REC, 0, "PUSH - Bad imm bits");
break;
}
}
@@ -811,7 +811,7 @@ void XEmitter::POP(int /*bits*/, const OpArg& reg)
if (reg.IsSimpleReg())
POP(reg.GetSimpleReg());
else
_assert_msg_(DYNA_REC, 0, "POP - Unsupported encoding");
ASSERT_MSG(DYNA_REC, 0, "POP - Unsupported encoding");
}
void XEmitter::BSWAP(int bits, X64Reg reg)
@@ -830,7 +830,7 @@ void XEmitter::BSWAP(int bits, X64Reg reg)
}
else
{
_assert_msg_(DYNA_REC, 0, "BSWAP - Wrong number of bits");
ASSERT_MSG(DYNA_REC, 0, "BSWAP - Wrong number of bits");
}
}
@@ -844,7 +844,7 @@ void XEmitter::UD2()
void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
{
_assert_msg_(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
ASSERT_MSG(DYNA_REC, !arg.IsImm(), "PREFETCH - Imm argument");
arg.operandReg = (u8)level;
arg.WriteREX(this, 0, 0);
Write8(0x0F);
@@ -854,7 +854,7 @@ void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
void XEmitter::SETcc(CCFlags flag, OpArg dest)
{
_assert_msg_(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
ASSERT_MSG(DYNA_REC, !dest.IsImm(), "SETcc - Imm argument");
dest.operandReg = 0;
dest.WriteREX(this, 0, 8);
Write8(0x0F);
@@ -864,8 +864,8 @@ void XEmitter::SETcc(CCFlags flag, OpArg dest)
void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
_assert_msg_(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "CMOVcc - Imm argument");
ASSERT_MSG(DYNA_REC, bits != 8, "CMOVcc - 8 bits unsupported");
if (bits == 16)
Write8(0x66);
src.operandReg = dest;
@@ -877,7 +877,7 @@ void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
void XEmitter::WriteMulDivType(int bits, OpArg src, int ext)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteMulDivType - Imm argument");
CheckFlags();
src.operandReg = ext;
if (bits == 16)
@@ -921,7 +921,7 @@ void XEmitter::NOT(int bits, const OpArg& src)
void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "WriteBitSearchType - Imm argument");
CheckFlags();
src.operandReg = (u8)dest;
if (bits == 16)
@@ -937,7 +937,7 @@ void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bo
void XEmitter::MOVNTI(int bits, const OpArg& dest, X64Reg src)
{
if (bits <= 16)
_assert_msg_(DYNA_REC, 0, "MOVNTI - bits<=16");
ASSERT_MSG(DYNA_REC, 0, "MOVNTI - bits<=16");
WriteBitSearchType(bits, src, dest, 0xC3);
}
@@ -967,7 +967,7 @@ void XEmitter::LZCNT(int bits, X64Reg dest, const OpArg& src)
void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVSX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@@ -1000,7 +1000,7 @@ void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "MOVZX - Imm argument");
if (dbits == sbits)
{
MOV(dbits, R(dest), src);
@@ -1027,14 +1027,14 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
}
else
{
_assert_msg_(DYNA_REC, 0, "MOVZX - Invalid size");
ASSERT_MSG(DYNA_REC, 0, "MOVZX - Invalid size");
}
src.WriteRest(this);
}
void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
{
_assert_msg_(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
ASSERT_MSG(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
if (bits == 8)
{
MOV(8, op & 1 ? arg : R(reg), op & 1 ? R(reg) : arg);
@@ -1042,7 +1042,7 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, const OpArg& arg)
}
if (bits == 16)
Write8(0x66);
_assert_msg_(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
ASSERT_MSG(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
arg.WriteREX(this, bits, bits, reg);
Write8(0x0F);
Write8(0x38);
@@ -1127,7 +1127,7 @@ void XEmitter::SwapAndStore(int size, const OpArg& dst, X64Reg src, MovInfo* inf
void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
ASSERT_MSG(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
src.operandReg = (u8)dest;
if (bits == 16)
Write8(0x66); // TODO: performance warning
@@ -1143,12 +1143,12 @@ void XEmitter::WriteShift(int bits, OpArg dest, const OpArg& shift, int ext)
bool writeImm = false;
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteShift - can't shift imms");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - can't shift imms");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteShift - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteShift - illegal argument");
}
dest.operandReg = ext;
if (bits == 16)
@@ -1214,11 +1214,11 @@ void XEmitter::WriteBitTest(int bits, const OpArg& dest, const OpArg& index, int
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - can't test imms");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - can't test imms");
}
if ((index.IsImm() && index.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "WriteBitTest - illegal argument");
ASSERT_MSG(DYNA_REC, 0, "WriteBitTest - illegal argument");
}
if (bits == 16)
Write8(0x66);
@@ -1263,16 +1263,16 @@ void XEmitter::SHRD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHRD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHRD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHRD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHRD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHRD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHRD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@@ -1298,16 +1298,16 @@ void XEmitter::SHLD(int bits, const OpArg& dest, const OpArg& src, const OpArg&
CheckFlags();
if (dest.IsImm())
{
_assert_msg_(DYNA_REC, 0, "SHLD - can't use imms as destination");
ASSERT_MSG(DYNA_REC, 0, "SHLD - can't use imms as destination");
}
if (!src.IsSimpleReg())
{
_assert_msg_(DYNA_REC, 0, "SHLD - must use simple register as source");
ASSERT_MSG(DYNA_REC, 0, "SHLD - must use simple register as source");
}
if ((shift.IsSimpleReg() && shift.GetSimpleReg() != ECX) ||
(shift.IsImm() && shift.GetImmBits() != 8))
{
_assert_msg_(DYNA_REC, 0, "SHLD - illegal shift");
ASSERT_MSG(DYNA_REC, 0, "SHLD - illegal shift");
}
if (bits == 16)
Write8(0x66);
@@ -1346,7 +1346,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
X64Reg _operandReg;
if (IsImm())
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Imm argument, wrong order");
}
if (bits == 16)
@@ -1360,7 +1360,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
if (!toRM)
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Writing to Imm (!toRM)");
}
if (operand.scale == SCALE_IMM8 && bits == 8)
@@ -1436,8 +1436,8 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
{
if (scale)
{
_assert_msg_(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requres register destination");
ASSERT_MSG(DYNA_REC, 0,
"WriteNormalOp - MOV with 64-bit imm requires register destination");
}
// mov reg64, imm64
else if (op == nrmMOV)
@@ -1446,11 +1446,11 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write64((u64)operand.offset);
return;
}
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Only MOV can take 64-bit imm");
}
else
{
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case %d %d", operand.scale, bits);
}
_operandReg = (X64Reg)normalops[op].ext; // pass extension in REG of ModRM
}
@@ -1484,7 +1484,7 @@ void OpArg::WriteNormalOp(XEmitter* emit, bool toRM, NormalOp op, const OpArg& o
emit->Write32((u32)operand.offset);
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - Unhandled case");
}
}
@@ -1493,7 +1493,7 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
if (a1.IsImm())
{
// Booh! Can't write to an imm
_assert_msg_(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
ASSERT_MSG(DYNA_REC, 0, "WriteNormalOp - a1 cannot be imm");
return;
}
if (a2.IsImm())
@@ -1508,8 +1508,8 @@ void XEmitter::WriteNormalOp(int bits, NormalOp op, const OpArg& a1, const OpArg
}
else
{
_assert_msg_(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
ASSERT_MSG(DYNA_REC, a2.IsSimpleReg() || a2.IsImm(),
"WriteNormalOp - a1 and a2 cannot both be memory");
a1.WriteNormalOp(this, true, op, a2, bits);
}
}
@@ -1587,7 +1587,7 @@ void XEmitter::CMP_or_TEST(int bits, const OpArg& a1, const OpArg& a2)
void XEmitter::MOV_sum(int bits, X64Reg dest, const OpArg& a1, const OpArg& a2)
{
// This stomps on flags, so ensure they aren't locked
_dbg_assert_(DYNA_REC, !flags_locked);
DEBUG_ASSERT(DYNA_REC, !flags_locked);
// Zero shortcuts (note that this can generate no code in the case where a1 == dest && a2 == zero
// or a2 == dest && a1 == zero)
@@ -1659,19 +1659,19 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
if (a1.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
return;
}
if (!a2.IsImm())
{
_assert_msg_(DYNA_REC, 0, "IMUL - third arg must be imm!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - third arg must be imm!");
return;
}
@@ -1701,7 +1701,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
}
else
{
_assert_msg_(DYNA_REC, 0, "IMUL - unhandled case!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - unhandled case!");
}
}
}
@@ -1711,7 +1711,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a)
CheckFlags();
if (bits == 8)
{
_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
ASSERT_MSG(DYNA_REC, 0, "IMUL - illegal bit size!");
return;
}
@@ -1890,7 +1890,7 @@ void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src)
void XEmitter::WriteMXCSR(OpArg arg, int ext)
{
if (arg.IsImm() || arg.IsSimpleReg())
_assert_msg_(DYNA_REC, 0, "MXCSR - invalid operand");
ASSERT_MSG(DYNA_REC, 0, "MXCSR - invalid operand");
arg.operandReg = ext;
arg.WriteREX(this, 0, 0);
@@ -3248,8 +3248,8 @@ void XEmitter::FWAIT()
void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const OpArg& arg)
{
int mf = 0;
_assert_msg_(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
ASSERT_MSG(DYNA_REC, !(bits == 80 && op_80b == floatINVALID),
"WriteFloatLoadStore: 80 bits not supported for this instruction");
switch (bits)
{
case 32:
@@ -3262,7 +3262,7 @@ void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const O
mf = 2;
break;
default:
_assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
ASSERT_MSG(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
}
Write8(0xd9 | mf);
// x87 instructions use the reg field of the ModR/M byte as opcode:
Source/Core/Common/x64Emitter.h
+14 -14
View File
@@ -156,64 +156,64 @@ struct OpArg
u64 Imm64() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM64);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM64);
return (u64)offset;
}
u32 Imm32() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM32);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM32);
return (u32)offset;
}
u16 Imm16() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM16);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM16);
return (u16)offset;
}
u8 Imm8() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM8);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM8);
return (u8)offset;
}
s64 SImm64() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM64);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM64);
return (s64)offset;
}
s32 SImm32() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM32);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM32);
return (s32)offset;
}
s16 SImm16() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM16);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM16);
return (s16)offset;
}
s8 SImm8() const
{
_dbg_assert_(DYNA_REC, scale == SCALE_IMM8);
DEBUG_ASSERT(DYNA_REC, scale == SCALE_IMM8);
return (s8)offset;
}
OpArg AsImm64() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u64)offset, SCALE_IMM64);
}
OpArg AsImm32() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u32)offset, SCALE_IMM32);
}
OpArg AsImm16() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u16)offset, SCALE_IMM16);
}
OpArg AsImm8() const
{
_dbg_assert_(DYNA_REC, IsImm());
DEBUG_ASSERT(DYNA_REC, IsImm());
return OpArg((u8)offset, SCALE_IMM8);
}
@@ -253,7 +253,7 @@ struct OpArg
void AddMemOffset(int val)
{
_dbg_assert_msg_(DYNA_REC, scale == SCALE_RIP || (scale <= SCALE_ATREG && scale > SCALE_NONE),
DEBUG_ASSERT_MSG(DYNA_REC, scale == SCALE_RIP || (scale <= SCALE_ATREG && scale > SCALE_NONE),
"Tried to increment an OpArg which doesn't have an offset");
offset += val;
}
@@ -329,7 +329,7 @@ inline u32 PtrOffset(const void* ptr, const void* base = nullptr)
s64 distance = (s64)ptr - (s64)base;
if (distance >= 0x80000000LL || distance < -0x80000000LL)
{
_assert_msg_(DYNA_REC, 0, "pointer offset out of range");
ASSERT_MSG(DYNA_REC, 0, "pointer offset out of range");
return 0;
}
Source/Core/Core/ConfigManager.cpp
+1 -1
View File
@@ -843,7 +843,7 @@ const char* SConfig::GetDirectoryForRegion(DiscIO::Region region)
return EUR_DIR;
case DiscIO::Region::NTSC_K:
_assert_msg_(BOOT, false, "NTSC-K is not a valid GameCube region");
ASSERT_MSG(BOOT, false, "NTSC-K is not a valid GameCube region");
return nullptr;
default:
Source/Core/Core/CoreTiming.cpp
+9 -9
View File
@@ -104,10 +104,10 @@ EventType* RegisterEvent(const std::string& name, TimedCallback callback)
{
// check for existing type with same name.
// we want event type names to remain unique so that we can use them for serialization.
_assert_msg_(POWERPC, s_event_types.find(name) == s_event_types.end(),
"CoreTiming Event \"%s\" is already registered. Events should only be registered "
"during Init to avoid breaking save states.",
name.c_str());
ASSERT_MSG(POWERPC, s_event_types.find(name) == s_event_types.end(),
"CoreTiming Event \"%s\" is already registered. Events should only be registered "
"during Init to avoid breaking save states.",
name.c_str());
auto info = s_event_types.emplace(name, EventType{callback, nullptr});
EventType* event_type = &info.first->second;
@@ -117,7 +117,7 @@ EventType* RegisterEvent(const std::string& name, TimedCallback callback)
void UnregisterAllEvents()
{
_assert_msg_(POWERPC, s_event_queue.empty(), "Cannot unregister events with events pending");
ASSERT_MSG(POWERPC, s_event_queue.empty(), "Cannot unregister events with events pending");
s_event_types.clear();
}
@@ -230,7 +230,7 @@ void ClearPendingEvents()
void ScheduleEvent(s64 cycles_into_future, EventType* event_type, u64 userdata, FromThread from)
{
_assert_msg_(POWERPC, event_type, "Event type is nullptr, will crash now.");
ASSERT_MSG(POWERPC, event_type, "Event type is nullptr, will crash now.");
bool from_cpu_thread;
if (from == FromThread::ANY)
@@ -240,9 +240,9 @@ void ScheduleEvent(s64 cycles_into_future, EventType* event_type, u64 userdata,
else
{
from_cpu_thread = from == FromThread::CPU;
_assert_msg_(POWERPC, from_cpu_thread == Core::IsCPUThread(),
"A \"%s\" event was scheduled from the wrong thread (%s)",
event_type->name->c_str(), from_cpu_thread ? "CPU" : "non-CPU");
ASSERT_MSG(POWERPC, from_cpu_thread == Core::IsCPUThread(),
"A \"%s\" event was scheduled from the wrong thread (%s)", event_type->name->c_str(),
from_cpu_thread ? "CPU" : "non-CPU");
}
if (from_cpu_thread)
Source/Core/Core/DSP/DSPCore.cpp
+1 -1
View File
@@ -373,7 +373,7 @@ u16 DSPCore_ReadRegister(size_t reg)
case DSP_REG_ACM1:
return g_dsp.r.ac[reg - DSP_REG_ACM0].m;
default:
_assert_msg_(DSP_CORE, 0, "cannot happen");
ASSERT_MSG(DSP_CORE, 0, "cannot happen");
return 0;
}
}
Source/Core/Core/DSP/Interpreter/DSPIntUtil.h
+1 -1
View File
@@ -161,7 +161,7 @@ static inline u16 dsp_op_read_reg(int _reg)
case DSP_REG_ACM1:
return g_dsp.r.ac[reg - DSP_REG_ACM0].m;
default:
_assert_msg_(DSP_INT, 0, "cannot happen");
ASSERT_MSG(DSP_INT, 0, "cannot happen");
return 0;
}
}
Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp
+1 -1
View File
@@ -140,7 +140,7 @@ void DSPEmitter::FallBackToInterpreter(UDSPInstruction inst)
// Fall back to interpreter
m_gpr.PushRegs();
_assert_msg_(DSPLLE, op_template->intFunc, "No function for %04x", inst);
ASSERT_MSG(DSPLLE, op_template->intFunc, "No function for %04x", inst);
ABI_CallFunctionC16(op_template->intFunc, inst);
m_gpr.PopRegs();
}
Source/Core/Core/DSP/Jit/x64/DSPJitCCUtil.cpp
+1 -1
View File
@@ -15,7 +15,7 @@ namespace DSP::JIT::x64
// Clobbers scratch
void DSPEmitter::Update_SR_Register(Gen::X64Reg val, Gen::X64Reg scratch)
{
_assert_(val != scratch);
ASSERT(val != scratch);
const OpArg sr_reg = m_gpr.GetReg(DSP_REG_SR);
// // 0x04
Source/Core/Core/DSP/Jit/x64/DSPJitRegCache.cpp
+71 -71
View File
@@ -83,7 +83,7 @@ static Gen::OpArg GetRegisterPointer(size_t reg)
case DSP_REG_PROD_64:
return MDisp(R15, static_cast<int>(offsetof(SDSP, r.prod.val)));
default:
_assert_msg_(DSPLLE, 0, "cannot happen");
ASSERT_MSG(DSPLLE, 0, "cannot happen");
return M(static_cast<void*>(nullptr));
}
}
@@ -191,8 +191,8 @@ DSPJitRegCache::DSPJitRegCache(const DSPJitRegCache& cache)
DSPJitRegCache& DSPJitRegCache::operator=(const DSPJitRegCache& cache)
{
_assert_msg_(DSPLLE, &m_emitter == &cache.m_emitter, "emitter does not match");
_assert_msg_(DSPLLE, m_is_temporary, "register cache not temporary??");
ASSERT_MSG(DSPLLE, &m_emitter == &cache.m_emitter, "emitter does not match");
ASSERT_MSG(DSPLLE, m_is_temporary, "register cache not temporary??");
m_is_merged = false;
m_xregs = cache.m_xregs;
@@ -203,7 +203,7 @@ DSPJitRegCache& DSPJitRegCache::operator=(const DSPJitRegCache& cache)
DSPJitRegCache::~DSPJitRegCache()
{
_assert_msg_(DSPLLE, !m_is_temporary || m_is_merged, "temporary cache not merged");
ASSERT_MSG(DSPLLE, !m_is_temporary || m_is_merged, "temporary cache not merged");
}
void DSPJitRegCache::Drop()
@@ -292,22 +292,22 @@ void DSPJitRegCache::FlushRegs(DSPJitRegCache& cache, bool emit)
// consistency checks
for (size_t i = 0; i < m_xregs.size(); i++)
{
_assert_msg_(DSPLLE, m_xregs[i].guest_reg == cache.m_xregs[i].guest_reg,
"cache and current xreg guest_reg mismatch for %u", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_xregs[i].guest_reg == cache.m_xregs[i].guest_reg,
"cache and current xreg guest_reg mismatch for %u", static_cast<u32>(i));
}
for (size_t i = 0; i < m_regs.size(); i++)
{
_assert_msg_(DSPLLE, m_regs[i].loc.IsImm() == cache.m_regs[i].loc.IsImm(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i));
_assert_msg_(DSPLLE, m_regs[i].loc.GetSimpleReg() == cache.m_regs[i].loc.GetSimpleReg(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i));
_assert_msg_(DSPLLE, m_regs[i].dirty || !cache.m_regs[i].dirty,
"cache and current reg dirty mismatch for %i", static_cast<u32>(i));
_assert_msg_(DSPLLE, m_regs[i].used == cache.m_regs[i].used,
"cache and current reg used mismatch for %i", static_cast<u32>(i));
_assert_msg_(DSPLLE, m_regs[i].shift == cache.m_regs[i].shift,
"cache and current reg shift mismatch for %i", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_regs[i].loc.IsImm() == cache.m_regs[i].loc.IsImm(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_regs[i].loc.GetSimpleReg() == cache.m_regs[i].loc.GetSimpleReg(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_regs[i].dirty || !cache.m_regs[i].dirty,
"cache and current reg dirty mismatch for %i", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_regs[i].used == cache.m_regs[i].used,
"cache and current reg used mismatch for %i", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, m_regs[i].shift == cache.m_regs[i].shift,
"cache and current reg shift mismatch for %i", static_cast<u32>(i));
}
m_use_ctr = cache.m_use_ctr;
@@ -321,7 +321,7 @@ void DSPJitRegCache::FlushMemBackedRegs()
for (size_t i = 0; i < m_regs.size(); i++)
{
_assert_msg_(DSPLLE, !m_regs[i].used, "register %u still in use", static_cast<u32>(i));
ASSERT_MSG(DSPLLE, !m_regs[i].used, "register %u still in use", static_cast<u32>(i));
if (m_regs[i].used)
{
@@ -351,27 +351,27 @@ void DSPJitRegCache::FlushRegs()
MovToMemory(i);
}
_assert_msg_(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
ASSERT_MSG(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
}
_assert_msg_(DSPLLE, m_xregs[RSP].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", RSP);
_assert_msg_(DSPLLE, m_xregs[RBX].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", RBX);
_assert_msg_(DSPLLE, m_xregs[RBP].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RBP);
_assert_msg_(DSPLLE, m_xregs[RSI].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RSI);
_assert_msg_(DSPLLE, m_xregs[RDI].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RDI);
ASSERT_MSG(DSPLLE, m_xregs[RSP].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", RSP);
ASSERT_MSG(DSPLLE, m_xregs[RBX].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", RBX);
ASSERT_MSG(DSPLLE, m_xregs[RBP].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RBP);
ASSERT_MSG(DSPLLE, m_xregs[RSI].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RSI);
ASSERT_MSG(DSPLLE, m_xregs[RDI].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", RDI);
#ifdef STATIC_REG_ACCS
_assert_msg_(DSPLLE, m_xregs[R8].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R8);
_assert_msg_(DSPLLE, m_xregs[R9].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R9);
ASSERT_MSG(DSPLLE, m_xregs[R8].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R8);
ASSERT_MSG(DSPLLE, m_xregs[R9].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R9);
#else
_assert_msg_(DSPLLE, m_xregs[R8].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R8);
_assert_msg_(DSPLLE, m_xregs[R9].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R9);
ASSERT_MSG(DSPLLE, m_xregs[R8].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R8);
ASSERT_MSG(DSPLLE, m_xregs[R9].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R9);
#endif
_assert_msg_(DSPLLE, m_xregs[R10].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R10);
_assert_msg_(DSPLLE, m_xregs[R11].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R11);
_assert_msg_(DSPLLE, m_xregs[R12].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R12);
_assert_msg_(DSPLLE, m_xregs[R13].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R13);
_assert_msg_(DSPLLE, m_xregs[R14].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R14);
_assert_msg_(DSPLLE, m_xregs[R15].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R15);
ASSERT_MSG(DSPLLE, m_xregs[R10].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R10);
ASSERT_MSG(DSPLLE, m_xregs[R11].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R11);
ASSERT_MSG(DSPLLE, m_xregs[R12].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R12);
ASSERT_MSG(DSPLLE, m_xregs[R13].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R13);
ASSERT_MSG(DSPLLE, m_xregs[R14].guest_reg == DSP_REG_NONE, "wrong xreg state for %d", R14);
ASSERT_MSG(DSPLLE, m_xregs[R15].guest_reg == DSP_REG_STATIC, "wrong xreg state for %d", R15);
m_use_ctr = 0;
}
@@ -398,7 +398,7 @@ void DSPJitRegCache::SaveRegs()
MovToMemory(i);
}
_assert_msg_(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
ASSERT_MSG(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
}
}
@@ -413,7 +413,7 @@ void DSPJitRegCache::PushRegs()
MovToMemory(i);
}
_assert_msg_(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
ASSERT_MSG(DSPLLE, !m_regs[i].loc.IsSimpleReg(), "register %zu is still a simple reg", i);
}
int push_count = 0;
@@ -438,9 +438,9 @@ void DSPJitRegCache::PushRegs()
m_xregs[i].guest_reg = DSP_REG_NONE;
}
_assert_msg_(DSPLLE,
m_xregs[i].guest_reg == DSP_REG_NONE || m_xregs[i].guest_reg == DSP_REG_STATIC,
"register %zu is still used", i);
ASSERT_MSG(DSPLLE,
m_xregs[i].guest_reg == DSP_REG_NONE || m_xregs[i].guest_reg == DSP_REG_STATIC,
"register %zu is still used", i);
}
}
@@ -481,10 +481,10 @@ X64Reg DSPJitRegCache::MakeABICallSafe(X64Reg reg)
void DSPJitRegCache::MovToHostReg(size_t reg, X64Reg host_reg, bool load)
{
_assert_msg_(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
_assert_msg_(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
_assert_msg_(DSPLLE, !m_regs[reg].used, "moving to host reg in use guest reg %zu", reg);
ASSERT_MSG(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
ASSERT_MSG(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
ASSERT_MSG(DSPLLE, !m_regs[reg].used, "moving to host reg in use guest reg %zu", reg);
X64Reg old_reg = m_regs[reg].loc.GetSimpleReg();
if (old_reg == host_reg)
{
@@ -510,7 +510,7 @@ void DSPJitRegCache::MovToHostReg(size_t reg, X64Reg host_reg, bool load)
m_emitter.MOV(64, R(host_reg), m_regs[reg].loc);
break;
default:
_assert_msg_(DSPLLE, 0, "unsupported memory size");
ASSERT_MSG(DSPLLE, 0, "unsupported memory size");
break;
}
}
@@ -524,10 +524,10 @@ void DSPJitRegCache::MovToHostReg(size_t reg, X64Reg host_reg, bool load)
void DSPJitRegCache::MovToHostReg(size_t reg, bool load)
{
_assert_msg_(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
_assert_msg_(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
_assert_msg_(DSPLLE, !m_regs[reg].used, "moving to host reg in use guest reg %zu", reg);
ASSERT_MSG(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
ASSERT_MSG(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
ASSERT_MSG(DSPLLE, !m_regs[reg].used, "moving to host reg in use guest reg %zu", reg);
if (m_regs[reg].loc.IsSimpleReg())
{
@@ -554,11 +554,11 @@ void DSPJitRegCache::MovToHostReg(size_t reg, bool load)
void DSPJitRegCache::RotateHostReg(size_t reg, int shift, bool emit)
{
_assert_msg_(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
_assert_msg_(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
_assert_msg_(DSPLLE, m_regs[reg].loc.IsSimpleReg(), "register %zu is not a simple reg", reg);
_assert_msg_(DSPLLE, !m_regs[reg].used, "rotating in use guest reg %zu", reg);
ASSERT_MSG(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
ASSERT_MSG(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
ASSERT_MSG(DSPLLE, m_regs[reg].loc.IsSimpleReg(), "register %zu is not a simple reg", reg);
ASSERT_MSG(DSPLLE, !m_regs[reg].used, "rotating in use guest reg %zu", reg);
if (shift > m_regs[reg].shift && emit)
{
@@ -595,10 +595,10 @@ void DSPJitRegCache::RotateHostReg(size_t reg, int shift, bool emit)
void DSPJitRegCache::MovToMemory(size_t reg)
{
_assert_msg_(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
_assert_msg_(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
_assert_msg_(DSPLLE, !m_regs[reg].used, "moving to memory in use guest reg %zu", reg);
ASSERT_MSG(DSPLLE, reg < m_regs.size(), "bad register name %zu", reg);
ASSERT_MSG(DSPLLE, m_regs[reg].parentReg == DSP_REG_NONE, "register %zu is proxy for %d", reg,
m_regs[reg].parentReg);
ASSERT_MSG(DSPLLE, !m_regs[reg].used, "moving to memory in use guest reg %zu", reg);
if (m_regs[reg].used)
{
@@ -620,7 +620,7 @@ void DSPJitRegCache::MovToMemory(size_t reg)
// TODO: Immediates?
}
_assert_msg_(DSPLLE, m_regs[reg].shift == 0, "still shifted??");
ASSERT_MSG(DSPLLE, m_regs[reg].shift == 0, "still shifted??");
// move to mem
OpArg tmp = m_regs[reg].mem;
@@ -639,7 +639,7 @@ void DSPJitRegCache::MovToMemory(size_t reg)
m_emitter.MOV(64, tmp, m_regs[reg].loc);
break;
default:
_assert_msg_(DSPLLE, 0, "unsupported memory size");
ASSERT_MSG(DSPLLE, 0, "unsupported memory size");
break;
}
m_regs[reg].dirty = false;
@@ -678,7 +678,7 @@ OpArg DSPJitRegCache::GetReg(int reg, bool load)
shift = 0;
}
_assert_msg_(DSPLLE, !m_regs[real_reg].used, "register %d already in use", real_reg);
ASSERT_MSG(DSPLLE, !m_regs[real_reg].used, "register %d already in use", real_reg);
if (m_regs[real_reg].used)
{
@@ -689,7 +689,7 @@ OpArg DSPJitRegCache::GetReg(int reg, bool load)
MovToHostReg(real_reg, load);
// TODO: actually handle INVALID_REG
_assert_msg_(DSPLLE, m_regs[real_reg].loc.IsSimpleReg(), "did not get host reg for %d", reg);
ASSERT_MSG(DSPLLE, m_regs[real_reg].loc.IsSimpleReg(), "did not get host reg for %d", reg);
RotateHostReg(real_reg, shift, load);
const OpArg oparg = m_regs[real_reg].loc;
@@ -815,7 +815,7 @@ void DSPJitRegCache::ReadReg(int sreg, X64Reg host_dreg, RegisterExtension exten
m_emitter.MOV(64, R(host_dreg), reg);
break;
default:
_assert_msg_(DSPLLE, 0, "unsupported memory size");
ASSERT_MSG(DSPLLE, 0, "unsupported memory size");
break;
}
PutReg(sreg, false);
@@ -845,7 +845,7 @@ void DSPJitRegCache::WriteReg(int dreg, OpArg arg)
}
break;
default:
_assert_msg_(DSPLLE, 0, "unsupported memory size");
ASSERT_MSG(DSPLLE, 0, "unsupported memory size");
break;
}
}
@@ -863,7 +863,7 @@ void DSPJitRegCache::WriteReg(int dreg, OpArg arg)
m_emitter.MOV(64, reg, arg);
break;
default:
_assert_msg_(DSPLLE, 0, "unsupported memory size");
ASSERT_MSG(DSPLLE, 0, "unsupported memory size");
break;
}
}
@@ -910,16 +910,16 @@ void DSPJitRegCache::SpillXReg(X64Reg reg)
{
if (m_xregs[reg].guest_reg <= DSP_REG_MAX_MEM_BACKED)
{
_assert_msg_(DSPLLE, !m_regs[m_xregs[reg].guest_reg].used,
"to be spilled host reg %x(guest reg %zx) still in use!", reg,
m_xregs[reg].guest_reg);
ASSERT_MSG(DSPLLE, !m_regs[m_xregs[reg].guest_reg].used,
"to be spilled host reg %x(guest reg %zx) still in use!", reg,
m_xregs[reg].guest_reg);
MovToMemory(m_xregs[reg].guest_reg);
}
else
{
_assert_msg_(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_NONE,
"to be spilled host reg %x still in use!", reg);
ASSERT_MSG(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_NONE,
"to be spilled host reg %x still in use!", reg);
}
}
@@ -950,7 +950,7 @@ X64Reg DSPJitRegCache::GetFreeXReg()
{
X64Reg reg = FindSpillFreeXReg();
_assert_msg_(DSPLLE, reg != INVALID_REG, "could not find register");
ASSERT_MSG(DSPLLE, reg != INVALID_REG, "could not find register");
if (reg == INVALID_REG)
{
m_emitter.INT3();
@@ -972,7 +972,7 @@ void DSPJitRegCache::GetXReg(X64Reg reg)
{
SpillXReg(reg);
}
_assert_msg_(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_NONE, "register already in use");
ASSERT_MSG(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_NONE, "register already in use");
m_xregs[reg].guest_reg = DSP_REG_USED;
}
@@ -984,7 +984,7 @@ void DSPJitRegCache::PutXReg(X64Reg reg)
return;
}
_assert_msg_(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_USED, "PutXReg without get(Free)XReg");
ASSERT_MSG(DSPLLE, m_xregs[reg].guest_reg == DSP_REG_USED, "PutXReg without get(Free)XReg");
m_xregs[reg].guest_reg = DSP_REG_NONE;
}
Source/Core/Core/FifoPlayer/FifoAnalyzer.cpp
+5 -5
View File
@@ -102,7 +102,7 @@ u32 AnalyzeCommand(const u8* data, DecodeMode mode)
// The recorder should have expanded display lists into the fifo stream and skipped the call to
// start them
// That is done to make it easier to track where memory is updated
_assert_(false);
ASSERT(false);
data += 8;
break;
@@ -170,17 +170,17 @@ void LoadCPReg(u32 subCmd, u32 value, CPMemory& cpMem)
break;
case 0x70:
_assert_((subCmd & 0x0F) < 8);
ASSERT((subCmd & 0x0F) < 8);
cpMem.vtxAttr[subCmd & 7].g0.Hex = value;
break;
case 0x80:
_assert_((subCmd & 0x0F) < 8);
ASSERT((subCmd & 0x0F) < 8);
cpMem.vtxAttr[subCmd & 7].g1.Hex = value;
break;
case 0x90:
_assert_((subCmd & 0x0F) < 8);
ASSERT((subCmd & 0x0F) < 8);
cpMem.vtxAttr[subCmd & 7].g2.Hex = value;
break;
@@ -267,7 +267,7 @@ void CalculateVertexElementSizes(int sizes[], int vatIndex, const CPMemory& cpMe
size = 4;
break;
default:
_assert_(0);
ASSERT(0);
break;
}
break;
Source/Core/Core/FifoPlayer/FifoPlayer.cpp
+1 -1
View File
@@ -328,7 +328,7 @@ void FifoPlayer::WriteFramePart(u32 dataStart, u32 dataEnd, u32& nextMemUpdate,
void FifoPlayer::WriteAllMemoryUpdates()
{
_assert_(m_File);
ASSERT(m_File);
for (u32 frameNum = 0; frameNum < m_File->GetFrameCount(); ++frameNum)
{

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