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more WIP BBA crap...nothing nice to see.

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6672 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
2010-12-27 22:30:24 +00:00
parent 33506f5bdc
commit 722b7db8f9
7 changed files with 488 additions and 485 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Source/Core/Core/Src/ConfigManager.cpp
+2
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@@ -155,6 +155,7 @@ void SConfig::SaveSettings()
ini.Set("Core", "SlotA", m_EXIDevice[0]);
ini.Set("Core", "SlotB", m_EXIDevice[1]);
ini.Set("Core", "SerialPort1", m_EXIDevice[2]);
ini.Set("Core", "BBA_MAC", m_bba_mac);
char sidevicenum[16];
for (int i = 0; i < 4; ++i)
{
@@ -279,6 +280,7 @@ void SConfig::LoadSettings()
ini.Get("Core", "SlotA", (int*)&m_EXIDevice[0], EXIDEVICE_MEMORYCARD_A);
ini.Get("Core", "SlotB", (int*)&m_EXIDevice[1], EXIDEVICE_NONE);
ini.Get("Core", "SerialPort1", (int*)&m_EXIDevice[2], EXIDEVICE_NONE);
ini.Get("Core", "BBA_MAC", &m_bba_mac);
ini.Get("Core", "ProfiledReJIT",&m_LocalCoreStartupParameter.bJITProfiledReJIT, false);
ini.Get("Core", "TimeProfiling",&m_LocalCoreStartupParameter.bJITILTimeProfiling, false);
ini.Get("Core", "OutputIR", &m_LocalCoreStartupParameter.bJITILOutputIR, false);
Source/Core/Core/Src/ConfigManager.h
+1
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@@ -64,6 +64,7 @@ struct SConfig : NonCopyable
std::string m_strMemoryCardB;
TEXIDevices m_EXIDevice[3];
TSIDevices m_SIDevice[4];
std::string m_bba_mac;
// interface language
INTERFACE_LANGUAGE m_InterfaceLanguage;
Source/Core/Core/Src/HW/BBA-TAP/TAP_Win32.cpp
+152 -112
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File diff suppressed because it is too large Load Diff
Source/Core/Core/Src/HW/EXI_Channel.cpp
+1
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@@ -234,6 +234,7 @@ void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
case EXI_READ: m_ImmData = pDevice->ImmRead(m_Control.TLEN + 1); break;
case EXI_WRITE: pDevice->ImmWrite(m_ImmData, m_Control.TLEN + 1); break;
case EXI_READWRITE:
ERROR_LOG(SP1, "RW UNSUPPORTED");
/* Only used by USBGecko?
pDevice->ImmWrite(m_ImmData, m_Control.TLEN + 1);
m_ImmData = pDevice->ImmRead(m_Control.TLEN + 1); */
Source/Core/Core/Src/HW/EXI_Device.cpp
+1 -1
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@@ -130,7 +130,7 @@ IEXIDevice* EXIDevice_Create(TEXIDevices _EXIDevice)
break;
case EXIDEVICE_ETH:
return new CEXIETHERNET();
return new CEXIETHERNET(SConfig::GetInstance().m_bba_mac);
break;
case EXIDEVICE_AM_BASEBOARD:
Source/Core/Core/Src/HW/EXI_DeviceEthernet.cpp
+217 -303
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File diff suppressed because it is too large Load Diff
Source/Core/Core/Src/HW/EXI_DeviceEthernet.h
+114 -69
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@@ -39,8 +39,6 @@ inline u32 getbitsw(u32 dword, int start, int end) {
return (dword & makemaskw(start, end)) >> (31 - end);
}
void DEBUGPRINT(const char * format, ...);
class WriteBuffer
{
public:
@@ -56,7 +54,7 @@ public:
{
if (_size + s >= ucapacity)
{
DEBUGPRINT("Write too large!");
INFO_LOG(SP1, "Write too large!");
exit(0);
}
@@ -113,7 +111,108 @@ private:
#define INVALID_P 0xFFFF
// TODO: convert into unions
// Network Control Register A, RW
enum NCRA
{
NCRA_RESET = 0x01, // RESET
NCRA_ST0 = 0x02, // Start transmit command/status
NCRA_ST1 = 0x04, // "
NCRA_SR = 0x08, // Start Receive
};
// Network Control Register B, RW
enum NCRB
{
NCRB_PR = 0x01, // Promiscuous Mode
NCRB_CA = 0x02, // Capture Effect Mode
NCRB_PM = 0x04, // Pass Multicast
NCRB_PB = 0x08, // Pass Bad Frame
NCRB_AB = 0x10, // Accept Broadcast
NCRB_HBD = 0x20, // reserved
NCRB_RXINTC = 0xC0, // Receive Interrupt Counter (mask)
};
// Interrupt Mask Register, RW, 00h
// Interrupt Register, RW, 00h
enum Interrupts
{
INT_FRAG = 0x01, // Fragment Counter
INT_R = 0x02, // Receive
INT_T = 0x04, // Transmit
INT_R_ERR = 0x08, // Receive Error
INT_T_ERR = 0x10, // Transmit Error
INT_FIFO_ERR = 0x20, // FIFO Error
INT_BUS_ERR = 0x40, // BUS Error
INT_RBF = 0x80, // RX Buffer Full
};
// NWAY Configuration Register, RW, 84h
enum NWAYC
{
NWAYC_FD = 0x01, // Full Duplex Mode
NWAYC_PS100 = 0x02, // Port Select 100/10
NWAYC_ANE = 0x03, // Autonegotiation Enable
NWAYC_ANS_RA = 0x04, // Restart Autonegotiation
NWAYC_LTE = 0x08, // Link Test Enable
};
enum NWAYS
{
NWAYS_LS10 = 0x01,
NWAYS_LS100 = 0x02,
NWAYS_LPNWAY = 0x04,
NWAYS_ANCLPT = 0x08,
NWAYS_100TXF = 0x10,
NWAYS_100TXH = 0x20,
NWAYS_10TXF = 0x40,
NWAYS_10TXH = 0x80
};
enum
{
BBA_NCRA = 0x00,
BBA_NCRB = 0x01,
BBA_LTPS = 0x04,
BBA_LRPS = 0x05,
BBA_IMR = 0x08,
BBA_IR = 0x09,
BBA_BP = 0x0a,
BBA_TLBP = 0x0c,
BBA_TWP = 0x0e,
BBA_TRP = 0x12,
BBA_RWP = 0x16,
BBA_RRP = 0x18,
BBA_RHBP = 0x1a,
BBA_RXINTT = 0x14,
BBA_NAFR_PAR0 = 0x20,
BBA_NAFR_PAR1 = 0x21,
BBA_NAFR_PAR2 = 0x22,
BBA_NAFR_PAR3 = 0x23,
BBA_NAFR_PAR4 = 0x24,
BBA_NAFR_PAR5 = 0x25,
BBA_NWAYC = 0x30,
BBA_NWAYS = 0x31,
BBA_GCA = 0x32,
BBA_MISC = 0x3d,
BBA_TXFIFOCNT = 0x3e,
BBA_WRTXFIFOD = 0x48,
BBA_MISC2 = 0x50,
BBA_SI_ACTRL = 0x5c,
BBA_SI_STATUS = 0x5d,
BBA_SI_ACTRL2 = 0x60,
};
enum
{
BBA_RECV_SIZE = 0x800,
@@ -125,65 +224,6 @@ enum
SIZEOF_RECV_DESCRIPTOR = 4,
EXI_DEVTYPE_ETHER = 0x04020200,
BBA_NCRA = 0x00, // Network Control Register A, RW
BBA_NCRA_RESET = 0x01, // RESET
BBA_NCRA_ST0 = 0x02, // ST0, Start transmit command/status
BBA_NCRA_ST1 = 0x04, // ST1, "
BBA_NCRA_SR = 0x08, // SR, Start Receive
BBA_NCRB = 0x01, // Network Control Register B, RW
BBA_NCRB_PR = 0x01, // PR, Promiscuous Mode
BBA_NCRB_CA = 0x02, // CA, Capture Effect Mode
BBA_NCRB_PM = 0x04, // PM, Pass Multicast
BBA_NCRB_PB = 0x08, // PB, Pass Bad Frame
BBA_NCRB_AB = 0x10, // AB, Accept Broadcast
BBA_NCRB_HBD = 0x20, // HBD, reserved
BBA_NCRB_RXINTC0 = 0x40, // RXINTC, Receive Interrupt Counter
BBA_NCRB_RXINTC1 = 0x80, // "
BBA_NCRB_1_PACKET_PER_INT = 0x00, // 0 0
BBA_NCRB_2_PACKETS_PER_INT = 0x40, // 0 1
BBA_NCRB_4_PACKETS_PER_INT = 0x80, // 1 0
BBA_NCRB_8_PACKETS_PER_INT = 0xC0, // 1 1
BBA_IMR = 0x08, // Interrupt Mask Register, RW, 00h
BBA_IR = 0x09, // Interrupt Register, RW, 00h
BBA_IR_FRAGI = 0x01, // FRAGI, Fragment Counter Interrupt
BBA_IR_RI = 0x02, // RI, Receive Interrupt
BBA_IR_TI = 0x04, // TI, Transmit Interrupt
BBA_IR_REI = 0x08, // REI, Receive Error Interrupt
BBA_IR_TEI = 0x10, // TEI, Transmit Error Interrupt
BBA_IR_FIFOEI = 0x20, // FIFOEI, FIFO Error Interrupt
BBA_IR_BUSEI = 0x40, // BUSEI, BUS Error Interrupt
BBA_IR_RBFI = 0x80, // RBFI, RX Buffer Full Interrupt
BBA_NWAYC = 0x30, // NWAY Configuration Register, RW, 84h
BBA_NWAYC_FD = 0x01, // FD, Full Duplex Mode
BBA_NWAYC_PS100 = 0x02, // PS100/10, Port Select 100/10
BBA_NWAYC_ANE = 0x04, // ANE, Autonegotiation Enable
BBA_NWAYC_ANS_RA = 0x08, // ANS, Restart Autonegotiation
BBA_NWAYC_LTE = 0x80, // LTE, Link Test Enable
BBA_NWAYS = 0x31,
BBA_NWAYS_LS10 = 0x01,
BBA_NWAYS_LS100 = 0x02,
BBA_NWAYS_LPNWAY = 0x04,
BBA_NWAYS_ANCLPT = 0x08,
BBA_NWAYS_100TXF = 0x10,
BBA_NWAYS_100TXH = 0x20,
BBA_NWAYS_10TXF = 0x40,
BBA_NWAYS_10TXH = 0x80,
BBA_INTERRUPT_RECV = 0x02,
BBA_INTERRUPT_SENT = 0x04,
BBA_INTERRUPT_RECV_ERROR = 0x08,
BBA_INTERRUPT_SEND_ERROR = 0x10,
BBA_RWP = 0x16, // Receive Buffer Write Page Pointer Register
BBA_RRP = 0x18, // Receive Buffer Read Page Pointer Register
BBA_SI_ACTRL2 = 0x60
};
enum
@@ -192,19 +232,22 @@ enum
EXPECT_ID
};
static u32 mPacketsSent = 0;
class CEXIETHERNET : public IEXIDevice
{
public:
CEXIETHERNET();
CEXIETHERNET(const std::string& mac_addr);
~CEXIETHERNET();
void SetMAC(u8 *new_addr);
void SetCS(int _iCS);
bool IsPresent();
void Update();
bool IsInterruptSet();
void ImmWrite(u32 _uData, u32 _uSize);
u32 ImmRead(u32 _uSize);
void DMAWrite(u32 _uAddr, u32 _uSize);
void DMARead(u32 _uAddr, u32 _uSize);
void ImmWrite(u32 data, u32 size);
u32 ImmRead(u32 size);
void DMAWrite(u32 addr, u32 size);
void DMARead(u32 addr, u32 size);
//private:
// STATE_TO_SAVE
@@ -212,7 +255,7 @@ public:
u32 m_uCommand;
bool m_bInterruptSet;
u32 mWriteP, mReadP;
u16 mWriteP, mReadP;
bool mExpectSpecialImmRead; //reset to false on deselect
u32 mSpecialImmData;
@@ -251,6 +294,8 @@ public:
volatile bool mWaiting;
static const u8 mac_address_default[6];
u8 mac_address[6];
u8 mRecvBuffer[BBA_RECV_SIZE];
#ifdef _WIN32
HANDLE mHAdapter, mHRecvEvent, mHReadWait;