mirror of
https://github.com/izzy2lost/dolphin.git
synced 2026-06-19 01:16:48 -07:00
Externals: update Bochs to newer version
Should resolve the disassembler not handling all the opcodes Dolphin generates.
This commit is contained in:
Fiora
+10
-6
@@ -50,14 +50,18 @@
|
||||
<ClInclude Include="dis_tables.h" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="dis_decode.cpp" />
|
||||
<ClCompile Include="dis_groups.cpp" />
|
||||
<ClCompile Include="resolve.cpp" />
|
||||
<ClCompile Include="syntax.cpp" />
|
||||
<ClCompile Include="dis_decode.cc" />
|
||||
<ClCompile Include="dis_groups.cc" />
|
||||
<ClCompile Include="resolve.cc" />
|
||||
<ClCompile Include="syntax.cc" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="dis_tables.inl" />
|
||||
<None Include="opcodes.inl" />
|
||||
<None Include="opcodes.inc" />
|
||||
<None Include="dis_tables.inc" />
|
||||
<None Include="dis_tables_avx.inc" />
|
||||
<None Include="dis_tables_sse.inc" />
|
||||
<None Include="dis_tables_x87.inc" />
|
||||
<None Include="dis_tables_xop.inc" />
|
||||
</ItemGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
set(SRCS dis_decode.cpp
|
||||
dis_groups.cpp
|
||||
resolve.cpp
|
||||
syntax.cpp)
|
||||
set(SRCS dis_decode.cc
|
||||
dis_groups.cc
|
||||
resolve.cc
|
||||
syntax.cc)
|
||||
|
||||
if(WIN32)
|
||||
set(SRCS ${SRCS} stdafx.cpp)
|
||||
|
||||
Vendored
+82
@@ -0,0 +1,82 @@
|
||||
# Copyright (C) 2001 The Bochs Project
|
||||
#
|
||||
# This library is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU Lesser General Public
|
||||
# License as published by the Free Software Foundation; either
|
||||
# version 2 of the License, or (at your option) any later version.
|
||||
#
|
||||
# This library is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
# Lesser General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU Lesser General Public
|
||||
# License along with this library; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
|
||||
@SUFFIX_LINE@
|
||||
|
||||
srcdir = @srcdir@
|
||||
VPATH = @srcdir@
|
||||
top_builddir = ..
|
||||
top_srcdir = @top_srcdir@
|
||||
|
||||
SHELL = @SHELL@
|
||||
|
||||
@SET_MAKE@
|
||||
|
||||
CXX = @CXX@
|
||||
CXXFLAGS = @CXXFLAGS@ @GUI_CXXFLAGS@
|
||||
|
||||
LDFLAGS = @LDFLAGS@
|
||||
LIBS = @LIBS@
|
||||
RANLIB = @RANLIB@
|
||||
|
||||
|
||||
# ===========================================================
|
||||
# end of configurable options
|
||||
# ===========================================================
|
||||
|
||||
|
||||
BX_OBJS = \
|
||||
dis_decode.o \
|
||||
dis_groups.o \
|
||||
resolve.o \
|
||||
syntax.o
|
||||
|
||||
BX_INCLUDES = disasm.h
|
||||
|
||||
BX_INCDIRS = -I.. -I$(srcdir)/.. -I../@INSTRUMENT_DIR@ -I$(srcdir)/../@INSTRUMENT_DIR@
|
||||
|
||||
all: libdisasm.a
|
||||
|
||||
.@CPP_SUFFIX@.o:
|
||||
$(CXX) @DASH@c $(BX_INCDIRS) $(CXXFLAGS) @CXXFP@$< @OFP@$@
|
||||
|
||||
|
||||
|
||||
libdisasm.a: $(BX_OBJS)
|
||||
@RMCOMMAND@ libdisasm.a
|
||||
@MAKELIB@ $(BX_OBJS)
|
||||
$(RANLIB) libdisasm.a
|
||||
|
||||
$(BX_OBJS): $(BX_INCLUDES)
|
||||
|
||||
|
||||
clean:
|
||||
@RMCOMMAND@ *.o
|
||||
@RMCOMMAND@ *.a
|
||||
|
||||
dist-clean: clean
|
||||
@RMCOMMAND@ Makefile
|
||||
|
||||
###########################################
|
||||
# dependencies generated by
|
||||
# gcc -MM -I.. -I../instrument/stubs *.cc | sed 's/\.cc/.@CPP_SUFFIX@/g'
|
||||
###########################################
|
||||
dis_decode.o: dis_decode.@CPP_SUFFIX@ disasm.h ../config.h dis_tables.h opcodes.inc \
|
||||
dis_tables.inc dis_tables_x87.inc dis_tables_sse.inc dis_tables_avx.inc dis_tables_xop.inc
|
||||
dis_groups.o: dis_groups.@CPP_SUFFIX@ disasm.h ../config.h
|
||||
resolve.o: resolve.@CPP_SUFFIX@ disasm.h ../config.h
|
||||
syntax.o: syntax.@CPP_SUFFIX@ disasm.h ../config.h
|
||||
Vendored
+4
@@ -38,4 +38,8 @@ typedef Bit64u bx_address;
|
||||
|
||||
#endif
|
||||
|
||||
#define BX_CONST64(x) (x##LL)
|
||||
#define GET32L(val64) ((Bit32u)(((Bit64u)(val64)) & 0xFFFFFFFF))
|
||||
#define GET32H(val64) ((Bit32u)(((Bit64u)(val64)) >> 32))
|
||||
|
||||
#endif
|
||||
|
||||
Vendored
+557
File diff suppressed because it is too large
Load Diff
-328
@@ -1,328 +0,0 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: dis_decode.cc,v 1.32 2006/05/12 17:04:19 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "disasm.h"
|
||||
#include "dis_tables.h"
|
||||
|
||||
#define OPCODE(entry) ((BxDisasmOpcodeInfo_t*) entry->OpcodeInfo)
|
||||
#define OPCODE_TABLE(entry) ((BxDisasmOpcodeTable_t*) entry->OpcodeInfo)
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
|
||||
static const unsigned char instruction_has_modrm[512] = {
|
||||
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
|
||||
/* ------------------------------- */
|
||||
/* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
|
||||
/* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
|
||||
/* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
|
||||
/* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
|
||||
/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
|
||||
/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* A0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* B0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* C0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
|
||||
/* D0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
|
||||
/* E0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
/* F0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1,
|
||||
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
|
||||
/* ------------------------------- */
|
||||
1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0F 00 */
|
||||
1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 0F 10 */
|
||||
1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 0F 20 */
|
||||
0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 0F 30 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 40 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 50 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 60 */
|
||||
1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 0F 70 */
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 80 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 90 */
|
||||
0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* 0F A0 */
|
||||
1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* 0F B0 */
|
||||
1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 0F C0 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F D0 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F E0 */
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* 0F F0 */
|
||||
/* ------------------------------- */
|
||||
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
|
||||
};
|
||||
|
||||
unsigned disassembler::disasm(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
|
||||
{
|
||||
x86_insn insn = decode(is_32, is_64, base, ip, instr, disbuf);
|
||||
return insn.ilen;
|
||||
}
|
||||
|
||||
x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
|
||||
{
|
||||
x86_insn insn(is_32, is_64);
|
||||
const Bit8u *instruction_begin = instruction = instr;
|
||||
resolve_modrm = NULL;
|
||||
unsigned b3 = 0;
|
||||
|
||||
db_eip = ip;
|
||||
db_base = base; // cs linear base (base for PM & cs<<4 for RM & VM)
|
||||
|
||||
disbufptr = disbuf; // start sprintf()'ing into beginning of buffer
|
||||
|
||||
#define SSE_PREFIX_NONE 0
|
||||
#define SSE_PREFIX_66 1
|
||||
#define SSE_PREFIX_F2 2
|
||||
#define SSE_PREFIX_F3 3 /* only one SSE prefix could be used */
|
||||
unsigned sse_prefix = SSE_PREFIX_NONE;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
insn.b1 = fetch_byte();
|
||||
insn.prefixes++;
|
||||
|
||||
switch(insn.b1) {
|
||||
case 0x40: // rex
|
||||
case 0x41:
|
||||
case 0x42:
|
||||
case 0x43:
|
||||
case 0x44:
|
||||
case 0x45:
|
||||
case 0x46:
|
||||
case 0x47:
|
||||
case 0x48:
|
||||
case 0x49:
|
||||
case 0x4A:
|
||||
case 0x4B:
|
||||
case 0x4C:
|
||||
case 0x4D:
|
||||
case 0x4E:
|
||||
case 0x4F:
|
||||
if (! is_64) break;
|
||||
insn.extend8b = 1;
|
||||
if (insn.b1 & 0x8) {
|
||||
insn.os_64 = 1;
|
||||
insn.os_32 = 1;
|
||||
}
|
||||
if (insn.b1 & 0x4) insn.rex_r = 8;
|
||||
if (insn.b1 & 0x2) insn.rex_x = 8;
|
||||
if (insn.b1 & 0x1) insn.rex_b = 8;
|
||||
continue;
|
||||
|
||||
case 0x26: // ES:
|
||||
if (! is_64) insn.seg_override = ES_REG;
|
||||
continue;
|
||||
|
||||
case 0x2e: // CS:
|
||||
if (! is_64) insn.seg_override = CS_REG;
|
||||
continue;
|
||||
|
||||
case 0x36: // SS:
|
||||
if (! is_64) insn.seg_override = SS_REG;
|
||||
continue;
|
||||
|
||||
case 0x3e: // DS:
|
||||
if (! is_64) insn.seg_override = DS_REG;
|
||||
continue;
|
||||
|
||||
case 0x64: // FS:
|
||||
insn.seg_override = FS_REG;
|
||||
continue;
|
||||
|
||||
case 0x65: // GS:
|
||||
insn.seg_override = GS_REG;
|
||||
continue;
|
||||
|
||||
case 0x66: // operand size override
|
||||
if (!insn.os_64) insn.os_32 = !is_32;
|
||||
if (!sse_prefix) sse_prefix = SSE_PREFIX_66;
|
||||
continue;
|
||||
|
||||
case 0x67: // address size override
|
||||
if (!is_64) insn.as_32 = !is_32;
|
||||
insn.as_64 = 0;
|
||||
continue;
|
||||
|
||||
case 0xf0: // lock
|
||||
continue;
|
||||
|
||||
case 0xf2: // repne
|
||||
if (!sse_prefix) sse_prefix = SSE_PREFIX_F2;
|
||||
continue;
|
||||
|
||||
case 0xf3: // rep
|
||||
if (!sse_prefix) sse_prefix = SSE_PREFIX_F3;
|
||||
continue;
|
||||
|
||||
// no more prefixes
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
insn.prefixes--;
|
||||
break;
|
||||
}
|
||||
|
||||
if (insn.b1 == 0x0f)
|
||||
{
|
||||
insn.b1 = 0x100 | fetch_byte();
|
||||
}
|
||||
|
||||
const BxDisasmOpcodeTable_t *opcode_table, *entry;
|
||||
|
||||
if (is_64) {
|
||||
if (insn.os_64)
|
||||
opcode_table = BxDisasmOpcodes64q;
|
||||
else if (insn.os_32)
|
||||
opcode_table = BxDisasmOpcodes64d;
|
||||
else
|
||||
opcode_table = BxDisasmOpcodes64w;
|
||||
} else {
|
||||
if (insn.os_32)
|
||||
opcode_table = BxDisasmOpcodes32;
|
||||
else
|
||||
opcode_table = BxDisasmOpcodes16;
|
||||
}
|
||||
|
||||
entry = opcode_table + insn.b1;
|
||||
|
||||
// will require 3rd byte for 3-byte opcode
|
||||
if (entry->Attr & _GRP3BTAB) b3 = fetch_byte();
|
||||
|
||||
if (instruction_has_modrm[insn.b1])
|
||||
{
|
||||
decode_modrm(&insn);
|
||||
}
|
||||
|
||||
int attr = entry->Attr;
|
||||
while(attr)
|
||||
{
|
||||
switch(attr) {
|
||||
case _GROUPN:
|
||||
entry = &(OPCODE_TABLE(entry)[insn.nnn]);
|
||||
break;
|
||||
|
||||
case _GRPSSE:
|
||||
if(sse_prefix) insn.prefixes--;
|
||||
/* For SSE opcodes, look into another 4 entries table
|
||||
with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
|
||||
entry = &(OPCODE_TABLE(entry)[sse_prefix]);
|
||||
break;
|
||||
|
||||
case _SPLIT11B:
|
||||
entry = &(OPCODE_TABLE(entry)[insn.mod != 3]); /* REG/MEM */
|
||||
break;
|
||||
|
||||
case _GRPRM:
|
||||
entry = &(OPCODE_TABLE(entry)[insn.rm]);
|
||||
break;
|
||||
|
||||
case _GRPFP:
|
||||
if(insn.mod != 3)
|
||||
{
|
||||
entry = &(OPCODE_TABLE(entry)[insn.nnn]);
|
||||
} else {
|
||||
int index = (insn.b1-0xD8)*64 + (insn.modrm & 0x3f);
|
||||
entry = &(BxDisasmOpcodeInfoFP[index]);
|
||||
}
|
||||
break;
|
||||
|
||||
case _GRP3DNOW:
|
||||
entry = &(BxDisasm3DNowGroup[peek_byte()]);
|
||||
break;
|
||||
|
||||
case _GRP3BTAB:
|
||||
entry = &(OPCODE_TABLE(entry)[b3 >> 4]);
|
||||
break;
|
||||
|
||||
case _GRP3BOP:
|
||||
entry = &(OPCODE_TABLE(entry)[b3 & 15]);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Internal disassembler error - unknown attribute !\n");
|
||||
return x86_insn(is_32, is_64);
|
||||
}
|
||||
|
||||
/* get additional attributes from group table */
|
||||
attr = entry->Attr;
|
||||
}
|
||||
|
||||
#define BRANCH_NOT_TAKEN 0x2E
|
||||
#define BRANCH_TAKEN 0x3E
|
||||
|
||||
unsigned branch_hint = 0;
|
||||
|
||||
// print prefixes
|
||||
for(unsigned i=0;i<insn.prefixes;i++)
|
||||
{
|
||||
Bit8u prefix_byte = *(instr+i);
|
||||
|
||||
if (prefix_byte == 0xF3 || prefix_byte == 0xF2 || prefix_byte == 0xF0)
|
||||
{
|
||||
const BxDisasmOpcodeTable_t *prefix = &(opcode_table[prefix_byte]);
|
||||
dis_sprintf("%s ", OPCODE(prefix)->IntelOpcode);
|
||||
}
|
||||
|
||||
// branch hint for jcc instructions
|
||||
if ((insn.b1 >= 0x070 && insn.b1 <= 0x07F) ||
|
||||
(insn.b1 >= 0x180 && insn.b1 <= 0x18F))
|
||||
{
|
||||
if (prefix_byte == BRANCH_NOT_TAKEN || prefix_byte == BRANCH_TAKEN)
|
||||
branch_hint = prefix_byte;
|
||||
}
|
||||
}
|
||||
|
||||
const BxDisasmOpcodeInfo_t *opcode = OPCODE(entry);
|
||||
|
||||
// patch jecx opcode
|
||||
if (insn.b1 == 0xE3 && insn.as_32 && !insn.as_64)
|
||||
opcode = &Ia_jecxz_Jb;
|
||||
|
||||
// fix nop opcode
|
||||
if (insn.b1 == 0x90 && !insn.rex_b) {
|
||||
opcode = &Ia_nop;
|
||||
}
|
||||
|
||||
// print instruction disassembly
|
||||
if (intel_mode)
|
||||
print_disassembly_intel(&insn, opcode);
|
||||
else
|
||||
print_disassembly_att (&insn, opcode);
|
||||
|
||||
if (branch_hint == BRANCH_NOT_TAKEN)
|
||||
{
|
||||
dis_sprintf(", not taken");
|
||||
}
|
||||
else if (branch_hint == BRANCH_TAKEN)
|
||||
{
|
||||
dis_sprintf(", taken");
|
||||
}
|
||||
|
||||
insn.ilen = (unsigned)(instruction - instruction_begin);
|
||||
|
||||
return insn;
|
||||
}
|
||||
|
||||
void disassembler::dis_sprintf(const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, fmt);
|
||||
vsprintf(disbufptr, fmt, ap);
|
||||
va_end(ap);
|
||||
|
||||
disbufptr += strlen(disbufptr);
|
||||
}
|
||||
|
||||
void disassembler::dis_putc(char symbol)
|
||||
{
|
||||
*disbufptr++ = symbol;
|
||||
*disbufptr = 0;
|
||||
}
|
||||
+294
-146
File diff suppressed because it is too large
Load Diff
Vendored
+133
-67
@@ -1,6 +1,23 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: dis_tables.h,v 1.29 2006/04/27 15:11:45 sshwarts Exp $
|
||||
// $Id: dis_tables.h 11878 2013-10-11 20:09:51Z sshwarts $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2005-2012 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
// License as published by the Free Software Foundation; either
|
||||
// version 2 of the License, or (at your option) any later version.
|
||||
//
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
// Lesser General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General Public
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
#ifndef _BX_DISASM_TABLES_
|
||||
#define _BX_DISASM_TABLES_
|
||||
@@ -11,70 +28,93 @@
|
||||
#define _GRPFP 3
|
||||
#define _GRP3DNOW 4
|
||||
#define _GRPSSE 5
|
||||
#define _GRPRM 6
|
||||
#define _GRP3BOP 7
|
||||
#define _GRP3BTAB 8
|
||||
#define _GRPSSE66 6
|
||||
#define _GRPSSEF2 7
|
||||
#define _GRPSSEF3 8
|
||||
#define _GRPSSENONE 9
|
||||
#define _GRPSSE2 10
|
||||
#define _GRPRM 11
|
||||
#define _GRP3BOP 12
|
||||
#define _GRP64B 13
|
||||
#define _GRPVEXW 14
|
||||
|
||||
/* ************************************************************************ */
|
||||
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
|
||||
#define GRPSSE2(n) _GRPSSE2, BxDisasmGroupSSE_##n
|
||||
#define GRPAVX(n) _GRPSSE, BxDisasmGroupAVX_##n
|
||||
#define GRPAVX2(n) _GRPSSE2, BxDisasmGroupAVX_##n
|
||||
#define GRPN(n) _GROUPN, BxDisasmGroup##n
|
||||
#define GRPRM(n) _GRPRM, BxDisasmGroupRm##n
|
||||
#define GRPMOD(n) _SPLIT11B, BxDisasmGroupMod##n
|
||||
#define GRPFP(n) _GRPFP, BxDisasmFPGroup##n
|
||||
#define GRP3DNOW _GRP3DNOW, BxDisasm3DNowGroup
|
||||
#define GR3BOP(n) _GRP3BOP, BxDisasm3ByteOp##n
|
||||
#define GR3BTAB(n) _GRP3BTAB, BxDisasm3ByteTable##n
|
||||
#define GR3BTAB(n) _GRP3BOP, BxDisasm3ByteOpTable##n
|
||||
#define GR64BIT(n) _GRP64B, BxDisasmGrpOs64B_##n
|
||||
#define GRPVEXW(n) _GRPVEXW, BxDisasmGrpVexW_##n
|
||||
/* ************************************************************************ */
|
||||
|
||||
/* ************************************************************************ */
|
||||
#define GRPSSE66(n) _GRPSSE66, &n
|
||||
#define GRPSSEF2(n) _GRPSSEF2, &n
|
||||
#define GRPSSEF3(n) _GRPSSEF3, &n
|
||||
#define GRPSSENONE(n) _GRPSSENONE, &n
|
||||
/* ************************************************************************ */
|
||||
|
||||
#define Apw &disassembler::Apw
|
||||
#define Apd &disassembler::Apd
|
||||
|
||||
#define AL &disassembler::AL
|
||||
#define CL &disassembler::CL
|
||||
#define AX &disassembler::AX
|
||||
#define DX &disassembler::DX
|
||||
#define AL_Reg &disassembler::AL_Reg
|
||||
#define CL_Reg &disassembler::CL_Reg
|
||||
#define AX_Reg &disassembler::AX_Reg
|
||||
#define DX_Reg &disassembler::DX_Reg
|
||||
|
||||
#define EAX &disassembler::EAX
|
||||
#define RAX &disassembler::RAX
|
||||
#define EAX_Reg &disassembler::EAX_Reg
|
||||
#define RAX_Reg &disassembler::RAX_Reg
|
||||
#define RCX_Reg &disassembler::RCX_Reg
|
||||
|
||||
#define CS &disassembler::CS
|
||||
#define DS &disassembler::DS
|
||||
#define ES &disassembler::ES
|
||||
#define SS &disassembler::SS
|
||||
#define FS &disassembler::FS
|
||||
#define GS &disassembler::GS
|
||||
#define CS &disassembler::CS
|
||||
#define DS &disassembler::DS
|
||||
#define ES &disassembler::ES
|
||||
#define SS &disassembler::SS
|
||||
#define FS &disassembler::FS
|
||||
#define GS &disassembler::GS
|
||||
|
||||
#define Sw &disassembler::Sw
|
||||
#define Sw &disassembler::Sw
|
||||
|
||||
#define Td &disassembler::Td
|
||||
#define Cd &disassembler::Cd
|
||||
#define Cq &disassembler::Cq
|
||||
|
||||
#define Cd &disassembler::Cd
|
||||
#define Cq &disassembler::Cq
|
||||
#define Dd &disassembler::Dd
|
||||
#define Dq &disassembler::Dq
|
||||
|
||||
#define Dd &disassembler::Dd
|
||||
#define Dq &disassembler::Dq
|
||||
#define Reg8 &disassembler::Reg8
|
||||
#define RX &disassembler::RX
|
||||
#define ERX &disassembler::ERX
|
||||
#define RRX &disassembler::RRX
|
||||
|
||||
#define R8 &disassembler::R8
|
||||
#define RX &disassembler::RX
|
||||
#define ERX &disassembler::ERX
|
||||
#define RRX &disassembler::RRX
|
||||
#define Eb &disassembler::Eb
|
||||
#define Ew &disassembler::Ew
|
||||
#define Ed &disassembler::Ed
|
||||
#define Eq &disassembler::Eq
|
||||
#define Ey &disassembler::Ey
|
||||
#define Ebd &disassembler::Ebd
|
||||
#define Ewd &disassembler::Ewd
|
||||
|
||||
#define Eb &disassembler::Eb
|
||||
#define Ew &disassembler::Ew
|
||||
#define Ed &disassembler::Ed
|
||||
#define Eq &disassembler::Eq
|
||||
#define Gb &disassembler::Gb
|
||||
#define Gw &disassembler::Gw
|
||||
#define Gd &disassembler::Gd
|
||||
#define Gq &disassembler::Gq
|
||||
#define Gy &disassembler::Gy
|
||||
|
||||
#define Gb &disassembler::Gb
|
||||
#define Gw &disassembler::Gw
|
||||
#define Gd &disassembler::Gd
|
||||
#define Gq &disassembler::Gq
|
||||
#define By &disassembler::By
|
||||
|
||||
#define I1 &disassembler::I1
|
||||
#define Ib &disassembler::Ib
|
||||
#define Iw &disassembler::Iw
|
||||
#define Id &disassembler::Id
|
||||
#define Iq &disassembler::Iq
|
||||
#define I1 &disassembler::I1
|
||||
#define Ib &disassembler::Ib
|
||||
#define Iw &disassembler::Iw
|
||||
#define Id &disassembler::Id
|
||||
#define Iq &disassembler::Iq
|
||||
|
||||
#define IbIb &disassembler::IbIb
|
||||
#define IwIb &disassembler::IwIb
|
||||
|
||||
#define sIbw &disassembler::sIbw
|
||||
@@ -85,14 +125,15 @@
|
||||
#define ST0 &disassembler::ST0
|
||||
#define STi &disassembler::STi
|
||||
|
||||
#define Rw &disassembler::Rw
|
||||
#define Rd &disassembler::Rd
|
||||
#define Rq &disassembler::Rq
|
||||
#define Rw &disassembler::Rw
|
||||
#define Rd &disassembler::Rd
|
||||
#define Rq &disassembler::Rq
|
||||
#define Ry &disassembler::Ry
|
||||
|
||||
#define Pq &disassembler::Pq
|
||||
#define Qd &disassembler::Qd
|
||||
#define Qq &disassembler::Qq
|
||||
#define Nq &disassembler::Nq
|
||||
#define Pq &disassembler::Pq
|
||||
#define Qd &disassembler::Qd
|
||||
#define Qq &disassembler::Qq
|
||||
#define Nq &disassembler::Nq
|
||||
|
||||
#define Vq &disassembler::Vq
|
||||
#define Vdq &disassembler::Vdq
|
||||
@@ -100,8 +141,16 @@
|
||||
#define Vsd &disassembler::Vsd
|
||||
#define Vps &disassembler::Vps
|
||||
#define Vpd &disassembler::Vpd
|
||||
#define Udq &disassembler::Udq
|
||||
#define VIb &disassembler::VIb
|
||||
|
||||
#define Ups &disassembler::Ups
|
||||
#define Upd &disassembler::Upd
|
||||
#define Udq &disassembler::Udq
|
||||
#define Uq &disassembler::Uq
|
||||
|
||||
#define Wb &disassembler::Wb
|
||||
#define Ww &disassembler::Ww
|
||||
#define Wd &disassembler::Wd
|
||||
#define Wq &disassembler::Wq
|
||||
#define Wdq &disassembler::Wdq
|
||||
#define Wss &disassembler::Wss
|
||||
@@ -109,10 +158,16 @@
|
||||
#define Wps &disassembler::Wps
|
||||
#define Wpd &disassembler::Wpd
|
||||
|
||||
#define Ob &disassembler::Ob
|
||||
#define Ow &disassembler::Ow
|
||||
#define Od &disassembler::Od
|
||||
#define Oq &disassembler::Oq
|
||||
#define Hdq &disassembler::Hdq
|
||||
#define Hps &disassembler::Hps
|
||||
#define Hpd &disassembler::Hpd
|
||||
#define Hss &disassembler::Hss
|
||||
#define Hsd &disassembler::Hsd
|
||||
|
||||
#define Ob &disassembler::Ob
|
||||
#define Ow &disassembler::Ow
|
||||
#define Od &disassembler::Od
|
||||
#define Oq &disassembler::Oq
|
||||
|
||||
#define Ma &disassembler::Ma
|
||||
#define Mp &disassembler::Mp
|
||||
@@ -126,26 +181,37 @@
|
||||
#define Mdq &disassembler::Mdq
|
||||
#define Mps &disassembler::Mps
|
||||
#define Mpd &disassembler::Mpd
|
||||
#define Mss &disassembler::Mss
|
||||
#define Msd &disassembler::Msd
|
||||
|
||||
#define Xb &disassembler::Xb
|
||||
#define Xw &disassembler::Xw
|
||||
#define Xd &disassembler::Xd
|
||||
#define Xq &disassembler::Xq
|
||||
#define VSib &disassembler::VSib
|
||||
|
||||
#define Yb &disassembler::Yb
|
||||
#define Yw &disassembler::Yw
|
||||
#define Yd &disassembler::Yd
|
||||
#define Yq &disassembler::Yq
|
||||
#define Xb &disassembler::Xb
|
||||
#define Xw &disassembler::Xw
|
||||
#define Xd &disassembler::Xd
|
||||
#define Xq &disassembler::Xq
|
||||
|
||||
#define Jb &disassembler::Jb
|
||||
#define Jw &disassembler::Jw
|
||||
#define Jd &disassembler::Jd
|
||||
#define Yb &disassembler::Yb
|
||||
#define Yw &disassembler::Yw
|
||||
#define Yd &disassembler::Yd
|
||||
#define Yq &disassembler::Yq
|
||||
|
||||
#define XX 0
|
||||
#define sYq &disassembler::sYq
|
||||
#define sYdq &disassembler::sYdq
|
||||
|
||||
#define Jb &disassembler::Jb
|
||||
#define Jw &disassembler::Jw
|
||||
#define Jd &disassembler::Jd
|
||||
|
||||
#define XX 0
|
||||
|
||||
const struct BxDisasmOpcodeInfo_t
|
||||
#include "opcodes.inl"
|
||||
#include "dis_tables.inl"
|
||||
#include "opcodes.inc"
|
||||
#include "dis_tables_x87.inc"
|
||||
#include "dis_tables_sse.inc"
|
||||
#include "dis_tables_avx.inc"
|
||||
#include "dis_tables_xop.inc"
|
||||
#include "dis_tables.inc"
|
||||
|
||||
#undef XX
|
||||
|
||||
|
||||
+3282
File diff suppressed because it is too large
Load Diff
-5081
File diff suppressed because it is too large
Load Diff
+1478
File diff suppressed because it is too large
Load Diff
+1452
File diff suppressed because it is too large
Load Diff
+919
File diff suppressed because it is too large
Load Diff
+890
File diff suppressed because it is too large
Load Diff
Vendored
+226
-99
File diff suppressed because it is too large
Load Diff
Vendored
+1903
File diff suppressed because it is too large
Load Diff
Vendored
-1230
File diff suppressed because it is too large
Load Diff
Vendored
+696
File diff suppressed because it is too large
Load Diff
Vendored
-460
@@ -1,460 +0,0 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: resolve.cc,v 1.13 2006/08/11 17:22:43 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include "disasm.h"
|
||||
|
||||
void disassembler::decode_modrm(x86_insn *insn)
|
||||
{
|
||||
insn->modrm = fetch_byte();
|
||||
BX_DECODE_MODRM(insn->modrm, insn->mod, insn->nnn, insn->rm);
|
||||
// MOVs with CRx and DRx always use register ops and ignore the mod field.
|
||||
if ((insn->b1 & ~3) == 0x120) insn->mod = 3;
|
||||
insn->nnn |= insn->rex_r;
|
||||
|
||||
if (insn->mod == 3) {
|
||||
/* mod, reg, reg */
|
||||
insn->rm |= insn->rex_b;
|
||||
return;
|
||||
}
|
||||
|
||||
if (insn->as_64)
|
||||
{
|
||||
if (insn->rm != 4) { /* rm != 100b, no s-i-b byte */
|
||||
insn->rm |= insn->rex_b;
|
||||
// one byte modrm
|
||||
switch (insn->mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve64_mod0;
|
||||
if ((insn->rm & 7) == 5) /* no reg, 32-bit displacement */
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
case 1:
|
||||
/* reg, 8-bit displacement, sign extend */
|
||||
resolve_modrm = &disassembler::resolve64_mod1or2;
|
||||
insn->displacement.displ32 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
/* reg, 32-bit displacement */
|
||||
resolve_modrm = &disassembler::resolve64_mod1or2;
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
} /* switch (mod) */
|
||||
} /* if (rm != 4) */
|
||||
else { /* rm == 4, s-i-b byte follows */
|
||||
insn->sib = fetch_byte();
|
||||
BX_DECODE_SIB(insn->sib, insn->scale, insn->index, insn->base);
|
||||
insn->base |= insn->rex_b;
|
||||
insn->index |= insn->rex_x;
|
||||
|
||||
switch (insn->mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve64_mod0_rm4;
|
||||
if ((insn->base & 7) == 5)
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
case 1:
|
||||
resolve_modrm = &disassembler::resolve64_mod1or2_rm4;
|
||||
insn->displacement.displ32 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
resolve_modrm = &disassembler::resolve64_mod1or2_rm4;
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
}
|
||||
} /* s-i-b byte follows */
|
||||
}
|
||||
else
|
||||
{
|
||||
if (insn->as_32)
|
||||
{
|
||||
if (insn->rm != 4) { /* rm != 100b, no s-i-b byte */
|
||||
insn->rm |= insn->rex_b;
|
||||
// one byte modrm
|
||||
switch (insn->mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve32_mod0;
|
||||
if ((insn->rm & 7) == 5) /* no reg, 32-bit displacement */
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
case 1:
|
||||
/* reg, 8-bit displacement, sign extend */
|
||||
resolve_modrm = &disassembler::resolve32_mod1or2;
|
||||
insn->displacement.displ32 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
/* reg, 32-bit displacement */
|
||||
resolve_modrm = &disassembler::resolve32_mod1or2;
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
} /* switch (mod) */
|
||||
} /* if (rm != 4) */
|
||||
else { /* rm == 4, s-i-b byte follows */
|
||||
insn->sib = fetch_byte();
|
||||
BX_DECODE_SIB(insn->sib, insn->scale, insn->index, insn->base);
|
||||
insn->base |= insn->rex_b;
|
||||
insn->index |= insn->rex_x;
|
||||
|
||||
switch (insn->mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve32_mod0_rm4;
|
||||
if ((insn->base & 7) == 5)
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
case 1:
|
||||
resolve_modrm = &disassembler::resolve32_mod1or2_rm4;
|
||||
insn->displacement.displ32 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
resolve_modrm = &disassembler::resolve32_mod1or2_rm4;
|
||||
insn->displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
}
|
||||
} /* s-i-b byte follows */
|
||||
}
|
||||
else {
|
||||
assert(insn->rex_b == 0);
|
||||
assert(insn->rex_x == 0);
|
||||
assert(insn->rex_r == 0);
|
||||
/* 16 bit addressing modes. */
|
||||
switch (insn->mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve16_mod0;
|
||||
if(insn->rm == 6)
|
||||
insn->displacement.displ16 = fetch_word();
|
||||
break;
|
||||
case 1:
|
||||
/* reg, 8-bit displacement, sign extend */
|
||||
resolve_modrm = &disassembler::resolve16_mod1or2;
|
||||
insn->displacement.displ16 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
resolve_modrm = &disassembler::resolve16_mod1or2;
|
||||
insn->displacement.displ16 = fetch_word();
|
||||
break;
|
||||
} /* switch (mod) ... */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve16_mod0(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod00_rm16[insn->rm];
|
||||
|
||||
if(insn->rm == 6)
|
||||
print_memory_access16(mode, seg, NULL, insn->displacement.displ16);
|
||||
else
|
||||
print_memory_access16(mode, seg, index16[insn->rm], 0);
|
||||
}
|
||||
|
||||
void disassembler::resolve16_mod1or2(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod01or10_rm16[insn->rm];
|
||||
|
||||
print_memory_access16(mode, seg, index16[insn->rm], insn->displacement.displ16);
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod0(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = segment_name[DS_REG];
|
||||
|
||||
if ((insn->rm & 7) == 5) /* no reg, 32-bit displacement */
|
||||
print_memory_access(mode, seg, NULL, NULL, 0, insn->displacement.displ32);
|
||||
else
|
||||
print_memory_access(mode, seg, general_32bit_regname[insn->rm], NULL, 0, 0);
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod1or2(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod01or10_rm32[insn->rm];
|
||||
|
||||
print_memory_access(mode, seg,
|
||||
general_32bit_regname[insn->rm], NULL, 0, insn->displacement.displ32);
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod0_rm4(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg, *base = NULL, *index = NULL;
|
||||
Bit32u disp32 = 0;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod00_base32[insn->base];
|
||||
|
||||
if ((insn->base & 7) != 5)
|
||||
base = general_32bit_regname[insn->base];
|
||||
else
|
||||
disp32 = insn->displacement.displ32;
|
||||
|
||||
if (insn->index != 4)
|
||||
index = general_32bit_regname[insn->index];
|
||||
|
||||
print_memory_access(mode, seg, base, index, insn->scale, disp32);
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod1or2_rm4(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg, *index = NULL;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod01or10_base32[insn->base];
|
||||
|
||||
if (insn->index != 4)
|
||||
index = general_32bit_regname[insn->index];
|
||||
|
||||
print_memory_access(mode, seg,
|
||||
general_32bit_regname[insn->base], index, insn->scale, insn->displacement.displ32);
|
||||
}
|
||||
|
||||
void disassembler::resolve64_mod0(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg, *rip_regname;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = segment_name[DS_REG];
|
||||
|
||||
if (intel_mode) rip_regname = "rip";
|
||||
else rip_regname = "%rip";
|
||||
|
||||
if ((insn->rm & 7) == 5) /* no reg, 32-bit displacement */
|
||||
print_memory_access(mode, seg, rip_regname, NULL, 0, insn->displacement.displ32);
|
||||
else
|
||||
print_memory_access(mode, seg, general_64bit_regname[insn->rm], NULL, 0, 0);
|
||||
}
|
||||
|
||||
void disassembler::resolve64_mod1or2(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod01or10_rm32[insn->rm];
|
||||
|
||||
print_memory_access(mode, seg,
|
||||
general_64bit_regname[insn->rm], NULL, 0, insn->displacement.displ32);
|
||||
}
|
||||
|
||||
void disassembler::resolve64_mod0_rm4(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg, *base = NULL, *index = NULL;
|
||||
Bit32u disp32 = 0;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod00_base32[insn->base];
|
||||
|
||||
if ((insn->base & 7) != 5)
|
||||
base = general_64bit_regname[insn->base];
|
||||
else
|
||||
disp32 = insn->displacement.displ32;
|
||||
|
||||
if (insn->index != 4)
|
||||
index = general_64bit_regname[insn->index];
|
||||
|
||||
print_memory_access(mode, seg, base, index, insn->scale, disp32);
|
||||
}
|
||||
|
||||
void disassembler::resolve64_mod1or2_rm4(const x86_insn *insn, unsigned mode)
|
||||
{
|
||||
const char *seg, *index = NULL;
|
||||
|
||||
if (insn->is_seg_override())
|
||||
seg = segment_name[insn->seg_override];
|
||||
else
|
||||
seg = sreg_mod01or10_base32[insn->base];
|
||||
|
||||
if (insn->index != 4)
|
||||
index = general_64bit_regname[insn->index];
|
||||
|
||||
print_memory_access(mode, seg,
|
||||
general_64bit_regname[insn->base], index, insn->scale, insn->displacement.displ32);
|
||||
}
|
||||
|
||||
void disassembler::print_datasize(unsigned size)
|
||||
{
|
||||
if (!intel_mode) return;
|
||||
|
||||
switch(size)
|
||||
{
|
||||
case B_SIZE:
|
||||
dis_sprintf("byte ptr ");
|
||||
break;
|
||||
case W_SIZE:
|
||||
dis_sprintf("word ptr ");
|
||||
break;
|
||||
case D_SIZE:
|
||||
dis_sprintf("dword ptr ");
|
||||
break;
|
||||
case Q_SIZE:
|
||||
dis_sprintf("qword ptr ");
|
||||
break;
|
||||
case O_SIZE:
|
||||
dis_sprintf("dqword ptr ");
|
||||
break;
|
||||
case T_SIZE:
|
||||
dis_sprintf("tbyte ptr ");
|
||||
break;
|
||||
case P_SIZE:
|
||||
break;
|
||||
case X_SIZE:
|
||||
break;
|
||||
};
|
||||
}
|
||||
|
||||
void disassembler::print_memory_access16(int datasize,
|
||||
const char *seg, const char *index, Bit16u disp)
|
||||
{
|
||||
print_datasize(datasize);
|
||||
|
||||
if (intel_mode)
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s+0x%x]", seg, index, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s]", seg, index);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:0x%x(%s,1)", seg, (unsigned) disp, index);
|
||||
else
|
||||
dis_sprintf("%s:(%s,1)", seg, index);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::print_memory_access(int datasize,
|
||||
const char *seg, const char *base, const char *index, int scale, Bit32u disp)
|
||||
{
|
||||
print_datasize(datasize);
|
||||
|
||||
if (intel_mode)
|
||||
{
|
||||
if (base == NULL)
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (scale != 0)
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s*%d+0x%x]", seg, index, 1<<scale, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s*%d]", seg, index, 1<<scale);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s+0x%x]", seg, index, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s]", seg, index);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s+0x%x]", seg, base, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s]", seg, base);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (scale != 0)
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s+%s*%d+0x%x]", seg, base, index, 1<<scale, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s+%s*%d]", seg, base, index, 1<<scale);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:[%s+%s+0x%x]", seg, base, index, (unsigned) disp);
|
||||
else
|
||||
dis_sprintf("%s:[%s+%s]", seg, base, index);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (base == NULL)
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
dis_sprintf("%s:0x%x", seg, (unsigned) disp);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:0x%x(,%s,%d)", seg, (unsigned) disp, index, 1<<scale);
|
||||
else
|
||||
dis_sprintf("%s:(,%s,%d)", seg, index, 1<<scale);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (index == NULL)
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:0x%x(%s)", seg, (unsigned) disp, base);
|
||||
else
|
||||
dis_sprintf("%s:(%s)", seg, base);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (disp != 0)
|
||||
dis_sprintf("%s:0x%x(%s,%s,%d)", seg, (unsigned) disp, base, index, 1<<scale);
|
||||
else
|
||||
dis_sprintf("%s:(%s,%s,%d)", seg, base, index, 1<<scale);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user