Replace all bitfields which were only declared with "(un)signed" with their actual types. Let me know if I missed any. It would also be a good idea to test this commit in both x64 and x86.

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6232 8ced0084-cf51-0410-be5f-012b33b47a6e
2026-06-19 01:16:48 -07:00 · 2010-09-27 04:29:51 +00:00
parent 6cf51dbd66
commit 18be8ffa6e
14 changed files with 656 additions and 655 deletions
@@ -36,21 +36,21 @@ union UDSPControl
 	u16 Hex;
 	struct
 	{
-		unsigned DSPReset       : 1; // Write 1 to reset and waits for 0
-		unsigned DSPAssertInt   : 1;
-		unsigned DSPHalt        : 1;
+		u16 DSPReset       : 1; // Write 1 to reset and waits for 0
+		u16 DSPAssertInt   : 1;
+		u16 DSPHalt        : 1;

-		unsigned AI             : 1;
-		unsigned AI_mask        : 1;
-		unsigned ARAM           : 1;
-		unsigned ARAM_mask      : 1;
-		unsigned DSP            : 1;
-		unsigned DSP_mask       : 1;
+		u16 AI             : 1;
+		u16 AI_mask        : 1;
+		u16 ARAM           : 1;
+		u16 ARAM_mask      : 1;
+		u16 DSP            : 1;
+		u16 DSP_mask       : 1;

-		unsigned ARAM_DMAState  : 1; // DSPGetDMAStatus() uses this flag
-		unsigned DSPInitCode    : 1;
-		unsigned DSPInit        : 1; // DSPInit() writes to this flag
-		unsigned pad            : 4;
+		u16 ARAM_DMAState  : 1; // DSPGetDMAStatus() uses this flag
+		u16 DSPInitCode    : 1;
+		u16 DSPInit        : 1; // DSPInit() writes to this flag
+		u16 pad            : 4;
 	};
 	UDSPControl(u16 _Hex = 0) : Hex(_Hex) {}
 };
@@ -53,15 +53,15 @@ union AICR
 	AICR(u32 _hex) { hex = _hex;}
 	struct 
 	{
-		unsigned PSTAT		: 1;  // sample counter/playback enable
-		unsigned AIFR		: 1;  // AI Frequency (0=32khz 1=48khz)
-		unsigned AIINTMSK	: 1;  // 0=interrupt masked 1=interrupt enabled
-		unsigned AIINT		: 1;  // audio interrupt status
-		unsigned AIINTVLD	: 1;  // This bit controls whether AIINT is affected by the AIIT register 
+		u32 PSTAT		: 1;  // sample counter/playback enable
+		u32 AIFR		: 1;  // AI Frequency (0=32khz 1=48khz)
+		u32 AIINTMSK	: 1;  // 0=interrupt masked 1=interrupt enabled
+		u32 AIINT		: 1;  // audio interrupt status
+		u32 AIINTVLD	: 1;  // This bit controls whether AIINT is affected by the AIIT register 
                                  // matching AISLRCNT. Once set, AIINT will hold
-		unsigned SCRESET	: 1;  // write to reset counter
-        unsigned DACFR  	: 1;  // DAC Frequency (0=48khz 1=32khz)
-		unsigned			:25;
+		u32 SCRESET		: 1;  // write to reset counter
+        u32 DACFR		: 1;  // DAC Frequency (0=48khz 1=32khz)
+		u32				:25;
 	};
 	u32 hex;
 };
@@ -71,9 +71,9 @@ union AIVR
 {
 	struct
 	{
-		unsigned leftVolume		:  8;
-		unsigned rightVolume	:  8;
-		unsigned				: 16;
+		u32 leftVolume		:  8;
+		u32 rightVolume		:  8;
+		u32					: 16;
 	};
 	u32 hex;
 };
@@ -62,17 +62,17 @@ private:
 		//	Channels 0, 1, 2
 		//		Channels 0, 1 only
 		//			Channel 0 only
-			unsigned EXIINTMASK		: 1;
-			unsigned EXIINT			: 1;
-			unsigned TCINTMASK		: 1;
-			unsigned TCINT			: 1;
-			unsigned CLK			: 3;
-			unsigned CHIP_SELECT	: 3; // CS1 and CS2 are Channel 0 only
-				unsigned EXTINTMASK	: 1;
-				unsigned EXTINT		: 1;
-				unsigned EXT		: 1; // External Insertion Status (1: External EXI device present)
-					unsigned ROMDIS	: 1; // ROM Disable
-			unsigned				:18;
+			u32 EXIINTMASK		: 1;
+			u32 EXIINT			: 1;
+			u32 TCINTMASK		: 1;
+			u32 TCINT			: 1;
+			u32 CLK				: 3;
+			u32 CHIP_SELECT		: 3; // CS1 and CS2 are Channel 0 only
+				u32 EXTINTMASK	: 1;
+				u32 EXTINT		: 1;
+				u32 EXT			: 1; // External Insertion Status (1: External EXI device present)
+					u32 ROMDIS	: 1; // ROM Disable
+			u32					:18;
 		};
 		UEXI_STATUS() {Hex = 0;}
 		UEXI_STATUS(u32 _hex) {Hex = _hex;}
@@ -84,11 +84,11 @@ private:
 		u32 Hex;
 		struct
 		{
-			unsigned TSTART			: 1;
-			unsigned DMA			: 1;
-			unsigned RW				: 2;
-			unsigned TLEN			: 2;
-			unsigned				:26;
+			u32 TSTART		: 1;
+			u32 DMA			: 1;
+			u32 RW			: 2;
+			u32 TLEN		: 2;
+			u32				:26;
 		};
 	};

@@ -53,13 +53,13 @@ private:
 		u8 U8[2];
 		struct
 		{
-			unsigned			:8; // Unknown
-			unsigned button		:1; // 1: Button Pressed
-			unsigned unk1		:1; // 1 ? Overflow?
-			unsigned unk2		:1; // Unknown related to 0 and 15 values It seems
-			unsigned sRate		:2; // Sample Rate, 00-11025, 01-22050, 10-44100, 11-??
-			unsigned pLength	:2; // Period Length, 00-32, 01-64, 10-128, 11-???
-			unsigned sampling	:1; // If We Are Sampling or Not
+			u16				:8; // Unknown
+			u16 button		:1; // 1: Button Pressed
+			u16 unk1		:1; // 1 ? Overflow?
+			u16 unk2		:1; // Unknown related to 0 and 15 values It seems
+			u16 sRate		:2; // Sample Rate, 00-11025, 01-22050, 10-44100, 11-??
+			u16 pLength		:2; // Period Length, 00-32, 01-64, 10-128, 11-???
+			u16 sampling	:1; // If We Are Sampling or Not
 		};
 	};
 	int Index;
@@ -562,14 +562,15 @@ void WriteUnchecked_U32(const u32 _iValue, const u32 _Address)
 #define PTE2_WIMG(v) (((v)>>3)&0xf)
 #define PTE2_PP(v)   ((v)&3)

+// Hey! these duplicate a structure in Gekko.h
 union UPTE1
 {
 	struct 
 	{
-		unsigned API    : 6;
-		unsigned H      : 1;
-		unsigned VSID   : 24;
-		unsigned V      : 1;        
+		u32 API    : 6;
+		u32 H      : 1;
+		u32 VSID   : 24;
+		u32 V      : 1;        
 	};
 	u32 Hex;
 };
@@ -578,13 +579,13 @@ union UPTE2
 {
 	struct 
 	{
-		unsigned PP     : 2;
-		unsigned        : 1;
-		unsigned WIMG   : 4;
-		unsigned C      : 1;
-		unsigned R      : 1;
-		unsigned        : 3;
-		unsigned RPN    : 20;
+		u32 PP     : 2;
+		u32        : 1;
+		u32 WIMG   : 4;
+		u32 C      : 1;
+		u32 R      : 1;
+		u32        : 3;
+		u32 RPN    : 20;
 	};
 	u32 Hex;
 };
@@ -63,10 +63,10 @@ private:
 		u32 Hex;
 		struct  
 		{
-			unsigned Parameter1	:	8;
-			unsigned Parameter2	:	8;
-			unsigned Command	:	8;
-			unsigned			:	8;
+			u32 Parameter1	:	8;
+			u32 Parameter2	:	8;
+			u32 Command		:	8;
+			u32				:	8;
 		};
 		UCommand()				{Hex = 0;}
 		UCommand(u32 _iValue)	{Hex = _iValue;}		
@@ -114,9 +114,9 @@ union UVIVerticalTimingRegister
 	u16 Hex;
 	struct
 	{
-		unsigned EQU	:	 4; // Equalization pulse in half lines
-		unsigned ACV	:	10; // Active video in lines per field (seems always zero)
-		unsigned		:	 2;
+		u16 EQU	:	 4; // Equalization pulse in half lines
+		u16 ACV	:	10; // Active video in lines per field (seems always zero)
+		u16		:	 2;
 	};
 	UVIVerticalTimingRegister(u16 _hex) { Hex = _hex;}
 	UVIVerticalTimingRegister() { Hex = 0;}
@@ -127,14 +127,14 @@ union UVIDisplayControlRegister
 	u16 Hex;
 	struct
 	{
-		unsigned ENB	:	1; // Enables video timing generation and data request
-		unsigned RST	:	1; // Clears all data requests and puts VI into its idle state
-		unsigned NIN	:	1; // 0: Interlaced, 1: Non-Interlaced: top field drawn at field rate and bottom field is not displayed
-		unsigned DLR	:	1; // Selects 3D Display Mode
-		unsigned LE0	:	2; // Display Latch; 0: Off, 1: On for 1 field, 2: On for 2 fields, 3: Always on
-		unsigned LE1	:	2;
-		unsigned FMT	:	2; // 0: NTSC, 1: PAL, 2: MPAL, 3: Debug
-		unsigned		:	6;
+		u16 ENB	:	1; // Enables video timing generation and data request
+		u16 RST	:	1; // Clears all data requests and puts VI into its idle state
+		u16 NIN	:	1; // 0: Interlaced, 1: Non-Interlaced: top field drawn at field rate and bottom field is not displayed
+		u16 DLR	:	1; // Selects 3D Display Mode
+		u16 LE0	:	2; // Display Latch; 0: Off, 1: On for 1 field, 2: On for 2 fields, 3: Always on
+		u16 LE1	:	2;
+		u16 FMT	:	2; // 0: NTSC, 1: PAL, 2: MPAL, 3: Debug
+		u16		:	6;
 	};
 	UVIDisplayControlRegister(u16 _hex) { Hex = _hex;}
 	UVIDisplayControlRegister() { Hex = 0;}
@@ -146,12 +146,12 @@ union UVIHorizontalTiming0
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HLW		:	9; // Halfline Width (W*16 = Width (720))
-		unsigned			:	7;
-		unsigned HCE		:	7; // Horizontal Sync Start to Color Burst End
-		unsigned			:	1;
-		unsigned HCS		:	7; // Horizontal Sync Start to Color Burst Start
-		unsigned			:	1;
+		u32 HLW		:	9; // Halfline Width (W*16 = Width (720))
+		u32			:	7;
+		u32 HCE		:	7; // Horizontal Sync Start to Color Burst End
+		u32			:	1;
+		u32 HCS		:	7; // Horizontal Sync Start to Color Burst Start
+		u32			:	1;
 	};
 };

@@ -161,11 +161,11 @@ union UVIHorizontalTiming1
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HSY		:	 7; // Horizontal Sync Width
-		unsigned HBE640		:	 9; // Horizontal Sync Start to horizontal blank end
-		unsigned			:	 1;
-		unsigned HBS640		:	 9; // Half line to horizontal blanking start
-		unsigned			:	 6;
+		u32 HSY		:	 7; // Horizontal Sync Width
+		u32 HBE640	:	 9; // Horizontal Sync Start to horizontal blank end
+		u32			:	 1;
+		u32 HBS640	:	 9; // Half line to horizontal blanking start
+		u32			:	 6;
 	};
 };

@@ -176,10 +176,10 @@ union UVIVBlankTimingRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned PRB		:	10; // Pre-blanking in half lines
-		unsigned			:	 6;
-		unsigned PSB		:	10; // Post blanking in half lines
-		unsigned			:	 6;
+		u32 PRB		:	10; // Pre-blanking in half lines
+		u32			:	 6;
+		u32 PSB		:	10; // Post blanking in half lines
+		u32			:	 6;
 	};
 };

@@ -190,10 +190,10 @@ union UVIBurstBlankingRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned BS0		:	 5; // Field x start to burst blanking start in halflines
-		unsigned BE0		:	11; // Field x start to burst blanking end in halflines
-		unsigned BS2		:	 5; // Field x+2 start to burst blanking start in halflines
-		unsigned BE2		:	11; // Field x+2 start to burst blanking end in halflines
+		u32 BS0		:	 5; // Field x start to burst blanking start in halflines
+		u32 BE0		:	11; // Field x start to burst blanking end in halflines
+		u32 BS2		:	 5; // Field x+2 start to burst blanking start in halflines
+		u32 BE2		:	11; // Field x+2 start to burst blanking end in halflines
 	};
 };

@@ -204,11 +204,11 @@ union UVIFBInfoRegister
 	struct  
 	{
 		// TODO: mask out lower 9bits/align to 9bits???
-		unsigned FBB		:	24; // Base address of the framebuffer in external mem
+		u32 FBB		:	24; // Base address of the framebuffer in external mem
 		// POFF only seems to exist in the top reg. XOFF, unknown.
-		unsigned XOFF		:	 4; // Horizontal Offset of the left-most pixel within the first word of the fetched picture
-		unsigned POFF		:	 1; // Page offest: 1: fb address is (address>>5)
-		unsigned CLRPOFF	:	 3; // ? setting bit 31 clears POFF
+		u32 XOFF	:	 4; // Horizontal Offset of the left-most pixel within the first word of the fetched picture
+		u32 POFF	:	 1; // Page offest: 1: fb address is (address>>5)
+		u32 CLRPOFF	:	 3; // ? setting bit 31 clears POFF
 	};
 };

@@ -219,13 +219,13 @@ union UVIInterruptRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HCT		:	11; // Horizontal Position
-		unsigned			:	 5;
-		unsigned VCT		:	11; // Vertical Position
-		unsigned			:	 1;
-		unsigned IR_MASK	:	 1; // Interrupt Mask Bit
-		unsigned			:	 2;
-		unsigned IR_INT		:	 1; // Interrupt Status (1=Active, 0=Clear)
+		u32 HCT		:	11; // Horizontal Position
+		u32			:	 5;
+		u32 VCT		:	11; // Vertical Position
+		u32			:	 1;
+		u32 IR_MASK	:	 1; // Interrupt Mask Bit
+		u32			:	 2;
+		u32 IR_INT	:	 1; // Interrupt Status (1=Active, 0=Clear)
 	};
 };

@@ -235,11 +235,11 @@ union UVILatchRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HCT		:	11; // Horizontal Count
-		unsigned			:	 5;
-		unsigned VCT		:	11; // Vertical Count
-		unsigned			:	 4;
-		unsigned TRG		:	 1; // Trigger Flag
+		u32 HCT		:	11; // Horizontal Count
+		u32			:	 5;
+		u32 VCT		:	11; // Vertical Count
+		u32			:	 4;
+		u32 TRG		:	 1; // Trigger Flag
 	};
 };

@@ -248,8 +248,8 @@ union UVIHorizontalStepping
 	u16 Hex;
 	struct
 	{
-		unsigned FbSteps	:	 8;
-		unsigned FieldSteps	:	 8;
+		u16 FbSteps		:	 8;
+		u16 FieldSteps	:	 8;
 	};
 };

@@ -258,10 +258,10 @@ union UVIHorizontalScaling
 	u16 Hex;
 	struct
 	{
-		unsigned STP		:	9; // Horizontal stepping size (U1.8 Scaler Value) (0x160 Works for 320)
-		unsigned			:	3;
-		unsigned HS_EN		:	1; // Enable Horizontal Scaling
-		unsigned			:	3;
+		u16 STP		:	9; // Horizontal stepping size (U1.8 Scaler Value) (0x160 Works for 320)
+		u16			:	3;
+		u16 HS_EN	:	1; // Enable Horizontal Scaling
+		u16			:	3;
 	};
 	UVIHorizontalScaling(u16 _hex) { Hex = _hex;}
 	UVIHorizontalScaling() { Hex = 0;}
@@ -274,10 +274,10 @@ union UVIFilterCoefTable3
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned Tap0		:	10;
-		unsigned Tap1		:	10;
-		unsigned Tap2		:	10;
-		unsigned			:	 2;
+		u32 Tap0	:	10;
+		u32 Tap1	:	10;
+		u32 Tap2	:	10;
+		u32			:	 2;
 	};
 };

@@ -288,10 +288,10 @@ union UVIFilterCoefTable4
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned Tap0		:	 8;
-		unsigned Tap1		:	 8;
-		unsigned Tap2		:	 8;
-		unsigned Tap3		:	 8;
+		u32 Tap0	:	 8;
+		u32 Tap1	:	 8;
+		u32 Tap2	:	 8;
+		u32 Tap3	:	 8;
 	};
 };

@@ -308,10 +308,10 @@ union UVIBorderBlankRegister
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned HBE656		:	10; // Border Horizontal Blank End
-		unsigned			:	11;
-		unsigned HBS656		:	10; // Border Horizontal Blank start
-		unsigned BRDR_EN	:	 1; // Border Enable
+		u32 HBE656	:	10; // Border Horizontal Blank End
+		u32			:	11;
+		u32 HBS656	:	10; // Border Horizontal Blank start
+		u32 BRDR_EN	:	 1; // Border Enable
 	};
 };

@@ -212,11 +212,11 @@ union TMatrixIndexA
 {
    struct
    {
-        unsigned PosNormalMtxIdx : 6;
-        unsigned Tex0MtxIdx : 6;
-        unsigned Tex1MtxIdx : 6;
-        unsigned Tex2MtxIdx : 6;
-        unsigned Tex3MtxIdx : 6;
+        u32 PosNormalMtxIdx : 6;
+        u32 Tex0MtxIdx : 6;
+        u32 Tex1MtxIdx : 6;
+        u32 Tex2MtxIdx : 6;
+        u32 Tex3MtxIdx : 6;
    };
    struct
    {
@@ -229,10 +229,10 @@ union TMatrixIndexB
 {
    struct
    {
-        unsigned Tex4MtxIdx : 6;
-        unsigned Tex5MtxIdx : 6;
-        unsigned Tex6MtxIdx : 6;
-        unsigned Tex7MtxIdx : 6;
+        u32 Tex4MtxIdx : 6;
+        u32 Tex5MtxIdx : 6;
+        u32 Tex6MtxIdx : 6;
+        u32 Tex7MtxIdx : 6;
    };
    struct
    {
@@ -89,12 +89,12 @@ union UCPStatusReg
 {
 	struct
 	{
-		unsigned OverflowHiWatermark	:	1;
-		unsigned UnderflowLoWatermark	:	1;
-		unsigned ReadIdle				:	1;
-		unsigned CommandIdle			:	1;
-		unsigned Breakpoint				:	1;
-		unsigned						:	11;
+		u16 OverflowHiWatermark	:	1;
+		u16 UnderflowLoWatermark:	1;
+		u16 ReadIdle			:	1;
+		u16 CommandIdle			:	1;
+		u16 Breakpoint			:	1;
+		u16						:	11;
 	};
 	u16 Hex;
 	UCPStatusReg() {Hex = 0; }
@@ -106,13 +106,13 @@ union UCPCtrlReg
 {
 	struct
 	{
-		unsigned GPReadEnable			:	1;
-		unsigned BPEnable				:	1;
-		unsigned FifoOverflowIntEnable	:	1;
-		unsigned FifoUnderflowIntEnable	:	1;
-		unsigned GPLinkEnable			:	1;
-		unsigned BPInt					:	1;
-		unsigned						:	10;
+		u16 GPReadEnable			:	1;
+		u16 BPEnable				:	1;
+		u16 FifoOverflowIntEnable	:	1;
+		u16 FifoUnderflowIntEnable	:	1;
+		u16 GPLinkEnable			:	1;
+		u16 BPInt					:	1;
+		u16							:	10;
 	};
 	u16 Hex;
 	UCPCtrlReg() {Hex = 0; }
@@ -124,10 +124,10 @@ union UCPClearReg
 {
 	struct
 	{
-		unsigned ClearFifoOverflow		:	1;
-		unsigned ClearFifoUnderflow		:	1;
-		unsigned ClearMetrices			:	1;
-		unsigned						:	13;
+		u16 ClearFifoOverflow		:	1;
+		u16 ClearFifoUnderflow		:	1;
+		u16 ClearMetrices			:	1;
+		u16							:	13;
 	};
 	u16 Hex;
 	UCPClearReg() {Hex = 0; }
@@ -109,13 +109,13 @@ union LitChannel
 {
    struct
    {
-        unsigned matsource      : 1;
-        unsigned enablelighting : 1;
-        unsigned lightMask0_3   : 4;
-        unsigned ambsource      : 1;
-        unsigned diffusefunc    : 2; // LIGHTDIF_X
-        unsigned attnfunc       : 2; // LIGHTATTN_X
-        unsigned lightMask4_7   : 4;
+        u32 matsource      : 1;
+        u32 enablelighting : 1;
+        u32 lightMask0_3   : 4;
+        u32 ambsource      : 1;
+        u32 diffusefunc    : 2; // LIGHTDIF_X
+        u32 attnfunc       : 2; // LIGHTATTN_X
+        u32 lightMask4_7   : 4;
    };
    struct
    {
@@ -139,10 +139,10 @@ union INVTXSPEC
 {
    struct
    {
-        unsigned numcolors : 2;
-        unsigned numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
-        unsigned numtextures : 4;
-        unsigned unused : 24;
+        u32 numcolors : 2;
+        u32 numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
+        u32 numtextures : 4;
+        u32 unused : 24;
    };
    u32 hex;
 };
@@ -151,13 +151,13 @@ union TexMtxInfo
 {
    struct 
    {
-        unsigned unknown : 1;
-        unsigned projection : 1; // XF_TEXPROJ_X
-        unsigned inputform : 2; // XF_TEXINPUT_X
-        unsigned texgentype : 3; // XF_TEXGEN_X
-        unsigned sourcerow : 5; // XF_SRCGEOM_X
-        unsigned embosssourceshift : 3; // what generated texcoord to use
-        unsigned embosslightshift : 3; // light index that is used
+        u32 unknown : 1;
+        u32 projection : 1; // XF_TEXPROJ_X
+        u32 inputform : 2; // XF_TEXINPUT_X
+        u32 texgentype : 3; // XF_TEXGEN_X
+        u32 sourcerow : 5; // XF_SRCGEOM_X
+        u32 embosssourceshift : 3; // what generated texcoord to use
+        u32 embosslightshift : 3; // light index that is used
    };
    u32 hex;
 };
@@ -166,9 +166,9 @@ union PostMtxInfo
 {
    struct 
    {
-        unsigned index : 6; // base row of dual transform matrix
-        unsigned unused : 2;
-        unsigned normalize : 1; // normalize before send operation
+        u32 index : 6; // base row of dual transform matrix
+        u32 unused : 2;
+        u32 normalize : 1; // normalize before send operation
    };
    u32 hex;
 };
@@ -74,12 +74,12 @@ namespace CommandProcessor
    {
 	    struct
 	    {
-		    unsigned OverflowHiWatermark	:	1;
-		    unsigned UnderflowLoWatermark	:	1;
-		    unsigned ReadIdle				:	1; // done reading
-		    unsigned CommandIdle			:	1; // done processing commands
-		    unsigned Breakpoint				:	1;
-		    unsigned						:	11;
+		    u16 OverflowHiWatermark	:	1;
+		    u16 UnderflowLoWatermark:	1;
+		    u16 ReadIdle			:	1; // done reading
+		    u16 CommandIdle			:	1; // done processing commands
+		    u16 Breakpoint			:	1;
+		    u16						:	11;
 	    };
 	    u16 Hex;
 	    UCPStatusReg() {Hex = 0; }
@@ -91,13 +91,13 @@ namespace CommandProcessor
    {
 	    struct
 	    {
-		    unsigned GPReadEnable			:	1;
-		    unsigned BPEnable           	:	1;
-		    unsigned FifoOverflowIntEnable	:	1;
-		    unsigned FifoUnderflowIntEnable	:	1;
-		    unsigned GPLinkEnable			:	1;
-		    unsigned BreakPointIntEnable	:	1;
-		    unsigned						:	10;
+		    u16 GPReadEnable			:	1;
+		    u16 BPEnable           		:	1;
+		    u16 FifoOverflowIntEnable	:	1;
+		    u16 FifoUnderflowIntEnable	:	1;
+		    u16 GPLinkEnable			:	1;
+		    u16 BreakPointIntEnable		:	1;
+		    u16							:	10;
 	    };
 	    u16 Hex;
 	    UCPCtrlReg() {Hex = 0; }
@@ -109,10 +109,10 @@ namespace CommandProcessor
    {
 	    struct
 	    {
-		    unsigned ClearFifoOverflow		:	1;
-		    unsigned ClearFifoUnderflow		:	1;
-		    unsigned ClearMetrices			:	1;
-		    unsigned						:	13;
+		    u16 ClearFifoOverflow		:	1;
+		    u16 ClearFifoUnderflow		:	1;
+		    u16 ClearMetrices			:	1;
+		    u16							:	13;
 	    };
 	    u16 Hex;
 	    UCPClearReg() {Hex = 0; }
@@ -89,14 +89,14 @@ union LitChannel
 {
    struct
    {
-        unsigned matsource      : 1;
-        unsigned enablelighting : 1;
-        unsigned lightMask0_3   : 4;
-        unsigned ambsource      : 1;
-        unsigned diffusefunc    : 2; // LIGHTDIF_X
-        unsigned attnfunc       : 2; // LIGHTATTN_X
-        unsigned lightMask4_7   : 4;
-        unsigned unused         : 17;
+        u32 matsource      : 1;
+        u32 enablelighting : 1;
+        u32 lightMask0_3   : 4;
+        u32 ambsource      : 1;
+        u32 diffusefunc    : 2; // LIGHTDIF_X
+        u32 attnfunc       : 2; // LIGHTATTN_X
+        u32 lightMask4_7   : 4;
+        u32 unused         : 17;
    };
    u32 hex;
    unsigned int GetFullLightMask() const
@@ -109,10 +109,10 @@ union INVTXSPEC
 {
    struct
    {
-        unsigned numcolors : 2;
-        unsigned numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
-        unsigned numtextures : 4;
-        unsigned unused : 24;
+        u32 numcolors : 2;
+        u32 numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
+        u32 numtextures : 4;
+        u32 unused : 24;
    };
    u32 hex;
 };
@@ -121,11 +121,11 @@ union TXFMatrixIndexA
 {
    struct
    {
-        unsigned PosNormalMtxIdx : 6;
-        unsigned Tex0MtxIdx : 6;
-        unsigned Tex1MtxIdx : 6;
-        unsigned Tex2MtxIdx : 6;
-        unsigned Tex3MtxIdx : 6;
+        u32 PosNormalMtxIdx : 6;
+        u32 Tex0MtxIdx : 6;
+        u32 Tex1MtxIdx : 6;
+        u32 Tex2MtxIdx : 6;
+        u32 Tex3MtxIdx : 6;
    };
    struct
    {
@@ -138,10 +138,10 @@ union TXFMatrixIndexB
 {
    struct
    {
-        unsigned Tex4MtxIdx : 6;
-        unsigned Tex5MtxIdx : 6;
-        unsigned Tex6MtxIdx : 6;
-        unsigned Tex7MtxIdx : 6;
+        u32 Tex4MtxIdx : 6;
+        u32 Tex5MtxIdx : 6;
+        u32 Tex6MtxIdx : 6;
+        u32 Tex7MtxIdx : 6;
    };
    struct
    {
@@ -164,13 +164,13 @@ union TexMtxInfo
 {
    struct 
    {
-        unsigned unknown : 1;
-        unsigned projection : 1; // XF_TEXPROJ_X
-        unsigned inputform : 2; // XF_TEXINPUT_X
-        unsigned texgentype : 3; // XF_TEXGEN_X
-        unsigned sourcerow : 5; // XF_SRCGEOM_X
-        unsigned embosssourceshift : 3; // what generated texcoord to use
-        unsigned embosslightshift : 3; // light index that is used
+        u32 unknown : 1;
+        u32 projection : 1; // XF_TEXPROJ_X
+        u32 inputform : 2; // XF_TEXINPUT_X
+        u32 texgentype : 3; // XF_TEXGEN_X
+        u32 sourcerow : 5; // XF_SRCGEOM_X
+        u32 embosssourceshift : 3; // what generated texcoord to use
+        u32 embosslightshift : 3; // light index that is used
    };
    u32 hex;
 };
@@ -179,9 +179,9 @@ union PostMtxInfo
 {
    struct 
    {
-        unsigned index : 6; // base row of dual transform matrix
-        unsigned unused : 2;
-        unsigned normalize : 1; // normalize before send operation
+        u32 index : 6; // base row of dual transform matrix
+        u32 unused : 2;
+        u32 normalize : 1; // normalize before send operation
    };
    u32 hex;
 };