mirror of
https://github.com/izzy2lost/WeeU.git
synced 2026-07-06 00:19:59 -07:00
Merge branch 'main' into android
This commit is contained in:
Vendored
+1
-1
Submodule dependencies/xbyak_aarch64 updated: e61bad546f...904b892345
@@ -558,6 +558,14 @@ if(ANDROID)
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endif()
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endif()
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if(CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(AARCH64)")
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target_sources(CemuCafe PRIVATE
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HW/Espresso/Recompiler/BackendAArch64/BackendAArch64.cpp
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HW/Espresso/Recompiler/BackendAArch64/BackendAArch64.h
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)
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target_link_libraries(CemuCafe PRIVATE xbyak_aarch64)
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endif()
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set_property(TARGET CemuCafe PROPERTY MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>")
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target_include_directories(CemuCafe PUBLIC "../")
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@@ -152,7 +152,6 @@ struct AArch64GenContext_t : CodeGenerator
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void jump(IMLSegment* imlSegment);
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void conditionalJumpCycleCheck(IMLSegment* imlSegment);
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void gqr_generateScaleCode(const VReg& resReg, const VReg& dataReg, bool isLoad, bool scalePS1, const IMLReg& registerGQR);
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static constexpr size_t MAX_JUMP_INSTR_COUNT = 2;
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std::list<std::pair<size_t, JumpInfo>> jumps;
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void prepareJump(JumpInfo&& jumpInfo)
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@@ -282,16 +281,41 @@ struct AArch64GenContext_t : CodeGenerator
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}
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};
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template<typename T>
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template<std::derived_from<VRegSc> T>
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T fpReg(const IMLReg& imlReg)
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{
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return T(imlReg.GetRegID() - IMLArchAArch64::PHYSREG_FPR_BASE);
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cemu_assert_debug(imlReg.GetRegFormat() == IMLRegFormat::F64);
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auto regId = imlReg.GetRegID();
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cemu_assert_debug(regId >= IMLArchAArch64::PHYSREG_FPR_BASE && regId < IMLArchAArch64::PHYSREG_FPR_BASE + IMLArchAArch64::PHYSREG_FPR_COUNT);
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return T(regId - IMLArchAArch64::PHYSREG_FPR_BASE);
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}
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template<typename T>
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template<std::derived_from<RReg> T>
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T gpReg(const IMLReg& imlReg)
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{
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return T(imlReg.GetRegID() - IMLArchAArch64::PHYSREG_GPR_BASE);
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auto regFormat = imlReg.GetRegFormat();
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if (std::is_same_v<T, WReg>)
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cemu_assert_debug(regFormat == IMLRegFormat::I32);
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else if (std::is_same_v<T, XReg>)
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cemu_assert_debug(regFormat == IMLRegFormat::I64);
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else
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cemu_assert_unimplemented();
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auto regId = imlReg.GetRegID();
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cemu_assert_debug(regId >= IMLArchAArch64::PHYSREG_GPR_BASE && regId < IMLArchAArch64::PHYSREG_GPR_BASE + IMLArchAArch64::PHYSREG_GPR_COUNT);
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return T(regId - IMLArchAArch64::PHYSREG_GPR_BASE);
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}
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template<std::derived_from<VRegSc> To, std::derived_from<VRegSc> From>
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To aliasAs(const From& reg)
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{
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return To(reg.getIdx());
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}
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template<std::derived_from<RReg> To, std::derived_from<RReg> From>
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To aliasAs(const From& reg)
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{
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return To(reg.getIdx());
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}
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AArch64GenContext_t::AArch64GenContext_t(Allocator* allocator)
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@@ -314,7 +338,7 @@ constexpr bool isAdrImmValidFPR(sint32 imm, uint32 bits)
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constexpr bool isAdrImmValidGPR(sint32 imm, uint32 bits = 32)
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{
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uint32 size = std::countr_zero(bits / 8u);
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int32_t times = 1 << size;
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sint32 times = 1 << size;
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return (0 <= imm && imm <= 4095 * times) && ((uint64)imm & ones(size)) == 0;
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}
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@@ -357,7 +381,8 @@ void AArch64GenContext_t::r_name(IMLInstruction* imlInstruction)
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if (imlInstruction->op_r_name.regR.GetBaseFormat() == IMLRegFormat::I64)
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{
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WReg regR = gpReg<WReg>(imlInstruction->op_r_name.regR);
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XReg regRXReg = gpReg<XReg>(imlInstruction->op_r_name.regR);
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WReg regR = aliasAs<WReg>(regRXReg);
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if (name >= PPCREC_NAME_R0 && name < PPCREC_NAME_R0 + 32)
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{
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ldr(regR, AdrUimm(HCPU_REG, offsetof(PPCInterpreter_t, gpr) + sizeof(uint32) * (name - PPCREC_NAME_R0)));
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@@ -437,7 +462,8 @@ void AArch64GenContext_t::name_r(IMLInstruction* imlInstruction)
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if (imlInstruction->op_r_name.regR.GetBaseFormat() == IMLRegFormat::I64)
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{
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auto regR = gpReg<WReg>(imlInstruction->op_r_name.regR);
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XReg regRXReg = gpReg<XReg>(imlInstruction->op_r_name.regR);
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WReg regR = aliasAs<WReg>(regRXReg);
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if (name >= PPCREC_NAME_R0 && name < PPCREC_NAME_R0 + 32)
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{
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str(regR, AdrUimm(HCPU_REG, offsetof(PPCInterpreter_t, gpr) + sizeof(uint32) * (name - PPCREC_NAME_R0)));
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@@ -658,7 +684,7 @@ bool AArch64GenContext_t::r_r_s32_carry(IMLInstruction* imlInstruction)
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bool AArch64GenContext_t::r_r_r(IMLInstruction* imlInstruction)
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{
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WReg regResult = gpReg<WReg>(imlInstruction->op_r_r_r.regR);
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XReg reg64Result = gpReg<XReg>(imlInstruction->op_r_r_r.regR);
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XReg reg64Result = aliasAs<XReg>(regResult);
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WReg regOperand1 = gpReg<WReg>(imlInstruction->op_r_r_r.regA);
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WReg regOperand2 = gpReg<WReg>(imlInstruction->op_r_r_r.regB);
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@@ -860,12 +886,12 @@ bool AArch64GenContext_t::macro(IMLInstruction* imlInstruction)
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{
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if (imlInstruction->operation == PPCREC_IML_MACRO_B_TO_REG)
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{
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XReg branchDstReg = gpReg<XReg>(imlInstruction->op_macro.paramReg);
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WReg branchDstReg = gpReg<WReg>(imlInstruction->op_macro.paramReg);
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mov(TEMP_GPR1.XReg, offsetof(PPCRecompilerInstanceData_t, ppcRecompilerDirectJumpTable));
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add(TEMP_GPR1.XReg, TEMP_GPR1.XReg, branchDstReg, ShMod::LSL, 1);
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ldr(TEMP_GPR1.XReg, AdrReg(PPC_REC_INSTANCE_REG, TEMP_GPR1.XReg));
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mov(LR.XReg, branchDstReg);
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mov(TEMP_GPR1.WReg, offsetof(PPCRecompilerInstanceData_t, ppcRecompilerDirectJumpTable));
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add(TEMP_GPR1.WReg, TEMP_GPR1.WReg, branchDstReg, ShMod::LSL, 1);
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ldr(TEMP_GPR1.XReg, AdrExt(PPC_REC_INSTANCE_REG, TEMP_GPR1.WReg, ExtMod::UXTW));
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mov(LR.WReg, branchDstReg);
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br(TEMP_GPR1.XReg);
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return true;
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}
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@@ -1391,9 +1417,9 @@ Cond ImlFPCondToArm64Cond(IMLCondition cond)
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void AArch64GenContext_t::fpr_compare(IMLInstruction* imlInstruction)
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{
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auto regR = gpReg<XReg>(imlInstruction->op_fpr_compare.regR);
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auto regA = fpReg<DReg>(imlInstruction->op_fpr_compare.regA);
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auto regB = fpReg<DReg>(imlInstruction->op_fpr_compare.regB);
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WReg regR = gpReg<WReg>(imlInstruction->op_fpr_compare.regR);
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DReg regA = fpReg<DReg>(imlInstruction->op_fpr_compare.regA);
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DReg regB = fpReg<DReg>(imlInstruction->op_fpr_compare.regB);
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auto cond = ImlFPCondToArm64Cond(imlInstruction->op_fpr_compare.cond);
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fcmp(regA, regB);
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cset(regR, cond);
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@@ -1697,10 +1697,10 @@ void VulkanRenderer::Initialize()
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void VulkanRenderer::Shutdown()
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{
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DeleteFontTextures();
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Renderer::Shutdown();
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SubmitCommandBuffer();
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WaitDeviceIdle();
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DeleteFontTextures();
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Renderer::Shutdown();
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if (m_imguiRenderPass != VK_NULL_HANDLE)
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{
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vkDestroyRenderPass(m_logicalDevice, m_imguiRenderPass, nullptr);
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