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https://github.com/izzy2lost/WeeU.git
synced 2026-07-06 00:19:59 -07:00
Update xbyak dependency & reimplement some instructions
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SSimco
File diff suppressed because it is too large
Load Diff
@@ -305,11 +305,11 @@ void PPCRecompiler_NativeRegisterAllocatorPass(ppcImlGenContext_t& ppcImlGenCont
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fprPhysPool.SetAvailable(IMLArchX86::PHYSREG_FPR_BASE + 14);
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#elif defined(__aarch64__)
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auto& gprPhysPool = raParam.GetPhysRegPool(IMLRegFormat::I64);
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for (int i = 0; i < 12; i++)
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for (int i = 0; i <= 24; i++)
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gprPhysPool.SetAvailable(i);
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auto& fprPhysPool = raParam.GetPhysRegPool(IMLRegFormat::F64);
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for (int i = 0; i < 15; i++)
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for (int i = 0; i <= 28; i++)
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fprPhysPool.SetAvailable(i);
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#endif
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@@ -43,7 +43,8 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "(x86)|(X86)|(amd64)|(AMD64)")
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endif()
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elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(AARCH64)")
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add_library(CemuAsm stub.cpp)
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enable_language(C ASM)
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add_library(CemuAsm aarch64util.s)
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else()
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message(STATUS "CemuAsm - Unsupported arch: ${CMAKE_SYSTEM_PROCESSOR}")
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endif()
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@@ -0,0 +1,198 @@
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.section .text
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.global recompiler_fres
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asmFresLookupTable:
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.word 0x07ff800, 0x03e1
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.word 0x0783800, 0x03a7
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.word 0x070ea00, 0x0371
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.word 0x06a0800, 0x0340
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.word 0x0638800, 0x0313
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.word 0x05d6200, 0x02ea
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.word 0x0579000, 0x02c4
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.word 0x0520800, 0x02a0
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.word 0x04cc800, 0x027f
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.word 0x047ca00, 0x0261
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.word 0x0430800, 0x0245
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.word 0x03e8000, 0x022a
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.word 0x03a2c00, 0x0212
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.word 0x0360800, 0x01fb
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.word 0x0321400, 0x01e5
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.word 0x02e4a00, 0x01d1
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.word 0x02aa800, 0x01be
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.word 0x0272c00, 0x01ac
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.word 0x023d600, 0x019b
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.word 0x0209e00, 0x018b
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.word 0x01d8800, 0x017c
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.word 0x01a9000, 0x016e
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.word 0x017ae00, 0x015b
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.word 0x014f800, 0x015b
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.word 0x0124400, 0x0143
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.word 0x00fbe00, 0x0143
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.word 0x00d3800, 0x012d
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.word 0x00ade00, 0x012d
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.word 0x0088400, 0x011a
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.word 0x0065000, 0x011a
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.word 0x0041c00, 0x0108
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.word 0x0020c00, 0x0106
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recompiler_fres:
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sub sp, sp, #48
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stp x0, x1, [sp]
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fmov x0, d31
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ubfx x1, x0, #52, #11
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cmp w1, #2047
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b.eq fres_nan_or_inf
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cbnz w1, fres_lookup
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orr x0, x0, #0x7ff0000000000000
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fmov d31, x0
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ldp x0, x1, [sp]
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add sp, sp, #48
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ret
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fres_nan_or_inf:
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stp q0, q1, [sp, #16]
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movi v0.2d, #0xffffffffffffffff
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movi d1, #0000000000000000
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tst x0, #0xfffffffffffff
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fneg v0.2d, v0.2d
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bsl v0.16b, v1.16b, v0.16b
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fcsel d31, d1, d31, eq
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ldp q0, q1, [sp, #16]
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add sp, sp, #48
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ret
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fres_lookup :
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stp x2, x3, [sp, #16]
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stp x4, x5, [sp, #32]
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ubfx x2, x0, #47, #5
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adrp x3, asmFresLookupTable
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add x3, x3, :lo12:asmFresLookupTable
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ubfx x4, x0, #37, #10
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mov w5, #1
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and x0, x0, #0x8000000000000000
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add x2, x3, x2, lsl #3
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ldp w2, w3, [x2]
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madd w3, w3, w4, w5
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mov w4, #2045
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sub w1, w4, w1
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orr x0, x0, x1, lsl #52
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sub w2, w2, w3, lsr #1
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add x0, x0, x2, lsl #29
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fmov d31, x0
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ldp x2, x3, [sp, #16]
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ldp x4, x5, [sp, #32]
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ldp x0, x1, [sp]
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add sp, sp, #48
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ret
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asmFrsqrteLookupTable:
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.word 0x01a7e800, 0x0568
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.word 0x017cb800, 0x04f3
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.word 0x01552800, 0x048d
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.word 0x0130c000, 0x0435
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.word 0x010f2000, 0x03e7
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.word 0x0eff000, 0x03a2
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.word 0x0d2e000, 0x0365
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.word 0x0b7c000, 0x032e
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.word 0x09e5000, 0x02fc
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.word 0x0867000, 0x02d0
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.word 0x06ff000, 0x02a8
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.word 0x05ab800, 0x0283
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.word 0x046a000, 0x0261
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.word 0x0339800, 0x0243
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.word 0x0218800, 0x0226
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.word 0x0105800, 0x020b
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.word 0x03ffa000, 0x07a4
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.word 0x03c29000, 0x0700
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.word 0x038aa000, 0x0670
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.word 0x03572000, 0x05f2
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.word 0x03279000, 0x0584
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.word 0x02fb7000, 0x0524
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.word 0x02d26000, 0x04cc
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.word 0x02ac0000, 0x047e
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.word 0x02881000, 0x043a
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.word 0x02665000, 0x03fa
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.word 0x02468000, 0x03c2
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.word 0x02287000, 0x038e
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.word 0x020c1000, 0x035e
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.word 0x01f12000, 0x0332
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.word 0x01d79000, 0x030a
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.word 0x01bf4000, 0x02e6
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.global recompiler_frsqrte
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recompiler_frsqrte:
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sub sp, sp, #48
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stp x0, x1, [sp]
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fcmp d31, #0.0
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fmov x0, d31
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b.ne frsqrte_not_zero
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// result is inf or -inf
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orr x0, x0, #0x7ff0000000000000
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fmov d31, x0
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ldp x0, x1, [sp]
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add sp, sp, #48
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ret
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frsqrte_not_zero:
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stp x2, x3, [sp, #16]
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lsr x1, x0, #52
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mov w2, #2047
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bics wzr, w2, w1
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// branch to frsqrte_lookup if not NaN or Inf
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b.ne frsqrte_lookup
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// branch to frsqrte_inf if not NaN
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tst x0, #0xfffffffffffff
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b.eq frsqrte_inf
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// result is NaN with same sign and same mantissa
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #16]
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add sp, sp, #48
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ret
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frsqrte_inf:
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// if -INF result is +NaN (#9221120237041090560)
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// if +INF result is +0.0
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str q0, [sp, #32]
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movi d31, #0000000000000000
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mov x1, #9221120237041090560
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cmp x0, #0
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fmov d0, x1
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fcsel d31, d0, d31, lt
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #16]
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ldr q0, [sp, #32]
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add sp, sp, #48
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ret
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frsqrte_lookup:
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tbnz x0, #63, frsqrte_negative_input
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ubfx x2, x0, #48, #5
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adrp x3, asmFrsqrteLookupTable
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add x3, x3, :lo12:asmFrsqrteLookupTable
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ubfx x0, x0, #37, #11
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add x2, x3, x2, lsl #3
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ldp w2, w3, [x2]
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msub w0, w3, w0, w2
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mov w2, #7171
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add w1, w1, w2
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mov w2, #1023
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sub w1, w2, w1, lsr #1
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sbfiz x0, x0, #26, #32
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add x0, x0, x1, lsl #52
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fmov d31, x0
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #16]
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add sp, sp, #48
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ret
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frsqrte_negative_input:
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mov x0, #9221120237041090560
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fmov d31, x0
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #16]
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add sp, sp, #48
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ret
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+8
-14
@@ -1,20 +1,14 @@
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#pragma once
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#if defined(ARCH_X86_64)
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extern "C" void recompiler_fres();
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extern "C" void recompiler_frsqrte();
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// #if defined(ARCH_X86_64)
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#else
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// stubbed on non-x86 for now
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static void recompiler_fres()
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{
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cemu_assert_unimplemented();
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}
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static void recompiler_frsqrte()
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{
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cemu_assert_unimplemented();
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}
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#endif
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// #else
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// // stubbed on non-x86 for now
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// static void recompiler_frsqrte()
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// {
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// cemu_assert_unimplemented();
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// }
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// #endif
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