mirror of
https://github.com/izzy2lost/Starship.git
synced 2026-07-05 15:19:42 -07:00
clean up leftover files from the decomp
This commit is contained in:
Sonic Dreamcaster
-10
@@ -1,10 +0,0 @@
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Checks: '-*,readability-braces-around-statements,readability-inconsistent-declaration-parameter-name'
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WarningsAsErrors: ''
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HeaderFilterRegex: '(src|include)\/.*\.h$'
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FormatStyle: 'file'
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CheckOptions:
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# Require argument names to match exactly (instead of allowing a name to be a prefix/suffix of another)
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# Note: 'true' is expected by clang-tidy 12+ but '1' is used for compatibility with older versions
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- key: readability-inconsistent-declaration-parameter-name.Strict
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value: 1
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@@ -1,9 +0,0 @@
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#!/usr/bin/env python3
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def apply(config, args):
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config['baseimg'] = 'baserom.us.rev1.z64'
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config['myimg'] = 'build/starfox64.us.rev1.uncompressed.z64'
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config['mapfile'] = 'build/starfox64.us.rev1.map'
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config['source_directories'] = ['./src','./include']
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config['objdump_flags'] = ['-M','reg-names=32']
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config['makeflags'] = ["KEEP_MDEBUG=1"]
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@@ -1,58 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from pathlib import Path
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try:
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import rabbitizer
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except ImportError:
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print("Missing dependency rabbitizer, install it with `python3 -m pip install 'rabbitizer>=1.0.0,<2.0.0'`")
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exit(1)
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try:
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import mapfile_parser
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except ImportError:
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print("Missing dependency mapfile_parser, install it with `python3 -m pip install 'mapfile-parser>=1.2.1,<2.0.0'`")
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exit(1)
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def decodeInstruction(bytesDiff: bytes, mapFile: mapfile_parser.MapFile) -> str:
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word = (bytesDiff[0] << 24) | (bytesDiff[1] << 16) | (bytesDiff[2] << 8) | (bytesDiff[3] << 0)
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instr = rabbitizer.Instruction(word)
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immOverride = None
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if instr.isJumpWithAddress():
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# Instruction is a function call (jal)
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# Get the embedded address of the function call
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symAddress = instr.getInstrIndexAsVram()
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# Search for the address in the mapfile
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symInfo = mapFile.findSymbolByVramOrVrom(symAddress)
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if symInfo is not None:
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# Use the symbol from the mapfile instead of a raw value
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immOverride = symInfo.symbol.name
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return instr.disassemble(immOverride=immOverride, extraLJust=-20)
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def firstDiffMain():
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parser = argparse.ArgumentParser(description="Find the first difference(s) between the built ROM and the base ROM.")
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parser.add_argument("-c", "--count", type=int, default=5, help="find up to this many instruction difference(s)")
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parser.add_argument("-v", "--version", help="Which version should be processed", default="us.rev1")
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parser.add_argument("-a", "--add-colons", action='store_true', help="Add colon between bytes" )
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args = parser.parse_args()
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buildFolder = Path("build")
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BUILTROM = Path(buildFolder / f"starfox64.us.rev1.uncompressed.z64")
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BUILTMAP = buildFolder / f"starfox64.us.rev1.map"
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EXPECTEDROM = Path("baserom.us.rev1.uncompressed.z64")
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EXPECTEDMAP = "expected" / BUILTMAP
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mapfile_parser.frontends.first_diff.doFirstDiff(BUILTMAP, EXPECTEDMAP, BUILTROM, EXPECTEDROM, args.count, mismatchSize=True, addColons=args.add_colons, bytesConverterCallback=decodeInstruction)
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if __name__ == "__main__":
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firstDiffMain()
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@@ -1,120 +0,0 @@
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// Signal Processor Registers
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SP_MEM_ADDR_REG = 0xA4040000; // defined:True
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SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
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SP_RD_LEN_REG = 0xA4040008; // defined:True
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SP_WR_LEN_REG = 0xA404000C; // defined:True
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SP_STATUS_REG = 0xA4040010; // defined:True
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SP_DMA_FULL_REG = 0xA4040014; // defined:True
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SP_DMA_BUSY_REG = 0xA4040018; // defined:True
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SP_SEMAPHORE_REG = 0xA404001C; // defined:True
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SP_PC = 0xA4080000; // defined:True
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// Display Processor Command Registers / Rasterizer Interface
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DPC_START_REG = 0xA4100000; // defined:True
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DPC_END_REG = 0xA4100004; // defined:True
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DPC_CURRENT_REG = 0xA4100008; // defined:True
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DPC_STATUS_REG = 0xA410000C; // defined:True
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DPC_CLOCK_REG = 0xA4100010; // defined:True
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DPC_BUFBUSY_REG = 0xA4100014; // defined:True
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DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
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DPC_TMEM_REG = 0xA410001C; // defined:True
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// Display Processor Span Registers
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DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
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DPS_TEST_MODE_REG = 0xA4200004; // defined:True
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DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
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DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
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// MIPS Interface Registers
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MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
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MI_VERSION_REG = 0xA4300004; // defined:True
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MI_INTR_REG = 0xA4300008; // defined:True
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MI_INTR_MASK_REG = 0xA430000C; // defined:True
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// Video Interface Registers
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VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
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VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
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VI_WIDTH_REG = 0xA4400008; // defined:True
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VI_INTR_REG = 0xA440000C; // defined:True
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VI_CURRENT_REG = 0xA4400010; // defined:True
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VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
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VI_V_SYNC_REG = 0xA4400018; // defined:True
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VI_H_SYNC_REG = 0xA440001C; // defined:True
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VI_LEAP_REG = 0xA4400020; // defined:True
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VI_H_START_REG = 0xA4400024; // defined:True
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VI_V_START_REG = 0xA4400028; // defined:True
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VI_V_BURST_REG = 0xA440002C; // defined:True
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VI_X_SCALE_REG = 0xA4400030; // defined:True
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VI_Y_SCALE_REG = 0xA4400034; // defined:True
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// Audio Interface Registers
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AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
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AI_LEN_REG = 0xA4500004; // defined:True
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AI_CONTROL_REG = 0xA4500008; // defined:True
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AI_STATUS_REG = 0xA450000C; // defined:True
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AI_DACRATE_REG = 0xA4500010; // defined:True
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AI_BITRATE_REG = 0xA4500014; // defined:True
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// Peripheral/Parallel Interface Registers
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PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
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PI_CART_ADDR_REG = 0xA4600004; // defined:True
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D_A4600005 = 0xA4600005; // defined:True // TODO figure out its name
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D_A4600006 = 0xA4600006; // defined:True // TODO figure out its name
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D_A4600007 = 0xA4600007; // defined:True // TODO figure out its name
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PI_RD_LEN_REG = 0xA4600008; // defined:True
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PI_WR_LEN_REG = 0xA460000C; // defined:True
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PI_STATUS_REG = 0xA4600010; // defined:True
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PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
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PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
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PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
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PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
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PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
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PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
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PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
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PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
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// RDRAM Interface Registers
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RI_MODE_REG = 0xA4700000; // defined:True
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RI_CONFIG_REG = 0xA4700004; // defined:True
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RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
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RI_SELECT_REG = 0xA470000C; // defined:True
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RI_REFRESH_REG = 0xA4700010; // defined:True
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RI_LATENCY_REG = 0xA4700014; // defined:True
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RI_RERROR_REG = 0xA4700018; // defined:True
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RI_WERROR_REG = 0xA470001C; // defined:True
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// Serial Interface Registers
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SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
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SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
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D_A4800008 = 0xA4800008; // defined:True // reserved
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D_A480000C = 0xA480000C; // defined:True // reserved
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SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
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D_A4800014 = 0xA4800014; // defined:True // reserved
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SI_STATUS_REG = 0xA4800018; // defined:True
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LEO_CMD = 0xA5000508;
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LEO_STATUS = 0xA5000508;
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LEO_BM_CTL = 0xA5000510;
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LEO_BM_STATUS = 0xA5000510;
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LEO_SEQ_CTL = 0xA5000518;
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LEO_SEQ_STATUS = 0xA5000518;
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LEO_C2_BUFF = 0xA5000000;
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LEO_SECTOR_BUFF = 0xA5000400;
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LEO_DATA = 0xA5000500;
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LEO_MISC_REG = 0xA5000504;
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LEO_CUR_TK = 0xA500050C;
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LEO_ERR_SECTOR = 0xA5000514;
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LEO_CUR_SECTOR = 0xA500051C;
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LEO_HARD_RESET = 0xA5000520;
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LEO_C1_S0 = 0xA5000524;
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LEO_HOST_SECBYTE = 0xA5000528;
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LEO_C1_S2 = 0xA500052C;
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LEO_SEC_BYTE = 0xA5000530;
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LEO_C1_S4 = 0xA5000534;
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LEO_C1_S6 = 0xA5000538;
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LEO_CUR_ADDR = 0xA500053C;
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LEO_ID_REG = 0xA5000540;
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LEO_TEST_REG = 0xA5000544;
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LEO_TEST_PIN_SEL = 0xA5000548;
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LEO_RAM_ADDR = 0xA5000580;
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@@ -1,10 +0,0 @@
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// libultra OS symbols
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osTvType = 0x80000300;
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osRomType = 0x80000304;
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osRomBase = 0x80000308;
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osResetType = 0x8000030C;
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osCicId = 0x80000310;
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osVersion = 0x80000314;
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osMemSize = 0x80000318;
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osAppNMIBuffer = 0x8000031C;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,123 +0,0 @@
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// hallucinated symbols
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D_400001 = 0x400001; //ignore:true
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D_7FFFFFFE = 0x7FFFFFFE; //ignore:True
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D_80000000 = 0x80000000; //ignore:True
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D_80000001 = 0x80000001; //ignore:true
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D_80000002 = 0x80000002; //ignore:True
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D_80000003 = 0x80000003; //ignore:True
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D_80000004 = 0x80000004; //ignore:True
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D_80000006 = 0x80000006; //ignore:True
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D_80000008 = 0x80000008; //ignore:True
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D_8000000A = 0x8000000A; //ignore:True
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D_8000000C = 0x8000000C; //ignore:True
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D_8000000D = 0x8000000D; //ignore:True
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D_8000000E = 0x8000000E; //ignore:True
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D_8000000F = 0x8000000F; //ignore:True
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||||
D_80000014 = 0x80000014; //ignore:True
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D_80000018 = 0x80000018; //ignore:True
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||||
D_8000001C = 0x8000001C; //ignore:True
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||||
D_80000024 = 0x80000024; //ignore:True
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||||
D_800F0032 = 0x800F0032; //ignore:True
|
||||
D_80100032 = 0x80100032; //ignore:True
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||||
D_80110000 = 0x80110000; //ignore:True
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||||
D_801100C8 = 0x801100C8; //ignore:True
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||||
D_80120000 = 0x80120000; //ignore:True
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||||
D_801200C8 = 0x801200C8; //ignore:True
|
||||
D_80130001 = 0x80130001; //ignore:True
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||||
D_801300C8 = 0x801300C8; //ignore:True
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D_80140001 = 0x80140001; //ignore:true
|
||||
D_80150000 = 0x80150000; //ignore:true
|
||||
D_80160000 = 0x80160000; //ignore:true
|
||||
D_80170000 = 0x80170000; //ignore:true
|
||||
D_80170001 = 0x80170001; //ignore:true
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||||
D_80180001 = 0x80180001; //ignore:True
|
||||
D_80180058 = 0x80180058; //ignore:True
|
||||
D_801D0001 = 0x801D0001; //ignore:True
|
||||
D_801C0130 = 0x801C0130; //ignore:True
|
||||
|
||||
// mirage symbols
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||||
D_3000000 = 0x3000000; //ignore:true
|
||||
D_6000000 = 0x6000000; //ignore:true
|
||||
D_7000000 = 0x7000000; //ignore:true
|
||||
D_8000000 = 0x8000000; //ignore:true
|
||||
D_A000000 = 0xA000000; //ignore:true
|
||||
D_C000000 = 0xC000000; //ignore:true
|
||||
|
||||
// rsp
|
||||
rspbootTextStart = 0x800004D0;//name_end:rspbootTextEnd
|
||||
aspMainTextStart = 0x800005A0;//name_end:aspMainTextEnd
|
||||
gspF3DEX_fifoTextStart = 0x80001490;//name_end:gspF3DEX_fifoTextEnd
|
||||
gspF3DEX_fifoDataStart = 0x800C4980; //name_end:gspF3DEX_fifoDataEnd
|
||||
aspMainDataStart = 0x800C3E70; //name_end:aspMainDataEnd
|
||||
altIPL3Start = 0x8001F090;
|
||||
|
||||
// redundant rodata
|
||||
D_800D63EC = 0x800D63EC; //force_migration:true
|
||||
D_800D65F8 = 0x800D65F8; //force_migration:true
|
||||
D_800D660C = 0x800D660C; //force_migration:true
|
||||
D_800D99D0 = 0x800D99D0; //force_migration:true
|
||||
D_800D99E0 = 0x800D99E0; //force_migration:true
|
||||
D_800D9A04 = 0x800D9A04; //force_migration:true
|
||||
D_800DA7B0 = 0x800DA7B0; //force_migration:true
|
||||
D_i3_801C517C = 0x801C517C; //force_migration:true segment:ovl_i3
|
||||
D_i3_801C5188 = 0x801C5188; //force_migration:true segment:ovl_i3
|
||||
D_i3_801C5190 = 0x801C5190; //force_migration:true segment:ovl_i3
|
||||
D_i3_801C51B8 = 0x801C51B8; //force_migration:true segment:ovl_i3
|
||||
D_i4_801A3754 = 0x801A3754; //force_migration:true segment:ovl_i4
|
||||
D_i5_801BF248 = 0x801BF248; //force_migration:true segment:ovl_i5
|
||||
D_i5_801BF27C = 0x801BF27C; //force_migration:true segment:ovl_i5
|
||||
D_i5_801BF510 = 0x801BF510; //force_migration:true segment:ovl_i5
|
||||
D_i5_801BF524 = 0x801BF524; //force_migration:true segment:ovl_i5
|
||||
D_i6_801AAF70 = 0x801AAF70; //force_migration:true segment:ovl_i6
|
||||
|
||||
// constant for K1 access
|
||||
D_A0000000 = 0xA0000000;//ignore:true
|
||||
|
||||
// hardcoded address used in sys_rdram
|
||||
D_A0300000 = 0xA0300000;//ignore:true
|
||||
D_A4000000 = 0xA4000000;//ignore:true
|
||||
|
||||
// hardcoded addresses in libultra
|
||||
D_BFF00000 = 0xBFF00000;//ignore:true
|
||||
D_BFF08000 = 0xBFF08000;//ignore:true
|
||||
D_BFF08004 = 0xBFF08004;//ignore:true
|
||||
|
||||
// RDB regs used only in exceptasm. Also -2.0f
|
||||
D_C0000000 = 0xC0000000;//ignore:true
|
||||
D_C0000008 = 0xC0000008;//ignore:true
|
||||
D_C000000C = 0xC000000C;//ignore:true
|
||||
|
||||
// hidden symbols
|
||||
sSamplesPerWavePeriod = 0x800C63E8; //size:0x4 type:u8
|
||||
sOvlUnused_Unk = 0x800CCBAC;
|
||||
D_800D6994 = 0x800D6994;
|
||||
D_801BE59C = 0x801BE59C; //segment:ovl_i5
|
||||
|
||||
// fake symbol removal
|
||||
gDmaTable = 0x8017ABE0; //size:0x650
|
||||
|
||||
// that stupid thing where i6 sets a value in ending
|
||||
D_i6_8019A490 = 0x8019A490; //ignore:true segment:ovl_i6
|
||||
|
||||
// dma symbols
|
||||
dma_table_ROM_START = 0xE0570;
|
||||
audio_seq_ROM_START = 0xE0BC0;
|
||||
audio_bank_ROM_START = 0x127F50;
|
||||
audio_table_ROM_START = 0x1471E0;
|
||||
ast_radio_de_ROM_START = 0xDE12C0;
|
||||
ast_radio_de_VRAM = 0x8017B230;
|
||||
ast_radio_de_ROM_END = 0xDF10B0;
|
||||
ast_radio_en_ROM_START = 0xEFB1A0;
|
||||
ast_radio_fr_ROM_START = 0xF08CF0;
|
||||
ast_radio_fr_ROM_END = 0xF17200;
|
||||
|
||||
// buffers
|
||||
gDramStack = 0x80289000; //size:0x400 segment:buffers defined:true
|
||||
gOSYieldData = 0x80289400; //size:0xC00 segment:buffers defined:true
|
||||
gZBuffer = 0x8028A000; //size:0x25800 segment:buffers defined:true
|
||||
gTaskOutputBuffer = 0x802AF800; //size:0x30000 name_end:gTaskOutputBufferEnd segment:buffers defined:true
|
||||
gAudioHeap = 0x802DF800; //size:0xB0000 segment:buffers defined:true
|
||||
gFillBuffer = 0x8038F800; //size:0x780 segment:buffers defined:true
|
||||
D_8038FA80 = 0x8038FA80;//ignore:true segment:buffers
|
||||
gFrameBuffers = 0x8038FF80; //size:0x70800 segment:buffers defined:true
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,120 +0,0 @@
|
||||
// Signal Processor Registers
|
||||
SP_MEM_ADDR_REG = 0xA4040000; // defined:True
|
||||
SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
|
||||
SP_RD_LEN_REG = 0xA4040008; // defined:True
|
||||
SP_WR_LEN_REG = 0xA404000C; // defined:True
|
||||
SP_STATUS_REG = 0xA4040010; // defined:True
|
||||
SP_DMA_FULL_REG = 0xA4040014; // defined:True
|
||||
SP_DMA_BUSY_REG = 0xA4040018; // defined:True
|
||||
SP_SEMAPHORE_REG = 0xA404001C; // defined:True
|
||||
|
||||
SP_PC = 0xA4080000; // defined:True
|
||||
|
||||
// Display Processor Command Registers / Rasterizer Interface
|
||||
DPC_START_REG = 0xA4100000; // defined:True
|
||||
DPC_END_REG = 0xA4100004; // defined:True
|
||||
DPC_CURRENT_REG = 0xA4100008; // defined:True
|
||||
DPC_STATUS_REG = 0xA410000C; // defined:True
|
||||
DPC_CLOCK_REG = 0xA4100010; // defined:True
|
||||
DPC_BUFBUSY_REG = 0xA4100014; // defined:True
|
||||
DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
|
||||
DPC_TMEM_REG = 0xA410001C; // defined:True
|
||||
|
||||
// Display Processor Span Registers
|
||||
DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
|
||||
DPS_TEST_MODE_REG = 0xA4200004; // defined:True
|
||||
DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
|
||||
DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
|
||||
|
||||
// MIPS Interface Registers
|
||||
MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
|
||||
MI_VERSION_REG = 0xA4300004; // defined:True
|
||||
MI_INTR_REG = 0xA4300008; // defined:True
|
||||
MI_INTR_MASK_REG = 0xA430000C; // defined:True
|
||||
|
||||
// Video Interface Registers
|
||||
VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
|
||||
VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
|
||||
VI_WIDTH_REG = 0xA4400008; // defined:True
|
||||
VI_INTR_REG = 0xA440000C; // defined:True
|
||||
VI_CURRENT_REG = 0xA4400010; // defined:True
|
||||
VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
|
||||
VI_V_SYNC_REG = 0xA4400018; // defined:True
|
||||
VI_H_SYNC_REG = 0xA440001C; // defined:True
|
||||
VI_LEAP_REG = 0xA4400020; // defined:True
|
||||
VI_H_START_REG = 0xA4400024; // defined:True
|
||||
VI_V_START_REG = 0xA4400028; // defined:True
|
||||
VI_V_BURST_REG = 0xA440002C; // defined:True
|
||||
VI_X_SCALE_REG = 0xA4400030; // defined:True
|
||||
VI_Y_SCALE_REG = 0xA4400034; // defined:True
|
||||
|
||||
// Audio Interface Registers
|
||||
AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
|
||||
AI_LEN_REG = 0xA4500004; // defined:True
|
||||
AI_CONTROL_REG = 0xA4500008; // defined:True
|
||||
AI_STATUS_REG = 0xA450000C; // defined:True
|
||||
AI_DACRATE_REG = 0xA4500010; // defined:True
|
||||
AI_BITRATE_REG = 0xA4500014; // defined:True
|
||||
|
||||
// Peripheral/Parallel Interface Registers
|
||||
PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
|
||||
PI_CART_ADDR_REG = 0xA4600004; // defined:True
|
||||
D_A4600005 = 0xA4600005; // defined:True // TODO figure out its name
|
||||
D_A4600006 = 0xA4600006; // defined:True // TODO figure out its name
|
||||
D_A4600007 = 0xA4600007; // defined:True // TODO figure out its name
|
||||
PI_RD_LEN_REG = 0xA4600008; // defined:True
|
||||
PI_WR_LEN_REG = 0xA460000C; // defined:True
|
||||
PI_STATUS_REG = 0xA4600010; // defined:True
|
||||
PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
|
||||
PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
|
||||
PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
|
||||
PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
|
||||
PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
|
||||
PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
|
||||
PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
|
||||
PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
|
||||
|
||||
// RDRAM Interface Registers
|
||||
RI_MODE_REG = 0xA4700000; // defined:True
|
||||
RI_CONFIG_REG = 0xA4700004; // defined:True
|
||||
RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
|
||||
RI_SELECT_REG = 0xA470000C; // defined:True
|
||||
RI_REFRESH_REG = 0xA4700010; // defined:True
|
||||
RI_LATENCY_REG = 0xA4700014; // defined:True
|
||||
RI_RERROR_REG = 0xA4700018; // defined:True
|
||||
RI_WERROR_REG = 0xA470001C; // defined:True
|
||||
|
||||
// Serial Interface Registers
|
||||
SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
|
||||
SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
|
||||
D_A4800008 = 0xA4800008; // defined:True // reserved
|
||||
D_A480000C = 0xA480000C; // defined:True // reserved
|
||||
SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
|
||||
D_A4800014 = 0xA4800014; // defined:True // reserved
|
||||
SI_STATUS_REG = 0xA4800018; // defined:True
|
||||
|
||||
LEO_CMD = 0xA5000508;
|
||||
LEO_STATUS = 0xA5000508;
|
||||
LEO_BM_CTL = 0xA5000510;
|
||||
LEO_BM_STATUS = 0xA5000510;
|
||||
LEO_SEQ_CTL = 0xA5000518;
|
||||
LEO_SEQ_STATUS = 0xA5000518;
|
||||
LEO_C2_BUFF = 0xA5000000;
|
||||
LEO_SECTOR_BUFF = 0xA5000400;
|
||||
LEO_DATA = 0xA5000500;
|
||||
LEO_MISC_REG = 0xA5000504;
|
||||
LEO_CUR_TK = 0xA500050C;
|
||||
LEO_ERR_SECTOR = 0xA5000514;
|
||||
LEO_CUR_SECTOR = 0xA500051C;
|
||||
LEO_HARD_RESET = 0xA5000520;
|
||||
LEO_C1_S0 = 0xA5000524;
|
||||
LEO_HOST_SECBYTE = 0xA5000528;
|
||||
LEO_C1_S2 = 0xA500052C;
|
||||
LEO_SEC_BYTE = 0xA5000530;
|
||||
LEO_C1_S4 = 0xA5000534;
|
||||
LEO_C1_S6 = 0xA5000538;
|
||||
LEO_CUR_ADDR = 0xA500053C;
|
||||
LEO_ID_REG = 0xA5000540;
|
||||
LEO_TEST_REG = 0xA5000544;
|
||||
LEO_TEST_PIN_SEL = 0xA5000548;
|
||||
LEO_RAM_ADDR = 0xA5000580;
|
||||
@@ -1,10 +0,0 @@
|
||||
// libultra OS symbols
|
||||
|
||||
osTvType = 0x80000300;
|
||||
osRomType = 0x80000304;
|
||||
osRomBase = 0x80000308;
|
||||
osResetType = 0x8000030C;
|
||||
osCicId = 0x80000310;
|
||||
osVersion = 0x80000314;
|
||||
osMemSize = 0x80000318;
|
||||
osAppNMIBuffer = 0x8000031C;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,109 +0,0 @@
|
||||
// hallucinated symbols
|
||||
D_7FFFFFFE = 0x7FFFFFFE; //ignore:true
|
||||
D_80000000 = 0x80000000; //ignore:true
|
||||
D_80000001 = 0x80000001; //ignore:true
|
||||
D_80000002 = 0x80000002; //ignore:true
|
||||
D_80000003 = 0x80000003; //ignore:true
|
||||
D_80000004 = 0x80000004; //ignore:true
|
||||
D_80000006 = 0x80000006; //ignore:true
|
||||
D_80000008 = 0x80000008; //ignore:true
|
||||
D_8000000A = 0x8000000A; //ignore:true
|
||||
D_8000000C = 0x8000000C; //ignore:true
|
||||
D_8000000D = 0x8000000D; //ignore:true
|
||||
D_8000000E = 0x8000000E; //ignore:true
|
||||
D_8000000F = 0x8000000F; //ignore:true
|
||||
D_80000014 = 0x80000014; //ignore:true
|
||||
D_80000018 = 0x80000018; //ignore:true
|
||||
D_8000001C = 0x8000001C; //ignore:true
|
||||
D_80000024 = 0x80000024; //ignore:true
|
||||
D_800D0000 = 0x800D0000; //ignore:true
|
||||
D_800F0032 = 0x800F0032; //ignore:true
|
||||
D_80100032 = 0x80100032; //ignore:true
|
||||
D_80110000 = 0x80110000; //ignore:true
|
||||
D_80110001 = 0x80110001; //ignore:true
|
||||
D_801100C8 = 0x801100C8; //ignore:true
|
||||
D_80120000 = 0x80120000; //ignore:true
|
||||
D_80120001 = 0x80120001; //ignore:true
|
||||
D_801200C8 = 0x801200C8; //ignore:true
|
||||
D_80130001 = 0x80130001; //ignore:true
|
||||
D_801300C8 = 0x801300C8; //ignore:true
|
||||
D_80180000 = 0x80180000; //ignore:true
|
||||
D_80140001 = 0x80140001; //ignore:true
|
||||
D_80150000 = 0x80150000; //ignore:true
|
||||
D_80160000 = 0x80160000; //ignore:true
|
||||
D_80170000 = 0x80170000; //ignore:true
|
||||
D_80170001 = 0x80170001; //ignore:true
|
||||
D_80180000 = 0x80180000; //ignore:true
|
||||
D_80180001 = 0x80180001; //ignore:true
|
||||
D_80180058 = 0x80180058; //ignore:true
|
||||
D_801B0130 = 0x801B0130; //ignore:true
|
||||
D_801C0001 = 0x801C0001; //ignore:true
|
||||
|
||||
// mirage symbols
|
||||
D_6000000 = 0x06000000; //ignore:true
|
||||
D_7000000 = 0x07000000; //ignore:true
|
||||
D_8000000 = 0x08000000; //ignore:true
|
||||
D_A000000 = 0x0A000000; //ignore:true
|
||||
D_F000000 = 0x0F000000; //ignore:true
|
||||
|
||||
// rsp
|
||||
rspbootTextStart = 0x80000450;//name_end:rspbootTextEnd
|
||||
aspMainTextStart = 0x80000520;//name_end:aspMainTextEnd
|
||||
gspF3DEX_fifoTextStart = 0x80001420;//name_end:gspF3DEX_fifoTextEnd
|
||||
gspF3DEX_fifoDataStart = 0x800C0F20; //name_end:gspF3DEX_fifoDataEnd
|
||||
aspMainDataStart = 0x800C0430; //name_end:aspMainDataEnd
|
||||
|
||||
// constant for K1 access
|
||||
D_A0000000 = 0xA0000000;//ignore:true
|
||||
|
||||
// hardcoded addresses in libultra
|
||||
D_BFF00000 = 0xBFF00000;//ignore:true
|
||||
D_BFF08000 = 0xBFF08000;//ignore:true
|
||||
D_BFF08004 = 0xBFF08004;//ignore:true
|
||||
|
||||
// RDB regs used only in exceptasm. Also -2.0f
|
||||
D_C0000000 = 0xC0000000;//ignore:true
|
||||
D_C0000008 = 0xC0000008;//ignore:true
|
||||
D_C000000C = 0xC000000C;//ignore:true
|
||||
|
||||
// redundant rodata
|
||||
D_800DB02C = 0x800DB02C; // force_migration:True
|
||||
D_800DB24C = 0x800DB24C; // force_migration:True
|
||||
D_800DB238 = 0x800DB238; // force_migration:True
|
||||
D_800DE430 = 0x800DE430; // force_migration:True
|
||||
D_800DE440 = 0x800DE440; // force_migration:True
|
||||
D_800DE464 = 0x800DE464; // force_migration:True
|
||||
D_800DF21C = 0x800DF21C; // force_migration:True
|
||||
D_i1_80192474 = 0x80192474; // force_migration:True segment:ovl_i1
|
||||
D_i3_801B89CC = 0x801B89CC; // force_migration:True segment:ovl_i3
|
||||
D_i3_801B89D8 = 0x801B89D8; // force_migration:True segment:ovl_i3
|
||||
D_i3_801B89E0 = 0x801B89E0; // force_migration:True segment:ovl_i3
|
||||
D_i3_801B8A08 = 0x801B8A08; // force_migration:True segment:ovl_i3
|
||||
D_i4_80196D64 = 0x80196D64; // force_migration:True segment:ovl_i4
|
||||
D_i5_801B2B18 = 0x801B2B18; // force_migration:True segment:ovl_i5
|
||||
D_i5_801B2B4C = 0x801B2B4C; // force_migration:True segment:ovl_i5
|
||||
D_i5_801B2DE0 = 0x801B2DE0; // force_migration:True segment:ovl_i5
|
||||
D_i5_801B2DF4 = 0x801B2DF4; // force_migration:True segment:ovl_i5
|
||||
D_i6_8019E810 = 0x8019E810; // force_migration:True segment:ovl_i6
|
||||
|
||||
// constant for K1 access
|
||||
D_A0000000 = 0xA0000000;//ignore:true
|
||||
|
||||
// hardcoded address used in sys_rdram
|
||||
D_A0300000 = 0xA0300000;//ignore:true
|
||||
D_A4000000 = 0xA4000000;//ignore:true
|
||||
|
||||
// hidden vars
|
||||
D_800C5118 = 0x800C5118;
|
||||
D_800DB5D4 = 0x800DB5D4;
|
||||
sOvlUnused_Unk = 0x800C88DC;
|
||||
D_i5_801B1E6C = 0x801B1E6C; // segment:ovl_i5
|
||||
|
||||
// that stupid thing where i6 sets a value in ending
|
||||
D_i6_8018DD90 = 0x8018DD90; //ignore:true segment:ovl_i6
|
||||
|
||||
// dma symbols
|
||||
dma_table_ROM_START = 0xE93C0;
|
||||
audio_seq_ROM_START = 0xE9950;
|
||||
audio_bank_ROM_START = 0x124920;
|
||||
audio_table_ROM_START = 0x143A40;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1 +0,0 @@
|
||||
bootproc = 0x80004EB8;
|
||||
@@ -1,8 +0,0 @@
|
||||
// dma symbols
|
||||
gDmaTable = 0x8017DB20;
|
||||
dma_table_ROM_START = 0xE44F0; //defined:true
|
||||
audio_seq_ROM_START = 0xE4A90; //defined:true
|
||||
audio_bank_ROM_START = 0x11F780; //defined:true
|
||||
audio_table_ROM_START = 0x13D7A0; //defined:true
|
||||
ovl_ending = 0x00F02520; //defined:true
|
||||
ovl_unused = 0x00F025C0; //defined:true
|
||||
@@ -1 +0,0 @@
|
||||
Save_Read = 0x800BED14;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user