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Android project - mVU_Globals => PTR_CPU(mVUglob)

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This commit is contained in:
k2154
2025-08-16 05:06:43 +09:00
parent 3ca937df00
commit f5a2533be3
12 changed files with 111 additions and 113 deletions
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app/src/main/cpp/common/arm64/AsmHelpers.h
+2 -1
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@@ -57,6 +57,7 @@ namespace a64 = vixl::aarch64;
// fastmem
#define RFASTMEMBASE a64::x25
#define PTR_MBLOCK(field) a64::MemOperand(RFASTMEMBASE, offsetof(microBlock, field))
#define RSTATE_x26 a64::x26
@@ -69,7 +70,7 @@ namespace a64 = vixl::aarch64;
#define RSTATE_MVU a64::x28
#define PTR_MVU(field) a64::MemOperand(RSTATE_MVU, offsetof(vuRegistersPack, field))
// iopMem->Main
// iopMem->Main, vu1Thread
#define RSTATE_x29 a64::x29
#define PTR_VU1(field) a64::MemOperand(RSTATE_x29, offsetof(VU_Thread, field))
app/src/main/cpp/pcsx2/R5900.cpp
+1 -1
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@@ -34,7 +34,7 @@ using namespace R5900; // for R5900 disasm tools
s32 EEsCycle; // used to sync the IOP to the EE
u32 EEoCycle;
alignas(16) cpuRegistersPack g_cpuRegistersPack;
alignas(32) cpuRegistersPack g_cpuRegistersPack;
alignas(16) tlbs tlb[48];
cachedTlbs_t cachedTlbs;
app/src/main/cpp/pcsx2/VUDef.h
+38
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@@ -170,4 +170,42 @@ struct alignas(16) VURegs
}
};
struct mVU_Globals
{
#define __four(val) { val, val, val, val }
u32 absclip [4] = __four(0x7fffffff);
u32 signbit [4] = __four(0x80000000);
u32 minvals [4] = __four(0xff7fffff);
u32 maxvals [4] = __four(0x7f7fffff);
u32 exponent[4] = __four(0x7f800000);
u32 one [4] = __four(0x3f800000);
u32 Pi4 [4] = __four(0x3f490fdb);
u32 T1 [4] = __four(0x3f7ffff5);
u32 T5 [4] = __four(0xbeaaa61c);
u32 T2 [4] = __four(0x3e4c40a6);
u32 T3 [4] = __four(0xbe0e6c63);
u32 T4 [4] = __four(0x3dc577df);
u32 T6 [4] = __four(0xbd6501c4);
u32 T7 [4] = __four(0x3cb31652);
u32 T8 [4] = __four(0xbb84d7e7);
u32 S2 [4] = __four(0xbe2aaaa4);
u32 S3 [4] = __four(0x3c08873e);
u32 S4 [4] = __four(0xb94fb21f);
u32 S5 [4] = __four(0x362e9c14);
u32 E1 [4] = __four(0x3e7fffa8);
u32 E2 [4] = __four(0x3d0007f4);
u32 E3 [4] = __four(0x3b29d3ff);
u32 E4 [4] = __four(0x3933e553);
u32 E5 [4] = __four(0x36b63510);
u32 E6 [4] = __four(0x353961ac);
u32 I32MAXF [4] = __four(0x4effffff);
float FTOI_4 [4] = __four(16.0);
float FTOI_12 [4] = __four(4096.0);
float FTOI_15 [4] = __four(32768.0);
float ITOF_4 [4] = __four(0.0625f);
float ITOF_12 [4] = __four(0.000244140625);
float ITOF_15 [4] = __four(0.000030517578125);
#undef __four
};
#endif //PCSX2_VUDEF_H
app/src/main/cpp/pcsx2/cpuRegistersPack.h
+3 -1
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@@ -15,13 +15,15 @@ struct cpuRegistersPack
alignas(16) fpuRegisters fpuRegs{};
alignas(16) psxRegisters psxRegs{};
alignas(16) VURegs vuRegs[2];
alignas(32) mVU_Globals mVUglob;
};
alignas(16) extern cpuRegistersPack g_cpuRegistersPack;
alignas(32) extern cpuRegistersPack g_cpuRegistersPack;
////
static cpuRegisters& cpuRegs = g_cpuRegistersPack.cpuRegs;
static fpuRegisters& fpuRegs = g_cpuRegistersPack.fpuRegs;
static psxRegisters& psxRegs = g_cpuRegistersPack.psxRegs;
static VURegs& VU0 = g_cpuRegistersPack.vuRegs[0];
static VURegs& VU1 = g_cpuRegistersPack.vuRegs[1];
static mVU_Globals& mVUglob = g_cpuRegistersPack.mVUglob;
#endif //PCSX2_CPUREGISTERSPACK_H
app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp
+1
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@@ -20,6 +20,7 @@
#include "common/FastJmp.h"
#include "common/HeapArray.h"
#include "common/Perf.h"
#include "x86/microVU_Misc.h"
// Only for MOVQ workaround.
#if !defined(__ANDROID__)
app/src/main/cpp/pcsx2/x86/microVU_Branch.inl
+3 -3
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@@ -413,7 +413,7 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump)
else
{
// xLoadFarAddr(arg2reg, &mVUpBlock->pStateEnd);
armMoveAddressToReg(RCX, &mVUpBlock->pStateEnd);
armAsm->Ldr(RCX, PTR_MBLOCK(pStateEnd));
}
if (mVUup.eBit && isEvilJump) // E-bit EvilJump
@@ -515,7 +515,7 @@ void normBranch(mV, microFlagCycles& mFC)
memcpy(&mVUpBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
// xLoadFarAddr(rax, &mVUpBlock->pStateEnd);
armMoveAddressToReg(RAX, &mVUpBlock->pStateEnd);
armAsm->Ldr(RAX, PTR_MBLOCK(pStateEnd));
// xCALL((void*)mVU.copyPLState);
armEmitCall(mVU.copyPLState);
@@ -654,7 +654,7 @@ void condBranch(mV, microFlagCycles& mFC, a64::Condition JMPcc)
memcpy(&mVUpBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
// xLoadFarAddr(rax, &mVUpBlock->pStateEnd);
armMoveAddressToReg(RAX, &mVUpBlock->pStateEnd);
armAsm->Ldr(RAX, PTR_MBLOCK(pStateEnd));
// xCALL((void*)mVU.copyPLState);
armEmitCall(mVU.copyPLState);
app/src/main/cpp/pcsx2/x86/microVU_Clamp.inl
+4 -4
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@@ -30,15 +30,15 @@ void mVUclamp1(microVU& mVU, const xmm& reg, const xmm& regT1, int xyzw, bool bC
{
case 1: case 2: case 4: case 8:
// xMIN.SS(reg, ptr32[mVUglob.maxvals]);
armAsm->Fminnm(reg.S(), reg.S(), armLoadPtrV(mVUglob.maxvals).S());
armAsm->Fminnm(reg.S(), reg.S(), armLoadPtrV(PTR_CPU(mVUglob.maxvals)).S());
// xMAX.SS(reg, ptr32[mVUglob.minvals]);
armAsm->Fmaxnm(reg.S(), reg.S(), armLoadPtrV(mVUglob.minvals).S());
armAsm->Fmaxnm(reg.S(), reg.S(), armLoadPtrV(PTR_CPU(mVUglob.minvals)).S());
break;
default:
// xMIN.PS(reg, ptr32[mVUglob.maxvals]);
armAsm->Fminnm(reg.V4S(), reg.V4S(), armLoadPtrV(mVUglob.maxvals).V4S());
armAsm->Fminnm(reg.V4S(), reg.V4S(), armLoadPtrV(PTR_CPU(mVUglob.maxvals)).V4S());
// xMAX.PS(reg, ptr32[mVUglob.minvals]);
armAsm->Fmaxnm(reg.V4S(), reg.V4S(), armLoadPtrV(mVUglob.minvals).V4S());
armAsm->Fmaxnm(reg.V4S(), reg.V4S(), armLoadPtrV(PTR_CPU(mVUglob.minvals)).V4S());
break;
}
}
app/src/main/cpp/pcsx2/x86/microVU_Execute.inl
+2 -4
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@@ -23,15 +23,15 @@ static bool mvuNeedsFPCRUpdate(mV)
void mVUdispatcherAB(mV)
{
mVU.startFunct = armStartBlock();
{
// xScopedStackFrame frame(false, true);
armBeginStackFrame();
// From memory to registry
armMoveAddressToReg(RSTATE_x29, &vu1Thread);
armMoveAddressToReg(RSTATE_MVU, &g_vuRegistersPack);
armMoveAddressToReg(RSTATE_CPU, &g_cpuRegistersPack);
armMoveAddressToReg(RSTATE_x29, &vu1Thread);
armMoveAddressToReg(RFASTMEMBASE, &mVUpBlock);
// = The caller has already put the needed parameters in ecx/edx:
if (!isVU1) {
@@ -139,7 +139,6 @@ void mVUdispatcherAB(mV)
void mVUdispatcherCD(mV)
{
mVU.startFunctXG = armStartBlock();
{
// xScopedStackFrame frame(false, true);
armBeginStackFrame();
@@ -261,7 +260,6 @@ static void mVUGenerateWaitMTVU(mV)
static void mVUGenerateCopyPipelineState(mV)
{
mVU.copyPLState = armStartBlock();
{
// xMOVAPS(xmm0, ptr[rax]);
armAsm->Ldr(xmm0, a64::MemOperand(RAX));
app/src/main/cpp/pcsx2/x86/microVU_Lower.inl
+32 -32
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@@ -35,7 +35,7 @@ static __fi void testNeg(mV, const xmm& xmmReg, const x32& gprTemp)
// xMOV(ptr32[&mVU.divFlag], divI);
armStorePtr(divI, PTR_MVU(microVU[mVU.index].divFlag));
// xAND.PS(xmmReg, ptr128[mVUglob.absclip]);
armAsm->And(xmmReg.V16B(), xmmReg.V16B(), armLoadPtrV(mVUglob.absclip).V16B());
armAsm->And(xmmReg.V16B(), xmmReg.V16B(), armLoadPtrV(PTR_CPU(mVUglob.absclip)).V16B());
// skip.SetTarget();
armBind(&skip);
}
@@ -75,9 +75,9 @@ mVUop(mVU_DIV)
// xXOR.PS(Fs, Ft);
armAsm->Eor(Fs.V16B(), Fs.V16B(), Ft.V16B());
// xAND.PS(Fs, ptr128[mVUglob.signbit]);
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.signbit).V16B());
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.signbit)).V16B());
// xOR.PS (Fs, ptr128[mVUglob.maxvals]); // If division by zero, then xmmFs = +/- fmax
armAsm->Orr(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.maxvals).V16B());
armAsm->Orr(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.maxvals)).V16B());
// xForwardJump8 djmp;
a64::Label djmp;
@@ -122,7 +122,7 @@ mVUop(mVU_SQRT)
if (CHECK_VU_OVERFLOW(mVU.index)) { // Clamp infinities (only need to do positive clamp since xmmFt is positive)
// xMIN.SS(Ft, ptr32[mVUglob.maxvals]);
armAsm->Umin(Ft.V4S(), Ft.V4S(), armLoadPtrV(mVUglob.maxvals).V4S());
armAsm->Umin(Ft.V4S(), Ft.V4S(), armLoadPtrV(PTR_CPU(mVUglob.maxvals)).V4S());
}
// xSQRT.SS(Ft, Ft);
armAsm->Fsqrt(Ft.S(), Ft.S());
@@ -179,9 +179,9 @@ mVUop(mVU_RSQRT)
armBind(&cjmp);
// xAND.PS(Fs, ptr128[mVUglob.signbit]);
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.signbit).V16B());
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.signbit)).V16B());
// xOR.PS(Fs, ptr128[mVUglob.maxvals]); // xmmFs = +/-Max
armAsm->Orr(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.maxvals).V16B());
armAsm->Orr(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.maxvals)).V16B());
// xForwardJump8 djmp;
a64::Label djmp;
@@ -230,18 +230,18 @@ static __fi void mVU_EATAN_(mV, const xmm& PQ, const xmm& Fs, const xmm& t1, con
// xMOVSS(PQ, Fs);
armAsm->Mov(PQ.S(), 0, Fs.S(), 0);
// xMUL.SS(PQ, ptr32[mVUglob.T1]);
armAsm->Fmul(PQ.S(), PQ.S(), armLoadPtrV(mVUglob.T1).S());
armAsm->Fmul(PQ.S(), PQ.S(), armLoadPtrV(PTR_CPU(mVUglob.T1)).S());
// xMOVAPS(t2, Fs);
armAsm->Mov(t2.Q(), Fs.Q());
EATANhelper(mVUglob.T2);
EATANhelper(mVUglob.T3);
EATANhelper(mVUglob.T4);
EATANhelper(mVUglob.T5);
EATANhelper(mVUglob.T6);
EATANhelper(mVUglob.T7);
EATANhelper(mVUglob.T8);
EATANhelper(PTR_CPU(mVUglob.T2));
EATANhelper(PTR_CPU(mVUglob.T3));
EATANhelper(PTR_CPU(mVUglob.T4));
EATANhelper(PTR_CPU(mVUglob.T5));
EATANhelper(PTR_CPU(mVUglob.T6));
EATANhelper(PTR_CPU(mVUglob.T7));
EATANhelper(PTR_CPU(mVUglob.T8));
// xADD.SS(PQ, ptr32[mVUglob.Pi4]);
armAsm->Fadd(PQ.S(), PQ.S(), armLoadPtrV(mVUglob.Pi4).S());
armAsm->Fadd(PQ.S(), PQ.S(), armLoadPtrV(PTR_CPU(mVUglob.Pi4)).S());
// xPSHUF.D(PQ, PQ, mVUinfo.writeP ? 0x27 : 0xC6);
armPSHUFD(PQ, PQ, mVUinfo.writeP ? 0x27 : 0xC6);
}
@@ -267,9 +267,9 @@ mVUop(mVU_EATAN)
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
// xSUB.SS(Fs, ptr32[mVUglob.one]);
armAsm->Fsub(Fs.S(), Fs.S(), armLoadPtrV(mVUglob.one).S());
armAsm->Fsub(Fs.S(), Fs.S(), armLoadPtrV(PTR_CPU(mVUglob.one)).S());
// xADD.SS(xmmPQ, ptr32[mVUglob.one]);
armAsm->Fadd(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(mVUglob.one).S());
armAsm->Fadd(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(PTR_CPU(mVUglob.one)).S());
SSE_DIVSS(mVU, Fs, xmmPQ);
mVU_EATAN_(mVU, xmmPQ, Fs, t1, t2);
mVU.regAlloc->clearNeeded(Fs);
@@ -377,28 +377,28 @@ mVUop(mVU_EEXP)
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
// xMUL.SS (xmmPQ, ptr32[mVUglob.E1]);
armAsm->Fmul(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(mVUglob.E1).S());
armAsm->Fmul(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(PTR_CPU(mVUglob.E1)).S());
// xADD.SS (xmmPQ, ptr32[mVUglob.one]);
armAsm->Fadd(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(mVUglob.one).S());
armAsm->Fadd(xmmPQ.S(), xmmPQ.S(), armLoadPtrV(PTR_CPU(mVUglob.one)).S());
// xMOVAPS(t1, Fs);
armAsm->Mov(t1.Q(), Fs.Q());
SSE_MULSS(mVU, t1, Fs);
// xMOVAPS(t2, t1);
armAsm->Mov(t2.Q(), t1.Q());
// xMUL.SS(t1, ptr32[mVUglob.E2]);
armAsm->Fmul(t1.S(), t1.S(), armLoadPtrV(mVUglob.E2).S());
armAsm->Fmul(t1.S(), t1.S(), armLoadPtrV(PTR_CPU(mVUglob.E2)).S());
SSE_ADDSS(mVU, xmmPQ, t1);
eexpHelper(&mVUglob.E3);
eexpHelper(&mVUglob.E4);
eexpHelper(&mVUglob.E5);
SSE_MULSS(mVU, t2, Fs);
// xMUL.SS(t2, ptr32[mVUglob.E6]);
armAsm->Fmul(t2.S(), t2.S(), armLoadPtrV(mVUglob.E6).S());
armAsm->Fmul(t2.S(), t2.S(), armLoadPtrV(PTR_CPU(mVUglob.E6)).S());
SSE_ADDSS(mVU, xmmPQ, t2);
SSE_MULSS(mVU, xmmPQ, xmmPQ);
SSE_MULSS(mVU, xmmPQ, xmmPQ);
// xMOVSSZX(t2, ptr32[mVUglob.one]);
armAsm->Ldr(t2, armMemOperandPtr(mVUglob.one));
armAsm->Ldr(t2, PTR_CPU(mVUglob.one));
SSE_DIVSS(mVU, t2, xmmPQ);
// xMOVSS(xmmPQ, t2);
armAsm->Mov(xmmPQ.S(), 0, t2.S(), 0);
@@ -470,7 +470,7 @@ mVUop(mVU_ERCPR)
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
// xMOVSSZX (Fs, ptr32[mVUglob.one]);
armAsm->Ldr(Fs, armMemOperandPtr(mVUglob.one));
armAsm->Ldr(Fs, PTR_CPU(mVUglob.one));
SSE_DIVSS(mVU, Fs, xmmPQ);
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
@@ -503,7 +503,7 @@ mVUop(mVU_ERLENG)
armAsm->Fsqrt(RQSCRATCH.S(), RQSCRATCH.S());
armAsm->Mov(xmmPQ.S(), 0, RQSCRATCH.S(), 0);
// xMOVSSZX (Fs, ptr32[mVUglob.one]);
armAsm->Ldr(Fs, armMemOperandPtr(mVUglob.one));
armAsm->Ldr(Fs, PTR_CPU(mVUglob.one));
SSE_DIVSS (mVU, Fs, xmmPQ);
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
@@ -533,7 +533,7 @@ mVUop(mVU_ERSADD)
armPSHUFD(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6);
mVU_sumXYZ(mVU, xmmPQ, Fs);
// xMOVSSZX (Fs, ptr32[mVUglob.one]);
armAsm->Ldr(Fs, armMemOperandPtr(mVUglob.one));
armAsm->Ldr(Fs, PTR_CPU(mVUglob.one));
SSE_DIVSS (mVU, Fs, xmmPQ);
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
@@ -562,11 +562,11 @@ mVUop(mVU_ERSQRT)
// xPSHUF.D (xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
armPSHUFD(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6);
// xAND.PS (Fs, ptr128[mVUglob.absclip]);
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.absclip).V16B());
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.absclip)).V16B());
// xSQRT.SS (xmmPQ, Fs);
armAsm->Fsqrt(xmmPQ.S(), Fs.S());
// xMOVSSZX (Fs, ptr32[mVUglob.one]);
armAsm->Ldr(Fs, armMemOperandPtr(mVUglob.one));
armAsm->Ldr(Fs, PTR_CPU(mVUglob.one));
SSE_DIVSS(mVU, Fs, xmmPQ);
// xMOVSS (xmmPQ, Fs);
armAsm->Mov(xmmPQ.S(), 0, Fs.S(), 0);
@@ -630,26 +630,26 @@ mVUop(mVU_ESIN)
// xMOVAPS (t2, Fs); // t2 = X^3
armAsm->Mov(t2, Fs);
// xMUL.SS (Fs, ptr32[mVUglob.S2]); // fs = s2 * X^3
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(mVUglob.S2).S());
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(PTR_CPU(mVUglob.S2)).S());
SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3
SSE_MULSS(mVU, t2, t1); // t2 = X^3 * X^2
// xMOVAPS (Fs, t2); // fs = X^5
armAsm->Mov(Fs, t2);
// xMUL.SS (Fs, ptr32[mVUglob.S3]); // ps = s3 * X^5
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(mVUglob.S3).S());
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(PTR_CPU(mVUglob.S3)).S());
SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3 + s3 * X^5
SSE_MULSS(mVU, t2, t1); // t2 = X^5 * X^2
// xMOVAPS (Fs, t2); // fs = X^7
armAsm->Mov(Fs, t2);
// xMUL.SS (Fs, ptr32[mVUglob.S4]); // fs = s4 * X^7
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(mVUglob.S4).S());
armAsm->Fmul(Fs.S(), Fs.S(), armLoadPtrV(PTR_CPU(mVUglob.S4)).S());
SSE_ADDSS(mVU, xmmPQ, Fs); // pq = X + s2 * X^3 + s3 * X^5 + s4 * X^7
SSE_MULSS(mVU, t2, t1); // t2 = X^7 * X^2
// xMUL.SS (t2, ptr32[mVUglob.S5]); // t2 = s5 * X^9
armAsm->Fmul(t2.S(), t2.S(), armLoadPtrV(mVUglob.S5).S());
armAsm->Fmul(t2.S(), t2.S(), armLoadPtrV(PTR_CPU(mVUglob.S5)).S());
SSE_ADDSS(mVU, xmmPQ, t2); // pq = X + s2 * X^3 + s3 * X^5 + s4 * X^7 + s5 * X^9
// xPSHUF.D (xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6); // Flip back
armPSHUFD(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6);
@@ -678,7 +678,7 @@ mVUop(mVU_ESQRT)
// xPSHUF.D(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
armPSHUFD(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6);
// xAND.PS (Fs, ptr128[mVUglob.absclip]);
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.absclip).V16B());
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.absclip)).V16B());
// xSQRT.SS(xmmPQ, Fs);
armAsm->Fsqrt(xmmPQ.S(), Fs.S());
// xPSHUF.D(xmmPQ, xmmPQ, mVUinfo.writeP ? 0x27 : 0xC6); // Flip back
app/src/main/cpp/pcsx2/x86/microVU_Misc.h
+1 -39
View File
@@ -16,45 +16,7 @@ struct microVU;
// Global Variables
//------------------------------------------------------------------
struct mVU_Globals
{
#define __four(val) { val, val, val, val }
u32 absclip [4] = __four(0x7fffffff);
u32 signbit [4] = __four(0x80000000);
u32 minvals [4] = __four(0xff7fffff);
u32 maxvals [4] = __four(0x7f7fffff);
u32 exponent[4] = __four(0x7f800000);
u32 one [4] = __four(0x3f800000);
u32 Pi4 [4] = __four(0x3f490fdb);
u32 T1 [4] = __four(0x3f7ffff5);
u32 T5 [4] = __four(0xbeaaa61c);
u32 T2 [4] = __four(0x3e4c40a6);
u32 T3 [4] = __four(0xbe0e6c63);
u32 T4 [4] = __four(0x3dc577df);
u32 T6 [4] = __four(0xbd6501c4);
u32 T7 [4] = __four(0x3cb31652);
u32 T8 [4] = __four(0xbb84d7e7);
u32 S2 [4] = __four(0xbe2aaaa4);
u32 S3 [4] = __four(0x3c08873e);
u32 S4 [4] = __four(0xb94fb21f);
u32 S5 [4] = __four(0x362e9c14);
u32 E1 [4] = __four(0x3e7fffa8);
u32 E2 [4] = __four(0x3d0007f4);
u32 E3 [4] = __four(0x3b29d3ff);
u32 E4 [4] = __four(0x3933e553);
u32 E5 [4] = __four(0x36b63510);
u32 E6 [4] = __four(0x353961ac);
u32 I32MAXF [4] = __four(0x4effffff);
float FTOI_4 [4] = __four(16.0);
float FTOI_12 [4] = __four(4096.0);
float FTOI_15 [4] = __four(32768.0);
float ITOF_4 [4] = __four(0.0625f);
float ITOF_12 [4] = __four(0.000244140625);
float ITOF_15 [4] = __four(0.000030517578125);
#undef __four
};
alignas(32) static constexpr struct mVU_Globals mVUglob;
//alignas(32) static constexpr struct mVU_Globals mVUglob;
static const uint _Ibit_ = 1 << 31;
static const uint _Ebit_ = 1 << 30;
app/src/main/cpp/pcsx2/x86/microVU_Misc.inl
+5 -11
View File
@@ -401,19 +401,13 @@ __fi void mVUaddrFix(mV, const a64::Register& gprReg)
}
// xAND(xRegister32(gprReg.Id), 0x3f); // ToDo: theres a potential problem if VU0 overrides VU1's VF0/VI0 regs!
armAsm->And(reg32, reg32, 0x3f);
// xADD(gprReg, (u128*)VU1.VF - (u128*)VU0.Mem);
a64::MemOperand mop1 = PTR_CPU(vuRegs[1].VF);
a64::MemOperand mop2 = PTR_CPU(vuRegs[0].Mem);
armAsm->Sub(REX, mop1.GetBaseRegister(), mop2.GetBaseRegister());
armAsm->Add(gprReg, gprReg, REX);
// armAsm->Ldr(RAX, PTR_CPU(vuRegs[0].Mem));
// armAsm->Add(gprReg, gprReg, EEX);
// armAsm->Ldr(RCX, PTR_CPU(vuRegs[1].VF));
// armAsm->Sub(gprReg, gprReg, EEX);
// PTR_CPU(vuRegs[0].Mem);
// armAsm->Sub(REX, RCX, RAX);
// armAsm->Add(gprReg, gprReg, REX);
armAsm->Add(gprReg, gprReg, (u128*)VU1.VF - (u128*)VU0.Mem);
// jmpB.SetTarget();
armBind(&jmpB);
// xSHL(gprReg, 4); // multiply by 16 (shift left by 4)
app/src/main/cpp/pcsx2/x86/microVU_Upper.inl
+19 -17
View File
@@ -454,7 +454,7 @@ mVUop(mVU_ABS)
return;
const xmm& Fs = mVU.regAlloc->allocReg(_Fs_, _Ft_, _X_Y_Z_W, !((_Fs_ == _Ft_) && (_X_Y_Z_W == 0xf)));
// xAND.PS(Fs, ptr128[mVUglob.absclip]);
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(mVUglob.absclip).V16B());
armAsm->And(Fs.V16B(), Fs.V16B(), armLoadPtrV(PTR_CPU(mVUglob.absclip)).V16B());
mVU.regAlloc->clearNeeded(Fs);
mVU.profiler.EmitOp(opABS);
}
@@ -525,7 +525,8 @@ mVUop(mVU_OPMSUB)
}
// FTOI0/FTIO4/FTIO12/FTIO15 Opcodes
static void mVU_FTOIx(mP, const float* addr, microOpcode opEnum)
//static void mVU_FTOIx(mP, const float* addr, microOpcode opEnum)
static void mVU_FTOIx(mP, const a64::MemOperand& addr, microOpcode opEnum)
{
pass1 { mVUanalyzeFMAC2(mVU, _Fs_, _Ft_); }
pass2
@@ -538,14 +539,14 @@ static void mVU_FTOIx(mP, const float* addr, microOpcode opEnum)
// cvttps2dq returns 0x8000000 for any unrepresentable values.
// We want it to return 0x8000000 for negative and 0x7fffffff for positive.
// So for unrepresentable positive values, xor with 0xffffffff to turn 0x80000000 into 0x7fffffff.
if (addr) {
if (addr.IsValid()) {
// xMUL.PS(Fs, ptr128[addr]);
armAsm->Fmul(Fs.V4S(), Fs.V4S(), armLoadPtrV(addr).V4S());
}
// xMOVAPS(t1, Fs);
armAsm->Mov(t1.Q(), Fs.Q());
// xPCMP.GTD(t1, ptr128[mVUglob.I32MAXF]);
armAsm->Cmgt(t1.V4S(), t1.V4S(), armLoadPtrV(mVUglob.I32MAXF).V4S());
armAsm->Cmgt(t1.V4S(), t1.V4S(), armLoadPtrV(PTR_CPU(mVUglob.I32MAXF)).V4S());
// xCVTTPS2DQ(Fs, Fs);
armAsm->Fcvtzs(Fs.V4S(), Fs.V4S());
// xPXOR(Fs, t1);
@@ -563,7 +564,8 @@ static void mVU_FTOIx(mP, const float* addr, microOpcode opEnum)
}
// ITOF0/ITOF4/ITOF12/ITOF15 Opcodes
static void mVU_ITOFx(mP, const float* addr, microOpcode opEnum)
//static void mVU_ITOFx(mP, const float* addr, microOpcode opEnum)
static void mVU_ITOFx(mP, const a64::MemOperand& addr, microOpcode opEnum)
{
pass1 { mVUanalyzeFMAC2(mVU, _Fs_, _Ft_); }
pass2
@@ -574,7 +576,7 @@ static void mVU_ITOFx(mP, const float* addr, microOpcode opEnum)
// xCVTDQ2PS(Fs, Fs);
armAsm->Scvtf(Fs.V4S(), Fs.V4S());
if (addr) {
if (addr.IsValid()) {
// xMUL.PS(Fs, ptr128[addr]);
armAsm->Fmul(Fs.V4S(), Fs.V4S(), armLoadPtrV(addr).V4S());
}
@@ -607,7 +609,7 @@ mVUop(mVU_CLIP)
armAsm->Lsl(gprT1, gprT1, 6);
// xMOVAPS (t1, ptr128[mVUglob.exponent]);
armAsm->Ldr(t1, armMemOperandPtr(mVUglob.exponent));
armAsm->Ldr(t1, PTR_CPU(mVUglob.exponent));
// xPAND (t1, Fs);
armAsm->And(t1.V16B(), t1.V16B(), Fs.V16B());
// xPXOR (t2, t2);
@@ -617,10 +619,10 @@ mVUop(mVU_CLIP)
// xPANDN (t1, Fs); // If denormal, set to zero, which can't be greater than any nonnegative denormal in Ft
armAsm->Bic(t1.V16B(), Fs.V16B(), t1.V16B());
// xPAND (Ft, ptr128[mVUglob.absclip]);
armAsm->And(Ft.V16B(), Ft.V16B(), armLoadPtrV(mVUglob.absclip).V16B());
armAsm->And(Ft.V16B(), Ft.V16B(), armLoadPtrV(PTR_CPU(mVUglob.absclip)).V16B());
// xMOVAPS (Fs, ptr128[mVUglob.signbit]);
armAsm->Ldr(Fs, armMemOperandPtr(mVUglob.signbit));
armAsm->Ldr(Fs, PTR_CPU(mVUglob.signbit));
// xPXOR (Fs, t1); // Negate
armAsm->Eor(Fs.V16B(), Fs.V16B(), t1.V16B());
// xPCMP.GTD(t1, Ft); // +w, +z, +y, +x
@@ -741,12 +743,12 @@ mVUop(mVU_MINIx) { mVU_FMACa(mVU, recPass, 2, 4, false, opMINIx, 0); }
mVUop(mVU_MINIy) { mVU_FMACa(mVU, recPass, 2, 4, false, opMINIy, 0); }
mVUop(mVU_MINIz) { mVU_FMACa(mVU, recPass, 2, 4, false, opMINIz, 0); }
mVUop(mVU_MINIw) { mVU_FMACa(mVU, recPass, 2, 4, false, opMINIw, 0); }
mVUop(mVU_FTOI0) { mVU_FTOIx(mX, NULL, opFTOI0); }
mVUop(mVU_FTOI4) { mVU_FTOIx(mX, mVUglob.FTOI_4, opFTOI4); }
mVUop(mVU_FTOI12) { mVU_FTOIx(mX, mVUglob.FTOI_12, opFTOI12); }
mVUop(mVU_FTOI15) { mVU_FTOIx(mX, mVUglob.FTOI_15, opFTOI15); }
mVUop(mVU_ITOF0) { mVU_ITOFx(mX, NULL, opITOF0); }
mVUop(mVU_ITOF4) { mVU_ITOFx(mX, mVUglob.ITOF_4, opITOF4); }
mVUop(mVU_ITOF12) { mVU_ITOFx(mX, mVUglob.ITOF_12, opITOF12); }
mVUop(mVU_ITOF15) { mVU_ITOFx(mX, mVUglob.ITOF_15, opITOF15); }
mVUop(mVU_FTOI0) { mVU_FTOIx(mX, a64::MemOperand(), opFTOI0); }
mVUop(mVU_FTOI4) { mVU_FTOIx(mX, PTR_CPU(mVUglob.FTOI_4), opFTOI4); }
mVUop(mVU_FTOI12) { mVU_FTOIx(mX, PTR_CPU(mVUglob.FTOI_12), opFTOI12); }
mVUop(mVU_FTOI15) { mVU_FTOIx(mX, PTR_CPU(mVUglob.FTOI_15), opFTOI15); }
mVUop(mVU_ITOF0) { mVU_ITOFx(mX, a64::MemOperand(), opITOF0); }
mVUop(mVU_ITOF4) { mVU_ITOFx(mX, PTR_CPU(mVUglob.ITOF_4), opITOF4); }
mVUop(mVU_ITOF12) { mVU_ITOFx(mX, PTR_CPU(mVUglob.ITOF_12), opITOF12); }
mVUop(mVU_ITOF15) { mVU_ITOFx(mX, PTR_CPU(mVUglob.ITOF_15), opITOF15); }
mVUop(mVU_NOP) { pass2 { mVU.profiler.EmitOp(opNOP); } pass3 { mVUlog("NOP"); } }