izzy/PCSX2_ARM64
0
0
Fork 0
mirror of https://github.com/izzy2lost/PCSX2_ARM64.git synced 2026-06-19 10:16:23 -07:00
Code Issues Packages Projects Releases Wiki Activity

Android project - Modify iCOP0.cpp, recVTLB.cpp code

Browse Source
This commit is contained in:
k2154
2025-08-21 00:18:25 +09:00
parent e3b71c4611
commit ef4fe46def
2 changed files with 18 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
app/src/main/cpp/pcsx2/x86/iCOP0.cpp
+4 -4
View File
@@ -42,15 +42,15 @@ static void _setupBranchTest()
// everything except the lower 10 bits away.
// xMOV(eax, ptr[(&psHu32(DMAC_PCR))]);
armAsm->Ldr(RXVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_PCR)));
armAsm->Uxtw(EAX, RXVIXLSCRATCH);
armAsm->Ldr(RWVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_PCR)));
armAsm->Uxtw(EAX, RWVIXLSCRATCH);
// xMOV(ecx, 0x3ff); // ECX is our 10-bit mask var
armAsm->Mov(ECX, 0x3ff);
// xNOT(eax);
armAsm->Mvn(EAX, EAX);
// xOR(eax, ptr[(&psHu32(DMAC_STAT))]);
armAsm->Ldr(RXVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_STAT)));
armAsm->Orr(EAX, EAX, a64::Operand(RXVIXLSCRATCH, a64::Extend::UXTW));
armAsm->Ldr(RWVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(DMAC_STAT)));
armAsm->Orr(EAX, EAX, a64::Operand(RWVIXLSCRATCH, a64::Extend::UXTW));
// xAND(eax, ecx);
armAsm->And(EAX, EAX, ECX);
// xCMP(eax, ecx);
app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp
+14 -17
View File
@@ -166,7 +166,6 @@ namespace vtlb_private
// xSHR(eax, VTLB_PAGE_BITS);
armAsm->Lsr(EAX, EAX, VTLB_PAGE_BITS);
// xMOV(rax, ptrNative[xComplexAddress(arg3reg, vtlbdata.vmap, rax * wordsize)]);
// armMoveAddressToReg(RXVIXLSCRATCH, vtlbdata.vmap);
armAsm->Ldr(RXVIXLSCRATCH, PTR_CPU(vtlbdata.vmap));
armAsm->Ldr(RAX, a64::MemOperand(RXVIXLSCRATCH, RAX, a64::LSL, 3));
// xADD(arg1reg, rax);
@@ -324,7 +323,6 @@ static void DynGen_IndirectTlbDispatcher(int mode, int bits, bool sign)
xSUB(rsp, 32 + 8);
#else
// xSUB(rsp, 8);
// armAsm->Sub(a64::sp, a64::sp, 48);
armAsm->Push(a64::xzr, a64::lr);
#endif
@@ -386,7 +384,6 @@ static void DynGen_IndirectTlbDispatcher(int mode, int bits, bool sign)
xADD(rsp, 32 + 8);
#else
// xADD(rsp, 8);
// armAsm->Add(a64::sp, a64::sp, 48);
armAsm->Pop(a64::lr, a64::xzr);
#endif
@@ -470,7 +467,8 @@ int vtlb_DynGenReadNonQuad(u32 bits, bool sign, bool xmm, int addr_reg, vtlb_Rea
const u8* codeStart;
// const xAddressReg x86addr(addr_reg);
a64::MemOperand x86addr = a64::MemOperand(RFASTMEMBASE, a64::XRegister(addr_reg));
const a64::XRegister x86addr(addr_reg);
auto mop = a64::MemOperand(RFASTMEMBASE, x86addr);
if (!xmm)
{
@@ -485,19 +483,19 @@ int vtlb_DynGenReadNonQuad(u32 bits, bool sign, bool xmm, int addr_reg, vtlb_Rea
{
case 8:
// sign ? xMOVSX(x86reg, ptr8[RFASTMEMBASE + x86addr]) : xMOVZX(xRegister32(x86reg), ptr8[RFASTMEMBASE + x86addr]);
sign ? armAsm->Ldrsb(x86reg, x86addr) : armAsm->Ldrb(x86reg.W(), x86addr);
sign ? armAsm->Ldrsb(x86reg, mop) : armAsm->Ldrb(x86reg.W(), mop);
break;
case 16:
// sign ? xMOVSX(x86reg, ptr16[RFASTMEMBASE + x86addr]) : xMOVZX(xRegister32(x86reg), ptr16[RFASTMEMBASE + x86addr]);
sign ? armAsm->Ldrsh(x86reg, x86addr) : armAsm->Ldrh(x86reg.W(), x86addr);
sign ? armAsm->Ldrsh(x86reg, mop) : armAsm->Ldrh(x86reg.W(), mop);
break;
case 32:
// sign ? xMOVSX(x86reg, ptr32[RFASTMEMBASE + x86addr]) : xMOV(xRegister32(x86reg), ptr32[RFASTMEMBASE + x86addr]);
sign ? armAsm->Ldrsw(x86reg, x86addr) : armAsm->Ldr(x86reg.W(), x86addr);
sign ? armAsm->Ldrsw(x86reg, mop) : armAsm->Ldr(x86reg.W(), mop);
break;
case 64:
// xMOV(x86reg, ptr64[RFASTMEMBASE + x86addr]);
armAsm->Ldr(x86reg, x86addr);
armAsm->Ldr(x86reg, mop);
break;
jNO_DEFAULT
@@ -512,7 +510,7 @@ int vtlb_DynGenReadNonQuad(u32 bits, bool sign, bool xmm, int addr_reg, vtlb_Rea
// const xRegisterSSE xmmreg(x86_dest_reg);
const a64::QRegister xmmreg(x86_dest_reg);
// xMOVSSZX(xmmreg, ptr32[RFASTMEMBASE + x86addr]);
armAsm->Ldr(xmmreg.S(), x86addr);
armAsm->Ldr(xmmreg.S(), mop);
}
// vtlb_AddLoadStoreInfo((uptr)codeStart, static_cast<u32>(x86Ptr - codeStart),
@@ -602,9 +600,7 @@ int vtlb_DynGenReadNonQuad_Const(u32 bits, bool sign, bool xmm, u32 addr_const,
// Shortcut for the INTC_STAT register, which many games like to spin on heavily.
if ((bits == 32) && !EmuConfig.Speedhacks.IntcStat && (paddr == INTC_STAT))
{
// armAsm->Ldr(RXVIXLSCRATCH, (uptr)&psHu32(INTC_STAT));
// auto mop = a64::MemOperand(RXVIXLSCRATCH);
auto mop = armMemOperandPtr(&psHu32(INTC_STAT));
armAsm->Ldr(RWVIXLSCRATCH, a64::MemOperand(RSTATE_x26, psHu(INTC_STAT)));
// x86_dest_reg = dest_reg_alloc ? dest_reg_alloc() : (_freeX86reg(eax), eax.GetId());
x86_dest_reg = dest_reg_alloc ? dest_reg_alloc() : (_freeX86reg(EAX), EAX.GetCode());
@@ -613,17 +609,18 @@ int vtlb_DynGenReadNonQuad_Const(u32 bits, bool sign, bool xmm, u32 addr_const,
auto regX = a64::XRegister(x86_dest_reg);
if (sign) {
// xMOVSX(xRegister64(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]);
armAsm->Ldrsw(regX, mop);
armAsm->Sxtw(regX, RWVIXLSCRATCH);
}
else {
// xMOV(xRegister32(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]);
armAsm->Ldr(regX.W(), mop);
armAsm->Uxtw(regX.W(), RWVIXLSCRATCH);
}
}
else
{
// xMOVDZX(xRegisterSSE(x86_dest_reg), ptr32[&psHu32(INTC_STAT)]);
armAsm->Ldr(a64::QRegister(x86_dest_reg).S(), mop);
armAsm->Uxtw(RWVIXLSCRATCH, RWVIXLSCRATCH);
armAsm->Fmov(a64::QRegister(x86_dest_reg).S(), RWVIXLSCRATCH);
}
}
else
@@ -831,7 +828,8 @@ void vtlb_DynGenWrite(u32 sz, bool xmm, int addr_reg, int value_reg)
const u8* codeStart = armGetCurrentCodePointer();
// const xAddressReg vaddr_reg(addr_reg);
const a64::MemOperand mop = a64::MemOperand(RFASTMEMBASE, a64::XRegister(addr_reg));
const a64::XRegister vaddr_reg(addr_reg);
auto mop = a64::MemOperand(RFASTMEMBASE, vaddr_reg);
if (!xmm)
{
@@ -1090,7 +1088,6 @@ void vtlb_DynV2P()
// xSHR(eax, VTLB_PAGE_BITS);
armAsm->Lsr(EAX, EAX, VTLB_PAGE_BITS);
// xMOV(eax, ptr[xComplexAddress(rdx, vtlbdata.ppmap, rax * 4)]);
// armMoveAddressToReg(RDX, vtlbdata.ppmap);
armAsm->Ldr(RXVIXLSCRATCH, PTR_CPU(vtlbdata.ppmap));
armAsm->Ldr(EAX, a64::MemOperand(RXVIXLSCRATCH, RAX, a64::LSL, 2));