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Android project - Applying LOADSTORE_RECOMPILE will improve game fps

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This commit is contained in:
k2154
2025-07-25 03:57:20 +09:00
parent f137a57983
commit 5607eaa312
8 changed files with 949 additions and 430 deletions
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app/src/main/cpp/common/arm64/AsmHelpers.cpp
+3 -2
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@@ -333,6 +333,7 @@ bool armIsCalleeSavedRegister(int reg)
bool armIsCallerSaved(int id)
{
#if defined(__ANDROID__)
// gpr registers callee saved => r19 ~ r28
// 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
return (id <= 15);
#else
@@ -349,9 +350,9 @@ bool armIsCallerSaved(int id)
bool armIsCallerSavedXmm(int id)
{
#if defined(__ANDROID__)
// v9,v10,v11,v12,v13,v14,v15
// vector registers callee saved => d8 ~ d15
// d9,d10,d11,d12,d13,d14,d15
return (id < 9);
// return true;
#else
#ifdef _WIN32
// XMM6 through XMM15 are saved. Upper 128 bits is always volatile.
app/src/main/cpp/common/arm64/AsmHelpers.h
+1 -16
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@@ -13,10 +13,6 @@
namespace a64 = vixl::aarch64;
#define RWRET a64::w0
#define RXRET a64::x0
#define RQRET a64::q0
#define RWARG1 a64::w0
#define RWARG2 a64::w1
#define RWARG3 a64::w2
@@ -40,29 +36,17 @@ namespace a64 = vixl::aarch64;
#define RDSCRATCH3 a64::d29
#define RSSCRATCH3 a64::s29
#define RQSCRATCHI a64::VRegister(30, 128, 16)
#define RQSCRATCHF a64::VRegister(30, 128, 4)
#define RQSCRATCHD a64::VRegister(30, 128, 2)
#define RQSCRATCH2I a64::VRegister(31, 128, 16)
#define RQSCRATCH2F a64::VRegister(31, 128, 4)
#define RQSCRATCH2D a64::VRegister(31, 128, 2)
#define EAX a64::w0
#define ECX a64::w1
#define EDX a64::w2
#define EBX a64::w3
#define EEX a64::w4
#define E5X a64::w5
#define E8X a64::w8
#define RAX a64::x0
#define RCX a64::x1
#define RDX a64::x2
#define RBX a64::x3
#define REX a64::x4
#define R5X a64::x5
#define R8X a64::x8
#define RSTATE_x19 a64::x19
#define RSTATE_x20 a64::x20
@@ -71,6 +55,7 @@ namespace a64 = vixl::aarch64;
#define RSTATE_x23 a64::x23
#define RSTATE_x24 a64::x24
#define RFASTMEMBASE a64::x25
#define RSTATE_x26 a64::x26
#define RSTATE_FPU a64::x27
#define RSTATE_PSX a64::x28
#define RSTATE_CPU a64::x29
app/src/main/cpp/pcsx2/Config.h
+1 -1
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@@ -1452,7 +1452,7 @@ namespace EmuFolders
#define ARITHMETIC_RECOMPILE
#define MULTDIV_RECOMPILE
#define JUMP_RECOMPILE
//#define LOADSTORE_RECOMPILE
#define LOADSTORE_RECOMPILE
#define MOVE_RECOMPILE
//#define MMI_RECOMPILE
//#define MMI0_RECOMPILE
app/src/main/cpp/pcsx2/x86/ix86-32/iR5900.cpp
+3 -1
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@@ -652,12 +652,14 @@ static void recResetRaw()
EE::Profiler.Reset();
// recVTLB => iR5900LoadStore
vtlb_DynGenDispatchers();
// xSetPtr(SysMemory::GetEERec());
armSetAsmPtr(recPtr, recPtrEnd - recPtr, nullptr);
armStartBlock();
_DynGen_Dispatchers();
// vtlb_DynGenDispatchers();
// recPtr = xGetPtr();
recPtr = armEndBlock();
app/src/main/cpp/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
+646 -296
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File diff suppressed because it is too large Load Diff
app/src/main/cpp/pcsx2/x86/ix86-32/recVTLB.cpp
+272 -101
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File diff suppressed because it is too large Load Diff
app/src/main/cpp/pcsx2/x86/microVU_Macro.inl
+21 -11
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@@ -928,7 +928,7 @@ namespace Dynarec {
namespace OpcodeImpl {
void recCOP2() { recCOP2t[_Rs_](); }
#if defined(LOADSTORE_RECOMPILE2) && defined(CP2_RECOMPILE)
#if defined(LOADSTORE_RECOMPILE) && defined(CP2_RECOMPILE)
/*********************************************************
* Load and store for COP2 (VU0 unit) *
@@ -958,11 +958,15 @@ void recLQC2()
else
{
_eeMoveGPRtoR(arg1regd, _Rs_);
if (_Imm_ != 0)
xADD(arg1regd, _Imm_);
xAND(arg1regd, ~0xF);
if (_Imm_ != 0) {
// xADD(arg1regd, _Imm_);
armAsm->Add(ECX, ECX, _Imm_);
}
// xAND(arg1regd, ~0xF);
armAsm->And(ECX, ECX, ~0xF);
xmmreg = vtlb_DynGenReadQuad(128, arg1regd.GetId(), alloc_cb);
// xmmreg = vtlb_DynGenReadQuad(128, arg1regd.GetId(), alloc_cb);
xmmreg = vtlb_DynGenReadQuad(128, ECX.GetCode(), alloc_cb);
}
// toss away if loading to vf00
@@ -983,8 +987,10 @@ void recSQC2()
// vf00 has to be special cased here, because of the microvu temps...
const int ftreg = _Rt_ ? _allocVFtoXMMreg(_Rt_, MODE_READ) : _allocTempXMMreg(XMMT_FPS);
if (!_Rt_)
xMOVAPS(xRegisterSSE(ftreg), ptr128[&vu0Regs.VF[0].F]);
if (!_Rt_) {
// xMOVAPS(xRegisterSSE(ftreg), ptr128[&vu0Regs.VF[0].F]);
armAsm->Ldr(a64::QRegister(ftreg).Q(), armMemOperandPtr(&vu0Regs.VF[0].F));
}
if (GPR_IS_CONST1(_Rs_))
{
@@ -994,11 +1000,15 @@ void recSQC2()
else
{
_eeMoveGPRtoR(arg1regd, _Rs_);
if (_Imm_ != 0)
xADD(arg1regd, _Imm_);
xAND(arg1regd, ~0xF);
if (_Imm_ != 0) {
// xADD(arg1regd, _Imm_);
armAsm->Add(ECX, ECX, _Imm_);
}
// xAND(arg1regd, ~0xF);
armAsm->And(ECX, ECX, ~0xF);
vtlb_DynGenWrite(128, true, arg1regd.GetId(), ftreg);
// vtlb_DynGenWrite(128, true, arg1regd.GetId(), ftreg);
vtlb_DynGenWrite(128, true, ECX.GetCode(), ftreg);
}
if (!_Rt_)
app/src/main/cpp/pcsx2/x86/microVU_Misc.inl
+2 -2
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@@ -293,7 +293,7 @@ __fi void mVUrestoreRegs(microVU& mVU, bool fromMemory = false, bool onlyNeeded
if (fromMemory)
{
int i;
for (i = 0; i < static_cast<int>(iREGCNT_XMM); ++i)
for (i = static_cast<int>(iREGCNT_XMM - 1); i >= 0; --i)
{
if (!armIsCallerSavedXmm(i))
continue;
@@ -303,7 +303,7 @@ __fi void mVUrestoreRegs(microVU& mVU, bool fromMemory = false, bool onlyNeeded
}
}
for (i = 0; i < static_cast<int>(iREGCNT_GPR); ++i)
for (i = static_cast<int>(iREGCNT_GPR - 1); i >= 0; --i)
{
if (!armIsCallerSaved(i) || i == 4)
continue;