mirror of
https://github.com/izzy2lost/Diddy-Kong-Racing.git
synced 2026-06-19 01:16:26 -07:00
Identified some of the changes to OSSched that Rare has done. *almost* matched what might be the retrace function and might not be
This commit is contained in:
Ryan Myers
+72
-72
@@ -52,17 +52,17 @@
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0x0800_0000 .. 0x0fff_ffff cartridge domain 2
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0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
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0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
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0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
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0x1fc0_0800 .. 0x1fcf_ffff Reserved
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0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
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0x8000_0000 .. 0xffff_ffff external SysAD device
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0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
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0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
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0x1fc0_0800 .. 0x1fcf_ffff Reserved
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0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
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0x8000_0000 .. 0xffff_ffff external SysAD device
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The Indy development board use cartridge domain 1:
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0x1000_0000 .. 0x10ff_ffff RAMROM
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0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
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0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
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0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
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0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
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0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
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0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
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@@ -109,9 +109,9 @@ The Indy development board use cartridge domain 1:
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#define RDRAM_0_DEVICE_ID 0
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#define RDRAM_1_DEVICE_ID 1
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#define RDRAM_RESET_MODE 0
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#define RDRAM_ACTIVE_MODE 1
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#define RDRAM_STANDBY_MODE 2
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#define RDRAM_RESET_MODE 0
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#define RDRAM_ACTIVE_MODE 1
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#define RDRAM_STANDBY_MODE 2
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#define RDRAM_LENGTH (2*512*2048)
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#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
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@@ -125,7 +125,7 @@ The Indy development board use cartridge domain 1:
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/*************************************************************************
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* PIF Physical memory map (total size = 2 KB)
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*
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* Size Description Mode
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* Size Description Mode
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* 1FC007FF +-------+-----------------+-----+
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* | 64 B | JoyChannel RAM | R/W |
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* 1FC007C0 +-------+-----------------+-----+
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@@ -177,7 +177,7 @@ The Indy development board use cartridge domain 1:
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/* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
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#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
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/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
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#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
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@@ -212,31 +212,31 @@ The Indy development board use cartridge domain 1:
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/*
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* Values to clear/set bit in status reg (SP_STATUS_REG - write)
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*/
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#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
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#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
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#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
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#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
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#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
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#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
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#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
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#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
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#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
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#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
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#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
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#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
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#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
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#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
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#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
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#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
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#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
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#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
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#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
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#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
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#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
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#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
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#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
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#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
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#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
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#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
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#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
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#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
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#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
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#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
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#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
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#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
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#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
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#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
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#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
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#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
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#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
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#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
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#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
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#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
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#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
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#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
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#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
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#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
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#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
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#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
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#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
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#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
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#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
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#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
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/*
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* Patterns to interpret status reg (SP_STATUS_REG - read)
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@@ -253,28 +253,28 @@ The Indy development board use cartridge domain 1:
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#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
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#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
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#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
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#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
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#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
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#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
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#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
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#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
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#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
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/*
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* Use of SIG bits
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*/
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#define SP_CLR_YIELD SP_CLR_SIG0
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#define SP_SET_YIELD SP_SET_SIG0
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#define SP_STATUS_YIELD SP_STATUS_SIG0
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#define SP_CLR_YIELDED SP_CLR_SIG1
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#define SP_SET_YIELDED SP_SET_SIG1
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#define SP_STATUS_YIELDED SP_STATUS_SIG1
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#define SP_CLR_TASKDONE SP_CLR_SIG2
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#define SP_SET_TASKDONE SP_SET_SIG2
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#define SP_STATUS_TASKDONE SP_STATUS_SIG2
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#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
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#define SP_SET_RSPSIGNAL SP_SET_SIG3
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#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
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#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
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#define SP_SET_CPUSIGNAL SP_SET_SIG4
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#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
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#define SP_CLR_YIELD SP_CLR_SIG0 /* Bit 9 */
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#define SP_SET_YIELD SP_SET_SIG0 /* Bit 10 */
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#define SP_STATUS_YIELD SP_STATUS_SIG0 /* Bit 7 */
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#define SP_CLR_YIELDED SP_CLR_SIG1 /* Bit 11 */
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#define SP_SET_YIELDED SP_SET_SIG1 /* Bit 12 */
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#define SP_STATUS_YIELDED SP_STATUS_SIG1 /* Bit 8 */
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#define SP_CLR_TASKDONE SP_CLR_SIG2 /* Bit 13 */
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#define SP_SET_TASKDONE SP_SET_SIG2 /* Bit 14 */
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#define SP_STATUS_TASKDONE SP_STATUS_SIG2 /* Bit 9 */
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#define SP_CLR_RSPSIGNAL SP_CLR_SIG3 /* Bit 15 */
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#define SP_SET_RSPSIGNAL SP_SET_SIG3 /* Bit 16 */
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#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3 /* Bit 10 */
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#define SP_CLR_CPUSIGNAL SP_CLR_SIG4 /* Bit 17 */
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#define SP_SET_CPUSIGNAL SP_SET_SIG4 /* Bit 18 */
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#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 /* Bit 11 */
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/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
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#define SP_IBIST_REG 0x04080004
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@@ -308,13 +308,13 @@ The Indy development board use cartridge domain 1:
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#define DPC_END_REG (DPC_BASE_REG+0x04)
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/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
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#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
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#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
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/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
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#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
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/* DP clock counter (R): [23:0] clock counter */
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#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
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#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
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/* DP buffer busy counter (R): [23:0] clock counter */
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#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
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@@ -482,9 +482,9 @@ The Indy development board use cartridge domain 1:
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/* VI status/control (R/W): [15-0] valid bits:
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* [1:0] = type[1:0] (pixel size)
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* 0: blank (no data, no sync)
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* 1: reserved
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* 2: 5/5/5/3 ("16" bit)
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* 3: 8/8/8/8 (32 bit)
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* 1: reserved
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* 2: 5/5/5/3 ("16" bit)
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* 3: 8/8/8/8 (32 bit)
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* [2] = gamma_dither_enable (normally on, unless "special effect")
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* [3] = gamma_enable (normally on, unless MPEG/JPEG)
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* [4] = divot_enable (normally on if antialiased, unless decal lines)
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@@ -508,11 +508,11 @@ The Indy development board use cartridge domain 1:
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#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
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/* VI width (R/W): [11:0] frame buffer line width in pixels */
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#define VI_WIDTH_REG (VI_BASE_REG+0x08)
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#define VI_WIDTH_REG (VI_BASE_REG+0x08)
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#define VI_H_WIDTH_REG VI_WIDTH_REG
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/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
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#define VI_INTR_REG (VI_BASE_REG+0x0C)
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#define VI_INTR_REG (VI_BASE_REG+0x0C)
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#define VI_V_INTR_REG VI_INTR_REG
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/*
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@@ -520,9 +520,9 @@ The Indy development board use cartridge domain 1:
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* line (the lsb of V_CURRENT is constant within a field, and in
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* interlaced modes gives the field number - which is constant for non-
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* interlaced modes)
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* - Any write to this register will clear interrupt line
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* - Any write to this register will clear interrupt line
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*/
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#define VI_CURRENT_REG (VI_BASE_REG+0x10)
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#define VI_CURRENT_REG (VI_BASE_REG+0x10)
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#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
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/*
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@@ -531,23 +531,23 @@ The Indy development board use cartridge domain 1:
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* [19:16] vertical sync width in half lines,
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* [29:20] start of color burst in pixels from h-sync
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*/
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#define VI_BURST_REG (VI_BASE_REG+0x14)
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#define VI_BURST_REG (VI_BASE_REG+0x14)
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#define VI_TIMING_REG VI_BURST_REG
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/* VI vertical sync (R/W): [9:0] number of half-lines per field */
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#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
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#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
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/* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
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* [20:16] a 5-bit leap pattern used for PAL only
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* (h_sync_period)
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*/
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#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
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#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
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/*
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* VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
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* [27:16] identical to h_sync_period
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*/
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#define VI_LEAP_REG (VI_BASE_REG+0x20)
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#define VI_LEAP_REG (VI_BASE_REG+0x20)
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#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
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/*
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@@ -568,17 +568,17 @@ The Indy development board use cartridge domain 1:
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* VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
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* : [25:16] start of color burst enable in half-lines
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*/
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#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
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#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
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/* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
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* [27:16] horizontal subpixel offset (2.10 format)
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*/
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#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
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#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
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/* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
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* [27:16] vertical subpixel offset (2.10 format)
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*/
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#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
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#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
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/*
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* Patterns to interpret VI_CONTROL_REG
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