From e6325cbd4cc6c5898d3c2392ccb5bcd38c2c62e5 Mon Sep 17 00:00:00 2001 From: Ryan Myers Date: Fri, 8 Oct 2021 13:42:45 -0400 Subject: [PATCH] Identified some of the changes to OSSched that Rare has done. *almost* matched what might be the retrace function and might not be --- include/PR/rcp.h | 144 ++++++------- .../non_matchings/sched/__scHandleRetrace.s | 96 ++++----- lib/src/mips1/sc/sched.c | 204 ++++++++---------- lib/src/mips1/sc/sched.h | 31 ++- 4 files changed, 242 insertions(+), 233 deletions(-) diff --git a/include/PR/rcp.h b/include/PR/rcp.h index fc07e79a..99b8b60c 100644 --- a/include/PR/rcp.h +++ b/include/PR/rcp.h @@ -52,17 +52,17 @@ 0x0800_0000 .. 0x0fff_ffff cartridge domain 2 0x1000_0000 .. 0x1fbf_ffff cartridge domain 1 -0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes) -0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes) -0x1fc0_0800 .. 0x1fcf_ffff Reserved -0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1 -0x8000_0000 .. 0xffff_ffff external SysAD device +0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes) +0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes) +0x1fc0_0800 .. 0x1fcf_ffff Reserved +0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1 +0x8000_0000 .. 0xffff_ffff external SysAD device The Indy development board use cartridge domain 1: 0x1000_0000 .. 0x10ff_ffff RAMROM -0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes) -0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes) -0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes) +0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes) +0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes) +0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes) @@ -109,9 +109,9 @@ The Indy development board use cartridge domain 1: #define RDRAM_0_DEVICE_ID 0 #define RDRAM_1_DEVICE_ID 1 -#define RDRAM_RESET_MODE 0 -#define RDRAM_ACTIVE_MODE 1 -#define RDRAM_STANDBY_MODE 2 +#define RDRAM_RESET_MODE 0 +#define RDRAM_ACTIVE_MODE 1 +#define RDRAM_STANDBY_MODE 2 #define RDRAM_LENGTH (2*512*2048) #define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH) @@ -125,7 +125,7 @@ The Indy development board use cartridge domain 1: /************************************************************************* * PIF Physical memory map (total size = 2 KB) * - * Size Description Mode + * Size Description Mode * 1FC007FF +-------+-----------------+-----+ * | 64 B | JoyChannel RAM | R/W | * 1FC007C0 +-------+-----------------+-----+ @@ -177,7 +177,7 @@ The Indy development board use cartridge domain 1: /* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */ #define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */ - + /* SP DRAM DMA address (R/W): [23:0] RDRAM address */ #define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */ @@ -212,31 +212,31 @@ The Indy development board use cartridge domain 1: /* * Values to clear/set bit in status reg (SP_STATUS_REG - write) */ -#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */ -#define SP_SET_HALT 0x00002 /* Bit 1: set halt */ -#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */ -#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */ -#define SP_SET_INTR 0x00010 /* Bit 4: set intr */ -#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */ -#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */ -#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */ -#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */ -#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */ -#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */ -#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */ -#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */ -#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */ -#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */ -#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */ -#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */ -#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */ -#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */ -#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */ -#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */ -#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */ -#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */ -#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */ -#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */ +#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */ +#define SP_SET_HALT 0x00002 /* Bit 1: set halt */ +#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */ +#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */ +#define SP_SET_INTR 0x00010 /* Bit 4: set intr */ +#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */ +#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */ +#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */ +#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */ +#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */ +#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */ +#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */ +#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */ +#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */ +#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */ +#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */ +#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */ +#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */ +#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */ +#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */ +#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */ +#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */ +#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */ +#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */ +#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */ /* * Patterns to interpret status reg (SP_STATUS_REG - read) @@ -253,28 +253,28 @@ The Indy development board use cartridge domain 1: #define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */ #define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */ #define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */ -#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */ -#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */ -#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */ +#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */ +#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */ +#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */ /* * Use of SIG bits */ -#define SP_CLR_YIELD SP_CLR_SIG0 -#define SP_SET_YIELD SP_SET_SIG0 -#define SP_STATUS_YIELD SP_STATUS_SIG0 -#define SP_CLR_YIELDED SP_CLR_SIG1 -#define SP_SET_YIELDED SP_SET_SIG1 -#define SP_STATUS_YIELDED SP_STATUS_SIG1 -#define SP_CLR_TASKDONE SP_CLR_SIG2 -#define SP_SET_TASKDONE SP_SET_SIG2 -#define SP_STATUS_TASKDONE SP_STATUS_SIG2 -#define SP_CLR_RSPSIGNAL SP_CLR_SIG3 -#define SP_SET_RSPSIGNAL SP_SET_SIG3 -#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3 -#define SP_CLR_CPUSIGNAL SP_CLR_SIG4 -#define SP_SET_CPUSIGNAL SP_SET_SIG4 -#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 +#define SP_CLR_YIELD SP_CLR_SIG0 /* Bit 9 */ +#define SP_SET_YIELD SP_SET_SIG0 /* Bit 10 */ +#define SP_STATUS_YIELD SP_STATUS_SIG0 /* Bit 7 */ +#define SP_CLR_YIELDED SP_CLR_SIG1 /* Bit 11 */ +#define SP_SET_YIELDED SP_SET_SIG1 /* Bit 12 */ +#define SP_STATUS_YIELDED SP_STATUS_SIG1 /* Bit 8 */ +#define SP_CLR_TASKDONE SP_CLR_SIG2 /* Bit 13 */ +#define SP_SET_TASKDONE SP_SET_SIG2 /* Bit 14 */ +#define SP_STATUS_TASKDONE SP_STATUS_SIG2 /* Bit 9 */ +#define SP_CLR_RSPSIGNAL SP_CLR_SIG3 /* Bit 15 */ +#define SP_SET_RSPSIGNAL SP_SET_SIG3 /* Bit 16 */ +#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3 /* Bit 10 */ +#define SP_CLR_CPUSIGNAL SP_CLR_SIG4 /* Bit 17 */ +#define SP_SET_CPUSIGNAL SP_SET_SIG4 /* Bit 18 */ +#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 /* Bit 11 */ /* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */ #define SP_IBIST_REG 0x04080004 @@ -308,13 +308,13 @@ The Indy development board use cartridge domain 1: #define DPC_END_REG (DPC_BASE_REG+0x04) /* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */ -#define DPC_CURRENT_REG (DPC_BASE_REG+0x08) +#define DPC_CURRENT_REG (DPC_BASE_REG+0x08) /* DP CMD status (R/W): [9:0] valid bits - see below for definitions */ #define DPC_STATUS_REG (DPC_BASE_REG+0x0C) /* DP clock counter (R): [23:0] clock counter */ -#define DPC_CLOCK_REG (DPC_BASE_REG+0x10) +#define DPC_CLOCK_REG (DPC_BASE_REG+0x10) /* DP buffer busy counter (R): [23:0] clock counter */ #define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14) @@ -482,9 +482,9 @@ The Indy development board use cartridge domain 1: /* VI status/control (R/W): [15-0] valid bits: * [1:0] = type[1:0] (pixel size) * 0: blank (no data, no sync) - * 1: reserved - * 2: 5/5/5/3 ("16" bit) - * 3: 8/8/8/8 (32 bit) + * 1: reserved + * 2: 5/5/5/3 ("16" bit) + * 3: 8/8/8/8 (32 bit) * [2] = gamma_dither_enable (normally on, unless "special effect") * [3] = gamma_enable (normally on, unless MPEG/JPEG) * [4] = divot_enable (normally on if antialiased, unless decal lines) @@ -508,11 +508,11 @@ The Indy development board use cartridge domain 1: #define VI_DRAM_ADDR_REG VI_ORIGIN_REG /* VI width (R/W): [11:0] frame buffer line width in pixels */ -#define VI_WIDTH_REG (VI_BASE_REG+0x08) +#define VI_WIDTH_REG (VI_BASE_REG+0x08) #define VI_H_WIDTH_REG VI_WIDTH_REG /* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */ -#define VI_INTR_REG (VI_BASE_REG+0x0C) +#define VI_INTR_REG (VI_BASE_REG+0x0C) #define VI_V_INTR_REG VI_INTR_REG /* @@ -520,9 +520,9 @@ The Indy development board use cartridge domain 1: * line (the lsb of V_CURRENT is constant within a field, and in * interlaced modes gives the field number - which is constant for non- * interlaced modes) - * - Any write to this register will clear interrupt line + * - Any write to this register will clear interrupt line */ -#define VI_CURRENT_REG (VI_BASE_REG+0x10) +#define VI_CURRENT_REG (VI_BASE_REG+0x10) #define VI_V_CURRENT_LINE_REG VI_CURRENT_REG /* @@ -531,23 +531,23 @@ The Indy development board use cartridge domain 1: * [19:16] vertical sync width in half lines, * [29:20] start of color burst in pixels from h-sync */ -#define VI_BURST_REG (VI_BASE_REG+0x14) +#define VI_BURST_REG (VI_BASE_REG+0x14) #define VI_TIMING_REG VI_BURST_REG /* VI vertical sync (R/W): [9:0] number of half-lines per field */ -#define VI_V_SYNC_REG (VI_BASE_REG+0x18) +#define VI_V_SYNC_REG (VI_BASE_REG+0x18) /* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel * [20:16] a 5-bit leap pattern used for PAL only * (h_sync_period) */ -#define VI_H_SYNC_REG (VI_BASE_REG+0x1C) +#define VI_H_SYNC_REG (VI_BASE_REG+0x1C) /* * VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period * [27:16] identical to h_sync_period */ -#define VI_LEAP_REG (VI_BASE_REG+0x20) +#define VI_LEAP_REG (VI_BASE_REG+0x20) #define VI_H_SYNC_LEAP_REG VI_LEAP_REG /* @@ -568,17 +568,17 @@ The Indy development board use cartridge domain 1: * VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines * : [25:16] start of color burst enable in half-lines */ -#define VI_V_BURST_REG (VI_BASE_REG+0x2C) +#define VI_V_BURST_REG (VI_BASE_REG+0x2C) /* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format) * [27:16] horizontal subpixel offset (2.10 format) */ -#define VI_X_SCALE_REG (VI_BASE_REG+0x30) +#define VI_X_SCALE_REG (VI_BASE_REG+0x30) /* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format) * [27:16] vertical subpixel offset (2.10 format) */ -#define VI_Y_SCALE_REG (VI_BASE_REG+0x34) +#define VI_Y_SCALE_REG (VI_BASE_REG+0x34) /* * Patterns to interpret VI_CONTROL_REG diff --git a/lib/asm/non_matchings/sched/__scHandleRetrace.s b/lib/asm/non_matchings/sched/__scHandleRetrace.s index 763fee49..4fe94072 100644 --- a/lib/asm/non_matchings/sched/__scHandleRetrace.s +++ b/lib/asm/non_matchings/sched/__scHandleRetrace.s @@ -10,7 +10,7 @@ glabel __scHandleRetrace /* 07A438 80079838 8C8E0274 */ lw $t6, 0x274($a0) /* 07A43C 8007983C 00808825 */ move $s1, $a0 /* 07A440 80079840 11C00007 */ beqz $t6, .L80079860 -/* 07A444 80079844 00008025 */ move $s0, $zero +/* 07A444 80079844 00008025 */ move $s0, $zero /* 07A448 80079848 3C03800E */ lui $v1, %hi(D_800DE754) # $v1, 0x800e /* 07A44C 8007984C 2463E754 */ addiu $v1, %lo(D_800DE754) # addiu $v1, $v1, -0x18ac /* 07A450 80079850 8C6F0000 */ lw $t7, ($v1) @@ -21,7 +21,7 @@ glabel __scHandleRetrace /* 07A460 80079860 8E390278 */ lw $t9, 0x278($s1) /* 07A464 80079864 3C03800E */ lui $v1, %hi(D_800DE754) # $v1, 0x800e /* 07A468 80079868 13200006 */ beqz $t9, .L80079884 -/* 07A46C 8007986C 2463E754 */ addiu $v1, %lo(D_800DE754) # addiu $v1, $v1, -0x18ac +/* 07A46C 8007986C 2463E754 */ addiu $v1, %lo(D_800DE754) # addiu $v1, $v1, -0x18ac /* 07A470 80079870 3C08800E */ lui $t0, %hi(D_800DE758) # $t0, 0x800e /* 07A474 80079874 8D08E758 */ lw $t0, %lo(D_800DE758)($t0) /* 07A478 80079878 3C01800E */ lui $at, %hi(D_800DE758) # $at, 0x800e @@ -32,18 +32,18 @@ glabel __scHandleRetrace /* 07A488 80079888 8E220274 */ lw $v0, 0x274($s1) /* 07A48C 8007988C 2941000B */ slti $at, $t2, 0xb /* 07A490 80079890 14200009 */ bnez $at, .L800798B8 -/* 07A494 80079894 00000000 */ nop +/* 07A494 80079894 00000000 */ nop /* 07A498 80079898 10400007 */ beqz $v0, .L800798B8 -/* 07A49C 8007989C 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa +/* 07A49C 8007989C 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa /* 07A4A0 800798A0 AC600000 */ sw $zero, ($v1) /* 07A4A4 800798A4 24100001 */ li $s0, 1 /* 07A4A8 800798A8 0C033490 */ jal __osSpSetStatus -/* 07A4AC 800798AC 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82 +/* 07A4AC 800798AC 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82 /* 07A4B0 800798B0 10000005 */ b .L800798C8 -/* 07A4B4 800798B4 00000000 */ nop +/* 07A4B4 800798B4 00000000 */ nop .L800798B8: /* 07A4B8 800798B8 10400003 */ beqz $v0, .L800798C8 -/* 07A4BC 800798BC 240B0001 */ li $t3, 1 +/* 07A4BC 800798BC 240B0001 */ li $t3, 1 /* 07A4C0 800798C0 3C018012 */ lui $at, %hi(D_80126110) # $at, 0x8012 /* 07A4C4 800798C4 AC2B6110 */ sw $t3, %lo(D_80126110)($at) .L800798C8: @@ -52,16 +52,16 @@ glabel __scHandleRetrace /* 07A4D0 800798D0 8E220278 */ lw $v0, 0x278($s1) /* 07A4D4 800798D4 2981000B */ slti $at, $t4, 0xb /* 07A4D8 800798D8 14200016 */ bnez $at, .L80079934 -/* 07A4DC 800798DC 00000000 */ nop +/* 07A4DC 800798DC 00000000 */ nop /* 07A4E0 800798E0 10400014 */ beqz $v0, .L80079934 -/* 07A4E4 800798E4 00000000 */ nop +/* 07A4E4 800798E4 00000000 */ nop /* 07A4E8 800798E8 8C4D0068 */ lw $t5, 0x68($v0) /* 07A4EC 800798EC 3C05800E */ lui $a1, %hi(D_800DE738) # $a1, 0x800e /* 07A4F0 800798F0 15A00004 */ bnez $t5, .L80079904 -/* 07A4F4 800798F4 24A5E738 */ addiu $a1, %lo(D_800DE738) # addiu $a1, $a1, -0x18c8 +/* 07A4F4 800798F4 24A5E738 */ addiu $a1, %lo(D_800DE738) # addiu $a1, $a1, -0x18c8 /* 07A4F8 800798F8 8C440050 */ lw $a0, 0x50($v0) /* 07A4FC 800798FC 0C03238C */ jal osSendMesg -/* 07A500 80079900 24060001 */ li $a2, 1 +/* 07A500 80079900 24060001 */ li $a2, 1 .L80079904: /* 07A504 80079904 240E0001 */ li $t6, 1 /* 07A508 80079908 A3AE0032 */ sb $t6, 0x32($sp) @@ -70,42 +70,42 @@ glabel __scHandleRetrace /* 07A514 80079914 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa /* 07A518 80079918 AC20E758 */ sw $zero, %lo(D_800DE758)($at) /* 07A51C 8007991C 0C033490 */ jal __osSpSetStatus -/* 07A520 80079920 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82 +/* 07A520 80079920 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82 /* 07A524 80079924 0C033494 */ jal osDpSetStatus -/* 07A528 80079928 240401D6 */ li $a0, 470 +/* 07A528 80079928 240401D6 */ li $a0, 470 /* 07A52C 8007992C 10000005 */ b .L80079944 -/* 07A530 80079930 00000000 */ nop +/* 07A530 80079930 00000000 */ nop .L80079934: /* 07A534 80079934 10400003 */ beqz $v0, .L80079944 -/* 07A538 80079938 240F0001 */ li $t7, 1 +/* 07A538 80079938 240F0001 */ li $t7, 1 /* 07A53C 8007993C 3C018012 */ lui $at, %hi(D_80126114) # $at, 0x8012 /* 07A540 80079940 AC2F6114 */ sw $t7, %lo(D_80126114)($at) .L80079944: /* 07A544 80079944 12000002 */ beqz $s0, .L80079950 -/* 07A548 80079948 26240078 */ addiu $a0, $s1, 0x78 +/* 07A548 80079948 26240078 */ addiu $a0, $s1, 0x78 /* 07A54C 8007994C AE200274 */ sw $zero, 0x274($s1) .L80079950: /* 07A550 80079950 93B80032 */ lbu $t8, 0x32($sp) /* 07A554 80079954 27A50044 */ addiu $a1, $sp, 0x44 /* 07A558 80079958 13000002 */ beqz $t8, .L80079964 -/* 07A55C 8007995C 00003025 */ move $a2, $zero +/* 07A55C 8007995C 00003025 */ move $a2, $zero /* 07A560 80079960 AE200278 */ sw $zero, 0x278($s1) .L80079964: /* 07A564 80079964 0C0322EC */ jal osRecvMesg -/* 07A568 80079968 AFA40028 */ sw $a0, 0x28($sp) +/* 07A568 80079968 AFA40028 */ sw $a0, 0x28($sp) /* 07A56C 8007996C 2410FFFF */ li $s0, -1 /* 07A570 80079970 1050000A */ beq $v0, $s0, .L8007999C -/* 07A574 80079974 00000000 */ nop +/* 07A574 80079974 00000000 */ nop /* 07A578 80079978 8FA50044 */ lw $a1, 0x44($sp) .L8007997C: /* 07A57C 8007997C 0C01E7D0 */ jal __scAppendList -/* 07A580 80079980 02202025 */ move $a0, $s1 +/* 07A580 80079980 02202025 */ move $a0, $s1 /* 07A584 80079984 8FA40028 */ lw $a0, 0x28($sp) /* 07A588 80079988 27A50044 */ addiu $a1, $sp, 0x44 /* 07A58C 8007998C 0C0322EC */ jal osRecvMesg -/* 07A590 80079990 00003025 */ move $a2, $zero +/* 07A590 80079990 00003025 */ move $a2, $zero /* 07A594 80079994 1450FFF9 */ bne $v0, $s0, .L8007997C -/* 07A598 80079998 8FA50044 */ lw $a1, 0x44($sp) +/* 07A598 80079998 8FA50044 */ lw $a1, 0x44($sp) .L8007999C: /* 07A59C 8007999C 8E390274 */ lw $t9, 0x274($s1) /* 07A5A0 800799A0 8E2A0278 */ lw $t2, 0x278($s1) @@ -117,13 +117,13 @@ glabel __scHandleRetrace /* 07A5B8 800799B8 02202025 */ move $a0, $s1 /* 07A5BC 800799BC 27A50038 */ addiu $a1, $sp, 0x38 /* 07A5C0 800799C0 0C01E835 */ jal __scSchedule -/* 07A5C4 800799C4 27A60034 */ addiu $a2, $sp, 0x34 +/* 07A5C4 800799C4 27A60034 */ addiu $a2, $sp, 0x34 /* 07A5C8 800799C8 10500005 */ beq $v0, $s0, .L800799E0 -/* 07A5CC 800799CC 00000000 */ nop +/* 07A5CC 800799CC 00000000 */ nop /* 07A5D0 800799D0 8FA50038 */ lw $a1, 0x38($sp) /* 07A5D4 800799D4 8FA60034 */ lw $a2, 0x34($sp) /* 07A5D8 800799D8 0C01E7EA */ jal __scExec -/* 07A5DC 800799DC 02202025 */ move $a0, $s1 +/* 07A5DC 800799DC 02202025 */ move $a0, $s1 .L800799E0: /* 07A5E0 800799E0 3C0D800E */ lui $t5, %hi(D_800DE760) # $t5, 0x800e /* 07A5E4 800799E4 8DADE764 */ lw $t5, %lo(D_800DE760+4)($t5) @@ -138,25 +138,25 @@ glabel __scHandleRetrace /* 07A608 80079A08 AC2EE760 */ sw $t6, %lo(D_800DE760)($at) /* 07A60C 80079A0C AC2FE764 */ sw $t7, %lo(D_800DE760+4)($at) /* 07A610 80079A10 8C580000 */ lw $t8, ($v0) -/* 07A614 80079A14 00000000 */ nop +/* 07A614 80079A14 00000000 */ nop /* 07A618 80079A18 27190001 */ addiu $t9, $t8, 1 /* 07A61C 80079A1C AC590000 */ sw $t9, ($v0) /* 07A620 80079A20 8E280280 */ lw $t0, 0x280($s1) /* 07A624 80079A24 8E23027C */ lw $v1, 0x27c($s1) /* 07A628 80079A28 250A0001 */ addiu $t2, $t0, 1 /* 07A62C 80079A2C 10600019 */ beqz $v1, .L80079A94 -/* 07A630 80079A30 AE2A0280 */ sw $t2, 0x280($s1) +/* 07A630 80079A30 AE2A0280 */ sw $t2, 0x280($s1) /* 07A634 80079A34 2D410002 */ sltiu $at, $t2, 2 /* 07A638 80079A38 14200016 */ bnez $at, .L80079A94 -/* 07A63C 80079A3C 00000000 */ nop +/* 07A63C 80079A3C 00000000 */ nop /* 07A640 80079A40 8C640050 */ lw $a0, 0x50($v1) /* 07A644 80079A44 00601025 */ move $v0, $v1 /* 07A648 80079A48 10800010 */ beqz $a0, .L80079A8C -/* 07A64C 80079A4C 00000000 */ nop +/* 07A64C 80079A4C 00000000 */ nop /* 07A650 80079A50 8C6B0068 */ lw $t3, 0x68($v1) -/* 07A654 80079A54 00000000 */ nop +/* 07A654 80079A54 00000000 */ nop /* 07A658 80079A58 15600005 */ bnez $t3, .L80079A70 -/* 07A65C 80079A5C 00000000 */ nop +/* 07A65C 80079A5C 00000000 */ nop /* 07A660 80079A60 8C6C0054 */ lw $t4, 0x54($v1) /* 07A664 80079A64 3C05800E */ lui $a1, %hi(D_800DE730) # $a1, 0x800e /* 07A668 80079A68 11800006 */ beqz $t4, .L80079A84 @@ -164,12 +164,12 @@ glabel __scHandleRetrace .L80079A70: /* 07A670 80079A70 8C450054 */ lw $a1, 0x54($v0) /* 07A674 80079A74 0C03238C */ jal osSendMesg -/* 07A678 80079A78 24060001 */ li $a2, 1 +/* 07A678 80079A78 24060001 */ li $a2, 1 /* 07A67C 80079A7C 10000004 */ b .L80079A90 -/* 07A680 80079A80 AE200280 */ sw $zero, 0x280($s1) +/* 07A680 80079A80 AE200280 */ sw $zero, 0x280($s1) .L80079A84: /* 07A684 80079A84 0C03238C */ jal osSendMesg -/* 07A688 80079A88 24060001 */ li $a2, 1 +/* 07A688 80079A88 24060001 */ li $a2, 1 .L80079A8C: /* 07A68C 80079A8C AE200280 */ sw $zero, 0x280($s1) .L80079A90: @@ -178,50 +178,50 @@ glabel __scHandleRetrace /* 07A694 80079A94 8E300260 */ lw $s0, 0x260($s1) /* 07A698 80079A98 00000000 */ nop /* 07A69C 80079A9C 12000025 */ beqz $s0, .L80079B34 -/* 07A6A0 80079AA0 8FBF001C */ lw $ra, 0x1c($sp) +/* 07A6A0 80079AA0 8FBF001C */ lw $ra, 0x1c($sp) .L80079AA4: /* 07A6A4 80079AA4 92020000 */ lbu $v0, ($s0) /* 07A6A8 80079AA8 24010001 */ li $at, 1 /* 07A6AC 80079AAC 14410016 */ bne $v0, $at, .L80079B08 -/* 07A6B0 80079AB0 3C04800E */ lui $a0, %hi(D_800DE760) # $a0, 0x800e +/* 07A6B0 80079AB0 3C04800E */ lui $a0, %hi(D_800DE760) # $a0, 0x800e /* 07A6B4 80079AB4 3C05800E */ lui $a1, %hi(D_800DE760) # $a1, 0x800e /* 07A6B8 80079AB8 8CA5E764 */ lw $a1, %lo(D_800DE760+4)($a1) /* 07A6BC 80079ABC 8C84E760 */ lw $a0, %lo(D_800DE760)($a0) /* 07A6C0 80079AC0 24060000 */ li $a2, 0 /* 07A6C4 80079AC4 0C033AA3 */ jal __ull_rem -/* 07A6C8 80079AC8 24070002 */ li $a3, 2 +/* 07A6C8 80079AC8 24070002 */ li $a3, 2 /* 07A6CC 80079ACC 14400014 */ bnez $v0, .L80079B20 -/* 07A6D0 80079AD0 00000000 */ nop +/* 07A6D0 80079AD0 00000000 */ nop /* 07A6D4 80079AD4 14600012 */ bnez $v1, .L80079B20 -/* 07A6D8 80079AD8 02202825 */ move $a1, $s1 +/* 07A6D8 80079AD8 02202825 */ move $a1, $s1 /* 07A6DC 80079ADC 8E040008 */ lw $a0, 8($s0) /* 07A6E0 80079AE0 0C03238C */ jal osSendMesg -/* 07A6E4 80079AE4 00003025 */ move $a2, $zero +/* 07A6E4 80079AE4 00003025 */ move $a2, $zero /* 07A6E8 80079AE8 8E2D0264 */ lw $t5, 0x264($s1) /* 07A6EC 80079AEC 00000000 */ nop /* 07A6F0 80079AF0 11A0000B */ beqz $t5, .L80079B20 -/* 07A6F4 80079AF4 00000000 */ nop +/* 07A6F4 80079AF4 00000000 */ nop /* 07A6F8 80079AF8 0C01E5D8 */ jal func_80079760 -/* 07A6FC 80079AFC 02202025 */ move $a0, $s1 +/* 07A6FC 80079AFC 02202025 */ move $a0, $s1 /* 07A700 80079B00 10000008 */ b .L80079B24 -/* 07A704 80079B04 8E100004 */ lw $s0, 4($s0) +/* 07A704 80079B04 8E100004 */ lw $s0, 4($s0) .L80079B08: /* 07A708 80079B08 24010002 */ li $at, 2 /* 07A70C 80079B0C 14410004 */ bne $v0, $at, .L80079B20 -/* 07A710 80079B10 02202825 */ move $a1, $s1 +/* 07A710 80079B10 02202825 */ move $a1, $s1 /* 07A714 80079B14 8E040008 */ lw $a0, 8($s0) /* 07A718 80079B18 0C03238C */ jal osSendMesg -/* 07A71C 80079B1C 00003025 */ move $a2, $zero +/* 07A71C 80079B1C 00003025 */ move $a2, $zero .L80079B20: /* 07A720 80079B20 8E100004 */ lw $s0, 4($s0) .L80079B24: -/* 07A724 80079B24 00000000 */ nop +/* 07A724 80079B24 00000000 */ nop /* 07A728 80079B28 1600FFDE */ bnez $s0, .L80079AA4 -/* 07A72C 80079B2C 00000000 */ nop +/* 07A72C 80079B2C 00000000 */ nop /* 07A730 80079B30 8FBF001C */ lw $ra, 0x1c($sp) .L80079B34: /* 07A734 80079B34 8FB00014 */ lw $s0, 0x14($sp) /* 07A738 80079B38 8FB10018 */ lw $s1, 0x18($sp) /* 07A73C 80079B3C 03E00008 */ jr $ra -/* 07A740 80079B40 27BD0048 */ addiu $sp, $sp, 0x48 +/* 07A740 80079B40 27BD0048 */ addiu $sp, $sp, 0x48 diff --git a/lib/src/mips1/sc/sched.c b/lib/src/mips1/sc/sched.c index 3edd27c5..8e28951f 100644 --- a/lib/src/mips1/sc/sched.c +++ b/lib/src/mips1/sc/sched.c @@ -7,6 +7,14 @@ #include "f3ddkr.h" #include "libultra_internal.h" +/* + * private typedefs and defines + */ +#define VIDEO_MSG 666 +#define RSP_DONE_MSG 667 +#define RDP_DONE_MSG 668 +#define PRE_NMI_MSG 669 + /************ .data ************/ // Unsure about if this is an array or struct. @@ -64,7 +72,7 @@ void __scYield(OSSched *sc); void __scMain(void); void __scExec(OSSched *sc, OSScTask *sp, OSScTask *dp); -void osCreateScheduler(OSSched *sc, void *stack, OSPri priority, u8 mode, u8 numFields){ +void osCreateScheduler(OSSched *sc, void *stack, OSPri priority, u8 mode, u8 numFields) { sc->curRSPTask = 0; sc->curRDPTask = 0; sc->clientList = 0; @@ -88,11 +96,11 @@ void osCreateScheduler(OSSched *sc, void *stack, OSPri priority, u8 mode, u8 num osCreateMesgQueue(&sc->interruptQ, sc->intBuf, OS_SC_MAX_MESGS); osCreateMesgQueue(&sc->cmdQ, sc->cmdMsgBuf, OS_SC_MAX_MESGS); - osSetEventMesg(OS_EVENT_SP, &sc->interruptQ, (OSMesg)667); - osSetEventMesg(OS_EVENT_DP, &sc->interruptQ, (OSMesg)668); - osSetEventMesg(OS_EVENT_PRENMI, &sc->interruptQ, (OSMesg)669); + osSetEventMesg(OS_EVENT_SP, &sc->interruptQ, (OSMesg)RSP_DONE_MSG); + osSetEventMesg(OS_EVENT_DP, &sc->interruptQ, (OSMesg)RDP_DONE_MSG); + osSetEventMesg(OS_EVENT_PRENMI, &sc->interruptQ, (OSMesg)PRE_NMI_MSG); - osViSetEvent(&sc->interruptQ, (OSMesg)666, numFields); + osViSetEvent(&sc->interruptQ, (OSMesg)VIDEO_MSG, numFields); osCreateThread(&sc->thread, 5, __scMain, (void *)sc, stack, priority); @@ -122,10 +130,10 @@ void osScRemoveClient(OSSched *sc, OSScClient *c) while (client != 0) { if (client == c) { - if(prev) - prev->next = c->next; - else - sc->clientList = c->next; + if(prev) + prev->next = c->next; + else + sc->clientList = c->next; break; } prev = client; @@ -152,23 +160,20 @@ void func_80079584(f32 *arg0, f32 *arg1, f32 *arg2) { GLOBAL_ASM("lib/asm/non_matchings/sched/__scMain.s") -//__scHandleRetrace equivalent for unk284? -void func_80079760(OSSched *sc) { - s32 sp24; - s32 sp20; - s32 sp1C; +void func_80079760(OSSched_Rare *sc) { + s32 state; + OSScTask *sp = 0; + OSScTask *dp = 0; - sp20 = 0; - sp1C = 0; - if (sc->audioListHead != 0) { - sc->unk284 = 1; + if (sc->audioListHead) { + sc->doAudio = 1; } - if ((sc->unk284 != 0) && (sc->curRSPTask != 0)) { + if (sc->doAudio && sc->curRSPTask) { __scYield(sc); } else { - sp24 = ((sc->curRSPTask == 0) << 1) | (sc->curRDPTask == 0); - if (__scSchedule(sc, &sp20, &sp1C, sp24) != sp24) { - __scExec(sc, sp20, sp1C); + state = ((sc->curRSPTask == 0) << 1) | (sc->curRDPTask == 0); + if (__scSchedule(sc, &sp, &dp, state) != state) { + __scExec(sc, sp, dp); } } } @@ -179,114 +184,95 @@ void dummy_80079810() { } #if 0 -void __scHandleRetrace(OSSched *sc) { - void *sp44; - OSScTask *sp38; - OSScTask *sp34; - u8 sp32; - OSMesgQueue *sp28; - OSMesgQueue *temp_a0; - OSMesgQueue *temp_a0_2; - OSScClient *temp_s0_2; - OSScClient *temp_s0_3; - OSScTask *temp_v0; - OSScTask *temp_v0_2; - s32 temp_s0; - s32 temp_t2; - s32 temp_t7; - OSScTask *temp_v1; - u64 temp_ret; - u8 temp_v0_3; - s32 phi_s0; - OSScClient *phi_s0_2; +void __scHandleRetrace(OSSched_Rare *sc) { + OSScTask *rspTask = NULL; + OSScClient *client; + s32 i; + s32 availRPC; + OSScTask *sp = 0; + OSScTask *dp = 0; + u8 set_curRSPTask_NULL = FALSE; + u8 set_curRDPTask_NULL = FALSE; - sp44 = NULL; - sp38 = NULL; - sp34 = NULL; - sp32 = 0; - phi_s0 = 0; - if (sc->curRSPTask != 0) { - D_800DE754 = (s32) (D_800DE754 + 1); + if (sc->curRSPTask) { + D_800DE754++; } - if (sc->curRDPTask != 0) { - D_800DE758 = (s32) (D_800DE758 + 1); + + if (sc->curRDPTask) { + D_800DE758++; } - temp_v0 = sc->curRSPTask; - if ((D_800DE754 >= 0xB) && (temp_v0 != 0)) { + + if (((s32)D_800DE754 > (s32)10) && (sc->curRSPTask)) { D_800DE754 = 0; - __osSpSetStatus(0xAAAA82U); - phi_s0 = 1; - } else if (temp_v0 != 0) { + set_curRSPTask_NULL = TRUE; + + __osSpSetStatus(SP_SET_HALT | SP_CLR_INTR_BREAK | SP_CLR_SIG0 | + SP_CLR_SIG1 | SP_CLR_SIG2 | SP_CLR_SIG3 | SP_CLR_SIG4 | + SP_CLR_SIG5 | SP_CLR_SIG6 | SP_CLR_SIG7); + } else if (sc->curRSPTask) { D_80126110 = 1; } - temp_v0_2 = sc->curRDPTask; - if ((D_800DE758 >= 0xB) && (temp_v0_2 != 0)) { - if (temp_v0_2->unk68 == 0) { - osSendMesg(temp_v0_2->msgQ, &D_800DE738, 1); + + if (((s32)D_800DE758 > (s32)10) && (sc->curRDPTask)) { + if (sc->curRDPTask->unk68 == 0) { + osSendMesg(sc->curRDPTask->msgQ, &D_800DE738, OS_MESG_BLOCK); } - sp32 = 1; - sc->doAudio = 0; + + set_curRDPTask_NULL = TRUE; + sc->frameCount = 0; D_800DE758 = 0; - __osSpSetStatus(0xAAAA82U); - osDpSetStatus(0x1D6U); - } else if (temp_v0_2 != 0) { + + __osSpSetStatus(SP_SET_HALT | SP_CLR_INTR_BREAK | SP_CLR_SIG0 | + SP_CLR_SIG1 | SP_CLR_SIG2 | SP_CLR_SIG3 | SP_CLR_SIG4 | + SP_CLR_SIG5 | SP_CLR_SIG6 | SP_CLR_SIG7); + + osDpSetStatus(DPC_SET_XBUS_DMEM_DMA | DPC_CLR_FREEZE | DPC_CLR_FLUSH | + DPC_CLR_TMEM_CTR | DPC_CLR_PIPE_CTR | DPC_CLR_CMD_CTR); + } else if (sc->curRDPTask) { D_80126114 = 1; } - temp_a0 = &sc->cmdQ; - if (phi_s0 != 0) { + + if (set_curRSPTask_NULL) { sc->curRSPTask = NULL; } - if (sp32 != 0) { + if (set_curRDPTask_NULL) { sc->curRDPTask = NULL; } - sp28 = temp_a0; - if (osRecvMesg(temp_a0, &sp44, 0) != -1) { - do { - __scAppendList(sc, (OSScTask *) sp44); - } while (osRecvMesg(sp28, &sp44, 0) != -1); - } - temp_s0 = ((sc->curRSPTask == 0) * 2) | (sc->curRDPTask == 0); - if (__scSchedule(sc, &sp38, &sp34, temp_s0) != temp_s0) { - __scExec(sc, sp38, sp34); - } - temp_t7 = D_800DE760 + 1; - D_800DE760 = (s32) (D_800DE760 + (temp_t7 == 0)); - D_800DE760 = temp_t7; - D_800DE750 = (s32) (D_800DE750 + 1); - temp_v1 = sc->curRDPTask; - temp_t2 = sc->doAudio + 1; - sc->doAudio = temp_t2; - if ((temp_v1 != 0) && ((u32) temp_t2 >= 2U)) { - temp_a0_2 = temp_v1->msgQ; - if (temp_a0_2 != 0) { - if ((temp_v1->unk68 != 0) || (temp_v1->msgQ != 0)) { - osSendMesg(temp_a0_2, temp_v1->msgQ, 1); + + while (osRecvMesg(&sc->cmdQ, (OSMesg *)&rspTask, OS_MESG_NOBLOCK) != -1) + __scAppendList(sc, rspTask); + + availRPC = ((sc->curRSPTask == NULL) << 1) | (sc->curRDPTask == NULL); + if (__scSchedule(sc, &sp, &dp, availRPC) != availRPC) + __scExec(sc, sp, dp); + + D_800DE760++; + D_800DE750++; + sc->frameCount++; + + if ((sc->unkTask) && (sc->frameCount >= 2)) { + if (sc->unkTask->msgQ) { + if ((sc->unkTask->unk68) || (sc->unkTask->msg)) { + osSendMesg(sc->unkTask->msgQ, sc->unkTask->msg, OS_MESG_BLOCK); } else { - osSendMesg(temp_a0_2, &D_800DE730, 1); + osSendMesg(sc->unkTask->msgQ, &D_800DE730, OS_MESG_BLOCK); } } - sc->doAudio = 0; sc->frameCount = 0; + sc->unkTask = 0; } - temp_s0_2 = sc->clientList; - phi_s0_2 = temp_s0_2; - if (temp_s0_2 != 0) { - do { - temp_v0_3 = phi_s0_2->unk0; - if (temp_v0_3 == 1) { - temp_ret = D_800DE760 % 2;//__ull_rem(D_800DE760, D_800DE764, 0, 2); - if ((temp_ret == 0)) { - osSendMesg(phi_s0_2->msgQ, (void *) sc, 0); - if (sc->audioListHead != 0) { - func_80079760(sc); - } + + for (client = sc->clientList; client != 0; client = client->next) { + if (client->unk0 == 1) { + if (D_800DE760 % 2 == 0) { + osSendMesg(client->msgQ, sc, OS_MESG_NOBLOCK); + if (sc->audioListHead) { + func_80079760(sc); } - } else if (temp_v0_3 == 2) { - osSendMesg(phi_s0_2->msgQ, (void *) sc, 0); } - temp_s0_3 = phi_s0_2->next; - phi_s0_2 = temp_s0_3; - } while (temp_s0_3 != 0); + } else if (client->unk0 == 2) { + osSendMesg(client->msgQ, sc, OS_MESG_NOBLOCK); + } } } #else diff --git a/lib/src/mips1/sc/sched.h b/lib/src/mips1/sc/sched.h index 8eb4ff7e..b7b4d43c 100644 --- a/lib/src/mips1/sc/sched.h +++ b/lib/src/mips1/sc/sched.h @@ -57,10 +57,13 @@ typedef struct OSScTask_s { OSTime startTime; /* remain at the end!!, or */ OSTime totalTime; /* possible conflict if */ #endif /* FINALROM library used with */ -} OSScTask; /* non FINALROM code */ + /* non FINALROM code */ + + s32 unk68; /* Added by Rare? */ +} OSScTask; typedef struct SCClient_s { - u8 unk0; + u8 unk0; /* Added by Rare? */ struct SCClient_s *next; /* next client in the list */ OSMesgQueue *msgQ; /* where to send the frame msg */ } OSScClient; @@ -83,9 +86,29 @@ typedef struct { /* 0x660 */ OSScTask *curRDPTask; /* 0x710 */ u32 frameCount; /* 0x714 */ s32 doAudio; - /* 0x718 */ s32 unk284; } OSSched; +/* 0x7C8 bytes */ +typedef struct { + /* 0x00 */ OSScMsg retraceMsg; + /* 0x20 */ OSScMsg prenmiMsg; + /* 0x40 */ OSMesgQueue interruptQ; + /* 0x68 */ OSMesg intBuf[OS_SC_MAX_MESGS]; //0x8 per OsMesg + /* 0xA8 */ OSMesgQueue cmdQ; + /* 0xD0 */ OSMesg cmdMsgBuf[OS_SC_MAX_MESGS]; //0x8 per OsMesg + /* 0x110 */ OSThread thread; + /* 0x2D8 */ OSScClient *clientList; + /* 0x2F0 */ OSScTask *audioListHead; + /* 0x3A0 */ OSScTask *gfxListHead; + /* 0x450 */ OSScTask *audioListTail; + /* 0x500 */ OSScTask *gfxListTail; + /* 0x5B0 */ OSScTask *curRSPTask; + /* 0x660 */ OSScTask *curRDPTask; + /* 0x710 */ OSScTask *unkTask; //Rare added? + /* 0x7C0 */ u32 frameCount; + /* 0x7C4 */ s32 doAudio; +} OSSched_Rare; + typedef struct{ u8 pad00[0x50]; } unk800E3900; @@ -103,7 +126,7 @@ void osScRemoveClient(OSSched *sc, OSScClient *c); OSMesgQueue *osScGetCmdQ(OSSched *sc); OSMesgQueue *osScGetInterruptQ(OSSched *sc); void func_80079584(f32 *arg0, f32 *arg1, f32 *arg2); -void func_80079760(OSSched *sc); +void func_80079760(OSSched_Rare *sc); void __scHandleRDP(OSSched *sc); OSScTask *__scTaskReady(OSScTask *t); s32 __scTaskComplete(OSSched *sc, OSScTask *t);