mirror of
https://github.com/izzy2lost/Diddy-Kong-Racing.git
synced 2026-06-19 01:16:26 -07:00
Merge pull request #174 from Ryan-Myers/master
Uncountable number of changes bringing over 40 new matches, almost entirely focused on libultra.
This commit is contained in:
David Benepe
@@ -13,6 +13,10 @@ ucode/
|
||||
# Linker file is automatically generated, so it should be ignored
|
||||
dkr.ld
|
||||
|
||||
# CTX files for mips2c should be ignored as we generate those
|
||||
ctx.c
|
||||
ctx_includes.c
|
||||
|
||||
# Misc stuff that should be ignored.
|
||||
.*/
|
||||
|
||||
|
||||
@@ -141,7 +141,7 @@ TEXBUILDER = $(TOOLS_DIR)/dkr_texbuilder
|
||||
COMPRESS = $(TOOLS_DIR)/dkr_decompressor -c
|
||||
|
||||
LIB_DIRS := lib/
|
||||
ASM_DIRS := asm/ asm/boot/ asm/assets/ lib/asm/
|
||||
ASM_DIRS := asm/ asm/boot/ asm/assets/ lib/asm/ lib/asm/non_decompilable
|
||||
SRC_DIRS := $(sort $(dir $(wildcard src/* src/**/*))) $(sort $(dir $(wildcard lib/src/* lib/src/**/* lib/src/**/**/*)))
|
||||
|
||||
GLOBAL_ASM_C_FILES != grep -rl 'GLOBAL_ASM(' $(SRC_DIRS)
|
||||
@@ -267,6 +267,7 @@ $(BUILD_DIR)/lib/src/al/%.o: OPT_FLAGS := -O3
|
||||
$(BUILD_DIR)/lib/src/os/%.o: OPT_FLAGS := -O1
|
||||
$(BUILD_DIR)/lib/src/os/osViMgr.o: OPT_FLAGS := -O2
|
||||
$(BUILD_DIR)/lib/src/os/osCreatePiManager.o: OPT_FLAGS := -O2
|
||||
$(BUILD_DIR)/lib/src/os/osMotor.o: OPT_FLAGS := -O2
|
||||
$(BUILD_DIR)/lib/src/libc/xprintf.o : OPT_FLAGS := -O3
|
||||
$(BUILD_DIR)/lib/src/al/unknown_0C9C90.o: OPT_FLAGS := -O2 -Wo,-loopunroll,0
|
||||
#$(BUILD_DIR)/lib/src/libc/llcvt.o: OPT_FLAGS :=
|
||||
@@ -274,6 +275,7 @@ $(BUILD_DIR)/lib/src/al/unknown_0C9C90.o: OPT_FLAGS := -O2 -Wo,-loopunroll,0
|
||||
|
||||
$(BUILD_DIR)/lib/%.o: MIPSISET := -mips2
|
||||
$(BUILD_DIR)/lib/src/mips1/%.o: MIPSISET := -mips1
|
||||
$(BUILD_DIR)/lib/src/os/osMotor.o: MIPSISET := -mips1
|
||||
|
||||
# asm-processor currently does not support -O3, so this is my workaround.
|
||||
$(BUILD_DIR)/lib/src/al/global_asm/%.o: OPT_FLAGS := -O2
|
||||
|
||||
@@ -113,30 +113,30 @@ s32 is_drumstick_unlocked(void) {
|
||||
}
|
||||
```
|
||||
|
||||
As of September 27th 2021, this is our current score:
|
||||
As of October 15th 2021, this is our current score:
|
||||
```
|
||||
==================================================================
|
||||
ADVENTURE ONE (ASM -> C Decompilation)
|
||||
------------------------ 16.16% Complete -------------------------
|
||||
# Decompiled functions: 934
|
||||
# GLOBAL_ASM remaining: 848
|
||||
# NON_MATCHING functions: 104
|
||||
-------------------------- Game Status ---------------------------
|
||||
Balloons: 8/47, Keys: 1/4, Trophies: 0/5
|
||||
T.T. Amulets: 1/4, Wizpig Amulets: 0/4
|
||||
------------------------------------------------------------------
|
||||
We are collecting silver coins in Ancient Lake. (5/8 silver coins)
|
||||
==================================================================
|
||||
ADVENTURE TWO (Cleanup & Documentation)
|
||||
------------------------ 0.80% Complete -------------------------
|
||||
# Documented functions: 65
|
||||
# Undocumented remaining: 1717
|
||||
-------------------------- Game Status ---------------------------
|
||||
Balloons: 0/47, Keys: 0/4, Trophies: 0/5
|
||||
T.T. Amulets: 0/4, Wizpig Amulets: 0/4
|
||||
------------------------------------------------------------------
|
||||
We are collecting the first balloon on Timber's Island.
|
||||
==================================================================
|
||||
===================================================================
|
||||
ADVENTURE ONE (ASM -> C Decompilation)
|
||||
------------------------- 17.77% Complete -------------------------
|
||||
# Decompiled functions: 972
|
||||
# GLOBAL_ASM remaining: 786
|
||||
# NON_MATCHING functions: 104
|
||||
--------------------------- Game Status ---------------------------
|
||||
Balloons: 9/47, Keys: 1/4, Trophies: 0/5
|
||||
T.T. Amulets: 1/4, Wizpig Amulets: 0/4
|
||||
-------------------------------------------------------------------
|
||||
We are collecting silver coins in Fossil Canyon. (6/8 silver coins)
|
||||
===================================================================
|
||||
ADVENTURE TWO (Cleanup & Documentation)
|
||||
------------------------- 0.80% Complete -------------------------
|
||||
# Documented functions: 65
|
||||
# Undocumented remaining: 1693
|
||||
--------------------------- Game Status ---------------------------
|
||||
Balloons: 0/47, Keys: 0/4, Trophies: 0/5
|
||||
T.T. Amulets: 0/4, Wizpig Amulets: 0/4
|
||||
-------------------------------------------------------------------
|
||||
We are collecting the first balloon on Timber's Island.
|
||||
===================================================================
|
||||
|
||||
```
|
||||
|
||||
|
||||
@@ -52,7 +52,7 @@ glabel func_80074B34
|
||||
/* 0757F4 80074BF4 15C00004 */ bnez $t6, .L80074C08
|
||||
/* 0757F8 80074BF8 3C048012 */ lui $a0, %hi(D_80124010) # $a0, 0x8012
|
||||
/* 0757FC 80074BFC 8C844010 */ lw $a0, %lo(D_80124010)($a0)
|
||||
/* 075800 80074C00 0C033B48 */ jal func_800CED20
|
||||
/* 075800 80074C00 0C033B48 */ jal osPfsInit
|
||||
/* 075804 80074C04 03203025 */ move $a2, $t9
|
||||
.L80074C08:
|
||||
/* 075808 80074C08 8FA40058 */ lw $a0, 0x58($sp)
|
||||
|
||||
@@ -68,7 +68,7 @@ glabel func_800758DC
|
||||
/* 0765D0 800759D0 00401825 */ move $v1, $v0
|
||||
/* 0765D4 800759D4 8E840000 */ lw $a0, ($s4)
|
||||
/* 0765D8 800759D8 02602825 */ move $a1, $s3
|
||||
/* 0765DC 800759DC 0C033B48 */ jal func_800CED20
|
||||
/* 0765DC 800759DC 0C033B48 */ jal osPfsInit
|
||||
/* 0765E0 800759E0 02A03025 */ move $a2, $s5
|
||||
/* 0765E4 800759E4 00401825 */ move $v1, $v0
|
||||
.L800759E8:
|
||||
@@ -90,7 +90,7 @@ glabel func_800758DC
|
||||
/* 07661C 80075A1C 24010001 */ li $at, 1
|
||||
/* 076620 80075A20 8E840000 */ lw $a0, ($s4)
|
||||
/* 076624 80075A24 02602825 */ move $a1, $s3
|
||||
/* 076628 80075A28 0C033B48 */ jal func_800CED20
|
||||
/* 076628 80075A28 0C033B48 */ jal osPfsInit
|
||||
/* 07662C 80075A2C 02A03025 */ move $a2, $s5
|
||||
/* 076630 80075A30 14520008 */ bne $v0, $s2, .L80075A54
|
||||
/* 076634 80075A34 02602825 */ move $a1, $s3
|
||||
|
||||
@@ -67,13 +67,13 @@ glabel func_80075B18
|
||||
/* 076818 80075C18 018D9021 */ addu $s2, $t4, $t5
|
||||
/* 07681C 80075C1C 8E840000 */ lw $a0, ($s4)
|
||||
/* 076820 80075C20 02402825 */ move $a1, $s2
|
||||
/* 076824 80075C24 0C033B48 */ jal func_800CED20
|
||||
/* 076824 80075C24 0C033B48 */ jal osPfsInit
|
||||
/* 076828 80075C28 02003025 */ move $a2, $s0
|
||||
/* 07682C 80075C2C 24010002 */ li $at, 2
|
||||
/* 076830 80075C30 14410004 */ bne $v0, $at, .L80075C44
|
||||
/* 076834 80075C34 02402825 */ move $a1, $s2
|
||||
/* 076838 80075C38 8E840000 */ lw $a0, ($s4)
|
||||
/* 07683C 80075C3C 0C033B48 */ jal func_800CED20
|
||||
/* 07683C 80075C3C 0C033B48 */ jal osPfsInit
|
||||
/* 076840 80075C40 02003025 */ move $a2, $s0
|
||||
.L80075C44:
|
||||
/* 076844 80075C44 14400006 */ bnez $v0, .L80075C60
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
#ifndef _ULTRA64_OS_INTERNAL_H_
|
||||
#define _ULTRA64_OS_INTERNAL_H_
|
||||
|
||||
/* Internal functions used by the operating system */
|
||||
/* Do not include this header in application code */
|
||||
|
||||
#include "os_thread.h"
|
||||
|
||||
/*
|
||||
* Leo Disk
|
||||
*/
|
||||
|
||||
/* transfer mode */
|
||||
|
||||
#define LEO_BLOCK_MODE 1
|
||||
#define LEO_TRACK_MODE 2
|
||||
#define LEO_SECTOR_MODE 3
|
||||
|
||||
/* Variables */
|
||||
/*
|
||||
* CPU counter increments at 3/4 of bus clock rate:
|
||||
*
|
||||
* Bus Clock Proc Clock Counter (1/2 Proc Clock)
|
||||
* --------- ---------- ------------------------
|
||||
* 62.5 Mhz 93.75 Mhz 46.875 Mhz
|
||||
*/
|
||||
extern u64 osClockRate;
|
||||
|
||||
#define OS_CLOCK_RATE 62500000LL
|
||||
#define OS_CPU_COUNTER (OS_CLOCK_RATE*3/4)
|
||||
#define OS_NSEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625000LL))/(1000000000LL/15625000LL))
|
||||
#define OS_USEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625LL))/(1000000LL/15625LL))
|
||||
#define OS_CYCLES_TO_NSEC(c) (((u64)(c)*(1000000000LL/15625000LL))/(OS_CPU_COUNTER/15625000LL))
|
||||
#define OS_CYCLES_TO_USEC(c) (((u64)(c)*(1000000LL/15625LL))/(OS_CPU_COUNTER/15625LL))
|
||||
|
||||
/* Functions */
|
||||
|
||||
u32 __osProbeTLB(void *);
|
||||
u32 __osDisableInt(void);
|
||||
void __osRestoreInt(u32);
|
||||
OSThread *__osGetCurrFaultedThread(void);
|
||||
u32 osVirtualToPhysical(void *addr);
|
||||
|
||||
#endif
|
||||
@@ -187,7 +187,7 @@ typedef struct {
|
||||
|
||||
/* Controller interface */
|
||||
|
||||
extern s32 osContInit(OSMesgQueue *mq, u8 *bitpattern, OSContStatus *status);
|
||||
extern s32 osContInit(OSMesgQueue *mq, u8 *bitpattern, OSContStatus *data);
|
||||
extern s32 osContReset(OSMesgQueue *, OSContStatus *);
|
||||
extern s32 osContStartQuery(OSMesgQueue *);
|
||||
extern s32 osContStartReadData(OSMesgQueue *mq);
|
||||
|
||||
+114
-30
@@ -1,35 +1,119 @@
|
||||
#ifndef _ULTRA64_OS_INTERNAL_H_
|
||||
#define _ULTRA64_OS_INTERNAL_H_
|
||||
/**************************************************************************
|
||||
* *
|
||||
* Copyright (C) 1995, Silicon Graphics, Inc. *
|
||||
* *
|
||||
* These coded instructions, statements, and computer programs contain *
|
||||
* unpublished proprietary information of Silicon Graphics, Inc., and *
|
||||
* are protected by Federal copyright law. They may not be disclosed *
|
||||
* to third parties or copied or duplicated in any form, in whole or *
|
||||
* in part, without the prior written consent of Silicon Graphics, Inc. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
|
||||
/* Internal functions used by the operating system */
|
||||
/* Do not include this header in application code */
|
||||
|
||||
#include "os_thread.h"
|
||||
|
||||
/* Variables */
|
||||
|
||||
extern u64 osClockRate;
|
||||
/*
|
||||
* CPU counter increments at 3/4 of bus clock rate:
|
||||
/**************************************************************************
|
||||
*
|
||||
* Bus Clock Proc Clock Counter (1/2 Proc Clock)
|
||||
* --------- ---------- ------------------------
|
||||
* 62.5 Mhz 93.75 Mhz 46.875 Mhz
|
||||
*/
|
||||
extern u64 osClockRate;
|
||||
* $Revision: 1.18 $
|
||||
* $Date: 1997/02/11 08:26:14 $
|
||||
* $Source: /disk6/Master/cvsmdev2/PR/include/os_internal.h,v $
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#define OS_CLOCK_RATE 62500000LL
|
||||
#define OS_CPU_COUNTER (OS_CLOCK_RATE*3/4)
|
||||
#define OS_NSEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625000LL))/(1000000000LL/15625000LL))
|
||||
#define OS_USEC_TO_CYCLES(n) (((u64)(n)*(OS_CPU_COUNTER/15625LL))/(1000000LL/15625LL))
|
||||
#define OS_CYCLES_TO_NSEC(c) (((u64)(c)*(1000000000LL/15625000LL))/(OS_CPU_COUNTER/15625000LL))
|
||||
#define OS_CYCLES_TO_USEC(c) (((u64)(c)*(1000000LL/15625LL))/(OS_CPU_COUNTER/15625LL))
|
||||
|
||||
/* Functions */
|
||||
|
||||
u32 __osProbeTLB(void *);
|
||||
u32 __osDisableInt(void);
|
||||
void __osRestoreInt(u32);
|
||||
OSThread *__osGetCurrFaultedThread(void);
|
||||
#ifndef _OS_INTERNAL_H_
|
||||
#define _OS_INTERNAL_H_
|
||||
|
||||
#ifdef _LANGUAGE_C_PLUS_PLUS
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <PR/os.h>
|
||||
#include <PR/os_exception.h>
|
||||
|
||||
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
|
||||
|
||||
/* Routines to get/fetch coprocessor 0 registers */
|
||||
|
||||
extern u32 __osGetCause(void);
|
||||
extern void __osSetCause(u32);
|
||||
extern u32 __osGetCompare(void);
|
||||
extern void __osSetCompare(u32);
|
||||
extern u32 __osGetConfig(void);
|
||||
extern void __osSetConfig(u32);
|
||||
extern void __osSetCount(u32);
|
||||
extern u32 __osGetSR(void);
|
||||
extern void __osSetSR(u32);
|
||||
extern u32 __osDisableInt(void);
|
||||
extern void __osRestoreInt(u32);
|
||||
|
||||
/* Routines to get/set floating-point control and status register */
|
||||
extern u32 __osSetFpcCsr(u32);
|
||||
extern u32 __osGetFpcCsr(void);
|
||||
|
||||
/* Routine for HW interrupt "handler" */
|
||||
extern void __osSetHWIntrRoutine(OSHWIntr, s32 (*handler)(void));
|
||||
|
||||
/* Routine for global interrupt mask */
|
||||
extern void __osSetGlobalIntMask(OSHWIntr);
|
||||
extern void __osResetGlobalIntMask(OSHWIntr);
|
||||
|
||||
/* Routine for global interrupt mask */
|
||||
extern s32 __osLeoInterrupt(void);
|
||||
|
||||
/* Routines for fetch TLB info */
|
||||
|
||||
extern u32 __osGetTLBASID(void);
|
||||
extern u32 __osGetTLBPageMask(s32);
|
||||
extern u32 __osGetTLBHi(s32);
|
||||
extern u32 __osGetTLBLo0(s32);
|
||||
extern u32 __osGetTLBLo1(s32);
|
||||
|
||||
/* Serial interface (Si) */
|
||||
|
||||
extern u32 __osSiGetStatus(void);
|
||||
extern s32 __osSiRawWriteIo(u32, u32);
|
||||
extern s32 __osSiRawReadIo(u32, u32 *);
|
||||
extern s32 __osSiRawStartDma(s32, void *);
|
||||
|
||||
/* Signal processor interface (Sp) */
|
||||
|
||||
extern u32 __osSpGetStatus(void);
|
||||
extern void __osSpSetStatus(u32);
|
||||
extern s32 __osSpSetPc(u32);
|
||||
extern s32 __osSpRawWriteIo(u32, u32);
|
||||
extern s32 __osSpRawReadIo(u32, u32 *);
|
||||
extern s32 __osSpRawStartDma(s32, u32, void *, u32);
|
||||
|
||||
/* Error handling */
|
||||
|
||||
extern void __osError(s16, s16, ...);
|
||||
extern OSThread * __osGetCurrFaultedThread(void);
|
||||
extern OSThread * __osGetNextFaultedThread(OSThread *);
|
||||
|
||||
/* Development board functions */
|
||||
|
||||
extern void __osGIOInit(s32);
|
||||
extern void __osGIOInterrupt(s32);
|
||||
extern void __osGIORawInterrupt(s32);
|
||||
|
||||
/* For debugger use */
|
||||
|
||||
extern OSThread * __osGetActiveQueue(void);
|
||||
|
||||
/* Debug port */
|
||||
extern void __osSyncPutChars(int, int, const char *);
|
||||
extern int __osSyncGetChars(char *);
|
||||
extern void __osAsyncPutChars(int, int, const char *);
|
||||
extern int __osAsyncGetChars(char *);
|
||||
extern int __osAtomicInc(unsigned int *p);
|
||||
extern int __osAtomicDec(unsigned int *p);
|
||||
|
||||
/* routine for rdb port */
|
||||
extern u32 __osRdbSend(u8 *buf, u32 size, u32 type);
|
||||
|
||||
|
||||
#endif /* _LANGUAGE_C */
|
||||
|
||||
#ifdef _LANGUAGE_C_PLUS_PLUS
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !_OS_INTERNAL_H */
|
||||
|
||||
+72
-72
@@ -52,17 +52,17 @@
|
||||
0x0800_0000 .. 0x0fff_ffff cartridge domain 2
|
||||
0x1000_0000 .. 0x1fbf_ffff cartridge domain 1
|
||||
|
||||
0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
|
||||
0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
|
||||
0x1fc0_0800 .. 0x1fcf_ffff Reserved
|
||||
0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
|
||||
0x8000_0000 .. 0xffff_ffff external SysAD device
|
||||
0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes)
|
||||
0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes)
|
||||
0x1fc0_0800 .. 0x1fcf_ffff Reserved
|
||||
0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1
|
||||
0x8000_0000 .. 0xffff_ffff external SysAD device
|
||||
|
||||
The Indy development board use cartridge domain 1:
|
||||
0x1000_0000 .. 0x10ff_ffff RAMROM
|
||||
0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
|
||||
0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
|
||||
0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
|
||||
0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes)
|
||||
0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes)
|
||||
0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes)
|
||||
|
||||
|
||||
|
||||
@@ -109,9 +109,9 @@ The Indy development board use cartridge domain 1:
|
||||
#define RDRAM_0_DEVICE_ID 0
|
||||
#define RDRAM_1_DEVICE_ID 1
|
||||
|
||||
#define RDRAM_RESET_MODE 0
|
||||
#define RDRAM_ACTIVE_MODE 1
|
||||
#define RDRAM_STANDBY_MODE 2
|
||||
#define RDRAM_RESET_MODE 0
|
||||
#define RDRAM_ACTIVE_MODE 1
|
||||
#define RDRAM_STANDBY_MODE 2
|
||||
|
||||
#define RDRAM_LENGTH (2*512*2048)
|
||||
#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)
|
||||
@@ -125,7 +125,7 @@ The Indy development board use cartridge domain 1:
|
||||
/*************************************************************************
|
||||
* PIF Physical memory map (total size = 2 KB)
|
||||
*
|
||||
* Size Description Mode
|
||||
* Size Description Mode
|
||||
* 1FC007FF +-------+-----------------+-----+
|
||||
* | 64 B | JoyChannel RAM | R/W |
|
||||
* 1FC007C0 +-------+-----------------+-----+
|
||||
@@ -177,7 +177,7 @@ The Indy development board use cartridge domain 1:
|
||||
|
||||
/* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */
|
||||
#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */
|
||||
|
||||
|
||||
/* SP DRAM DMA address (R/W): [23:0] RDRAM address */
|
||||
#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */
|
||||
|
||||
@@ -212,31 +212,31 @@ The Indy development board use cartridge domain 1:
|
||||
/*
|
||||
* Values to clear/set bit in status reg (SP_STATUS_REG - write)
|
||||
*/
|
||||
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
|
||||
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
|
||||
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
|
||||
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
|
||||
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
|
||||
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
|
||||
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
|
||||
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
|
||||
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
|
||||
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
|
||||
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
|
||||
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
|
||||
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
|
||||
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
|
||||
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
|
||||
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
|
||||
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
|
||||
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
|
||||
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
|
||||
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
|
||||
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
|
||||
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
|
||||
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
|
||||
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
|
||||
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
|
||||
#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */
|
||||
#define SP_SET_HALT 0x00002 /* Bit 1: set halt */
|
||||
#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */
|
||||
#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */
|
||||
#define SP_SET_INTR 0x00010 /* Bit 4: set intr */
|
||||
#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */
|
||||
#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */
|
||||
#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */
|
||||
#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */
|
||||
#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */
|
||||
#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */
|
||||
#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */
|
||||
#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */
|
||||
#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */
|
||||
#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */
|
||||
#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */
|
||||
#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */
|
||||
#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */
|
||||
#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */
|
||||
#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */
|
||||
#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */
|
||||
#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */
|
||||
#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */
|
||||
#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */
|
||||
#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */
|
||||
|
||||
/*
|
||||
* Patterns to interpret status reg (SP_STATUS_REG - read)
|
||||
@@ -253,28 +253,28 @@ The Indy development board use cartridge domain 1:
|
||||
#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */
|
||||
#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */
|
||||
#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */
|
||||
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
|
||||
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
|
||||
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
|
||||
#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */
|
||||
#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */
|
||||
#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */
|
||||
|
||||
/*
|
||||
* Use of SIG bits
|
||||
*/
|
||||
#define SP_CLR_YIELD SP_CLR_SIG0
|
||||
#define SP_SET_YIELD SP_SET_SIG0
|
||||
#define SP_STATUS_YIELD SP_STATUS_SIG0
|
||||
#define SP_CLR_YIELDED SP_CLR_SIG1
|
||||
#define SP_SET_YIELDED SP_SET_SIG1
|
||||
#define SP_STATUS_YIELDED SP_STATUS_SIG1
|
||||
#define SP_CLR_TASKDONE SP_CLR_SIG2
|
||||
#define SP_SET_TASKDONE SP_SET_SIG2
|
||||
#define SP_STATUS_TASKDONE SP_STATUS_SIG2
|
||||
#define SP_CLR_RSPSIGNAL SP_CLR_SIG3
|
||||
#define SP_SET_RSPSIGNAL SP_SET_SIG3
|
||||
#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3
|
||||
#define SP_CLR_CPUSIGNAL SP_CLR_SIG4
|
||||
#define SP_SET_CPUSIGNAL SP_SET_SIG4
|
||||
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4
|
||||
#define SP_CLR_YIELD SP_CLR_SIG0 /* Bit 9 */
|
||||
#define SP_SET_YIELD SP_SET_SIG0 /* Bit 10 */
|
||||
#define SP_STATUS_YIELD SP_STATUS_SIG0 /* Bit 7 */
|
||||
#define SP_CLR_YIELDED SP_CLR_SIG1 /* Bit 11 */
|
||||
#define SP_SET_YIELDED SP_SET_SIG1 /* Bit 12 */
|
||||
#define SP_STATUS_YIELDED SP_STATUS_SIG1 /* Bit 8 */
|
||||
#define SP_CLR_TASKDONE SP_CLR_SIG2 /* Bit 13 */
|
||||
#define SP_SET_TASKDONE SP_SET_SIG2 /* Bit 14 */
|
||||
#define SP_STATUS_TASKDONE SP_STATUS_SIG2 /* Bit 9 */
|
||||
#define SP_CLR_RSPSIGNAL SP_CLR_SIG3 /* Bit 15 */
|
||||
#define SP_SET_RSPSIGNAL SP_SET_SIG3 /* Bit 16 */
|
||||
#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3 /* Bit 10 */
|
||||
#define SP_CLR_CPUSIGNAL SP_CLR_SIG4 /* Bit 17 */
|
||||
#define SP_SET_CPUSIGNAL SP_SET_SIG4 /* Bit 18 */
|
||||
#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 /* Bit 11 */
|
||||
|
||||
/* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */
|
||||
#define SP_IBIST_REG 0x04080004
|
||||
@@ -308,13 +308,13 @@ The Indy development board use cartridge domain 1:
|
||||
#define DPC_END_REG (DPC_BASE_REG+0x04)
|
||||
|
||||
/* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */
|
||||
#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
|
||||
#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)
|
||||
|
||||
/* DP CMD status (R/W): [9:0] valid bits - see below for definitions */
|
||||
#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)
|
||||
|
||||
/* DP clock counter (R): [23:0] clock counter */
|
||||
#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
|
||||
#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)
|
||||
|
||||
/* DP buffer busy counter (R): [23:0] clock counter */
|
||||
#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)
|
||||
@@ -482,9 +482,9 @@ The Indy development board use cartridge domain 1:
|
||||
/* VI status/control (R/W): [15-0] valid bits:
|
||||
* [1:0] = type[1:0] (pixel size)
|
||||
* 0: blank (no data, no sync)
|
||||
* 1: reserved
|
||||
* 2: 5/5/5/3 ("16" bit)
|
||||
* 3: 8/8/8/8 (32 bit)
|
||||
* 1: reserved
|
||||
* 2: 5/5/5/3 ("16" bit)
|
||||
* 3: 8/8/8/8 (32 bit)
|
||||
* [2] = gamma_dither_enable (normally on, unless "special effect")
|
||||
* [3] = gamma_enable (normally on, unless MPEG/JPEG)
|
||||
* [4] = divot_enable (normally on if antialiased, unless decal lines)
|
||||
@@ -508,11 +508,11 @@ The Indy development board use cartridge domain 1:
|
||||
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
|
||||
|
||||
/* VI width (R/W): [11:0] frame buffer line width in pixels */
|
||||
#define VI_WIDTH_REG (VI_BASE_REG+0x08)
|
||||
#define VI_WIDTH_REG (VI_BASE_REG+0x08)
|
||||
#define VI_H_WIDTH_REG VI_WIDTH_REG
|
||||
|
||||
/* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */
|
||||
#define VI_INTR_REG (VI_BASE_REG+0x0C)
|
||||
#define VI_INTR_REG (VI_BASE_REG+0x0C)
|
||||
#define VI_V_INTR_REG VI_INTR_REG
|
||||
|
||||
/*
|
||||
@@ -520,9 +520,9 @@ The Indy development board use cartridge domain 1:
|
||||
* line (the lsb of V_CURRENT is constant within a field, and in
|
||||
* interlaced modes gives the field number - which is constant for non-
|
||||
* interlaced modes)
|
||||
* - Any write to this register will clear interrupt line
|
||||
* - Any write to this register will clear interrupt line
|
||||
*/
|
||||
#define VI_CURRENT_REG (VI_BASE_REG+0x10)
|
||||
#define VI_CURRENT_REG (VI_BASE_REG+0x10)
|
||||
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
|
||||
|
||||
/*
|
||||
@@ -531,23 +531,23 @@ The Indy development board use cartridge domain 1:
|
||||
* [19:16] vertical sync width in half lines,
|
||||
* [29:20] start of color burst in pixels from h-sync
|
||||
*/
|
||||
#define VI_BURST_REG (VI_BASE_REG+0x14)
|
||||
#define VI_BURST_REG (VI_BASE_REG+0x14)
|
||||
#define VI_TIMING_REG VI_BURST_REG
|
||||
|
||||
/* VI vertical sync (R/W): [9:0] number of half-lines per field */
|
||||
#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
|
||||
#define VI_V_SYNC_REG (VI_BASE_REG+0x18)
|
||||
|
||||
/* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel
|
||||
* [20:16] a 5-bit leap pattern used for PAL only
|
||||
* (h_sync_period)
|
||||
*/
|
||||
#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
|
||||
#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)
|
||||
|
||||
/*
|
||||
* VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period
|
||||
* [27:16] identical to h_sync_period
|
||||
*/
|
||||
#define VI_LEAP_REG (VI_BASE_REG+0x20)
|
||||
#define VI_LEAP_REG (VI_BASE_REG+0x20)
|
||||
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
|
||||
|
||||
/*
|
||||
@@ -568,17 +568,17 @@ The Indy development board use cartridge domain 1:
|
||||
* VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines
|
||||
* : [25:16] start of color burst enable in half-lines
|
||||
*/
|
||||
#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
|
||||
#define VI_V_BURST_REG (VI_BASE_REG+0x2C)
|
||||
|
||||
/* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format)
|
||||
* [27:16] horizontal subpixel offset (2.10 format)
|
||||
*/
|
||||
#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
|
||||
#define VI_X_SCALE_REG (VI_BASE_REG+0x30)
|
||||
|
||||
/* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format)
|
||||
* [27:16] vertical subpixel offset (2.10 format)
|
||||
*/
|
||||
#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
|
||||
#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)
|
||||
|
||||
/*
|
||||
* Patterns to interpret VI_CONTROL_REG
|
||||
|
||||
@@ -32,5 +32,6 @@
|
||||
#include <PR/libultra.h>
|
||||
#include <PR/pfs.h>
|
||||
#include <PR/rcp.h>
|
||||
#include <PR/os.h>
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,3 +1,12 @@
|
||||
/* The comment below is needed for this file to be picked up by generate_ld */
|
||||
/* RAM_POS: 0x800D2560 */
|
||||
|
||||
.include "macros.inc"
|
||||
|
||||
.set noat # allow manual use of $at
|
||||
.set noreorder # dont insert nops after branches
|
||||
.set gp=64 # 64-bit instructions are used
|
||||
|
||||
glabel __osDisableInt
|
||||
/* 0D3160 800D2560 40086000 */ mfc0 $t0, $12
|
||||
/* 0D3164 800D2564 2401FFFE */ li $at, -2
|
||||
@@ -7,4 +16,3 @@ glabel __osDisableInt
|
||||
/* 0D3174 800D2574 00000000 */ nop
|
||||
/* 0D3178 800D2578 03E00008 */ jr $ra
|
||||
/* 0D317C 800D257C 00000000 */ nop
|
||||
|
||||
@@ -1,3 +1,12 @@
|
||||
/* The comment below is needed for this file to be picked up by generate_ld */
|
||||
/* RAM_POS: 0x800D2580 */
|
||||
|
||||
.include "macros.inc"
|
||||
|
||||
.set noat # allow manual use of $at
|
||||
.set noreorder # dont insert nops after branches
|
||||
.set gp=64 # 64-bit instructions are used
|
||||
|
||||
glabel __osRestoreInt
|
||||
/* 0D3180 800D2580 40086000 */ mfc0 $t0, $12
|
||||
/* 0D3184 800D2584 01044025 */ or $t0, $t0, $a0
|
||||
@@ -7,4 +16,4 @@ glabel __osRestoreInt
|
||||
/* 0D3194 800D2594 03E00008 */ jr $ra
|
||||
/* 0D3198 800D2598 00000000 */ nop
|
||||
|
||||
/* 0D319C 800D259C 00000000 */ nop
|
||||
/* 0D319C 800D259C 00000000 */ nop
|
||||
@@ -0,0 +1,15 @@
|
||||
/* The comment below is needed for this file to be picked up by generate_ld */
|
||||
/* RAM_POS: 0x800D7460 */
|
||||
|
||||
.include "macros.inc"
|
||||
|
||||
.set noat # allow manual use of $at
|
||||
.set noreorder # dont insert nops after branches
|
||||
.set gp=64 # 64-bit instructions are used
|
||||
|
||||
glabel __osSetCompare
|
||||
/* 0D8060 800D7460 40845800 */ mtc0 $a0, $11
|
||||
/* 0D8064 800D7464 03E00008 */ jr $ra
|
||||
/* 0D8068 800D7468 00000000 */ nop
|
||||
|
||||
/* 0D806C 800D746C 00000000 */ nop
|
||||
@@ -1,3 +1,12 @@
|
||||
/* The comment below is needed for this file to be picked up by generate_ld */
|
||||
/* RAM_POS: 0x800D04E0 */
|
||||
|
||||
.include "macros.inc"
|
||||
|
||||
.set noat # allow manual use of $at
|
||||
.set noreorder # dont insert nops after branches
|
||||
.set gp=64 # 64-bit instructions are used
|
||||
|
||||
glabel bzero
|
||||
/* 0D10E0 800D04E0 28A1000C */ slti $at, $a1, 0xc
|
||||
/* 0D10E4 800D04E4 1420001D */ bnez $at, .L800D055C
|
||||
@@ -87,8 +87,8 @@ glabel __osDispatchThread
|
||||
/* 0D4174 800D3574 275A94D0 */ addiu $k0, %lo(D_800E94D0) # addiu $k0, $k0, -0x6b30
|
||||
/* 0D4178 800D3578 037AD821 */ addu $k1, $k1, $k0
|
||||
/* 0D417C 800D357C 977B0000 */ lhu $k1, ($k1)
|
||||
/* 0D4180 800D3580 3C1AA430 */ lui $k0, %hi(D_A430000C) # $k0, 0xa430
|
||||
/* 0D4184 800D3584 275A000C */ addiu $k0, %lo(D_A430000C) # addiu $k0, $k0, 0xc
|
||||
/* 0D4180 800D3580 3C1AA430 */ lui $k0, %hi(MI_INTR_MASK_REG) # $k0, 0xa430
|
||||
/* 0D4184 800D3584 275A000C */ addiu $k0, %lo(MI_INTR_MASK_REG) # addiu $k0, $k0, 0xc
|
||||
/* 0D4188 800D3588 AF5B0000 */ sw $k1, ($k0)
|
||||
/* 0D418C 800D358C 00000000 */ nop
|
||||
/* 0D4190 800D3590 00000000 */ nop
|
||||
|
||||
@@ -45,8 +45,8 @@ glabel __osEnqueueAndYield
|
||||
/* 0D3F74 800D3374 0369D825 */ or $k1, $k1, $t1
|
||||
/* 0D3F78 800D3378 ACBB0118 */ sw $k1, 0x118($a1)
|
||||
.L800D337C:
|
||||
/* 0D3F7C 800D337C 3C1BA430 */ lui $k1, %hi(D_A430000C) # $k1, 0xa430
|
||||
/* 0D3F80 800D3380 8F7B000C */ lw $k1, %lo(D_A430000C)($k1)
|
||||
/* 0D3F7C 800D337C 3C1BA430 */ lui $k1, %hi(MI_INTR_MASK_REG) # $k1, 0xa430
|
||||
/* 0D3F80 800D3380 8F7B000C */ lw $k1, %lo(MI_INTR_MASK_REG)($k1)
|
||||
/* 0D3F84 800D3384 1360000B */ beqz $k1, .L800D33B4
|
||||
/* 0D3F88 800D3388 00000000 */ nop
|
||||
/* 0D3F8C 800D338C 3C1A800E */ lui $k0, %hi(__OSGlobalIntMask) # $k0, 0x800e
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
.section .rodata
|
||||
|
||||
glabel D_800E9670
|
||||
glabel __osIntOffTable
|
||||
.word 0x00141818
|
||||
.word 0x1C1C1C1C
|
||||
.word 0x20202020
|
||||
@@ -10,7 +10,7 @@ glabel D_800E9670
|
||||
.word 0x10101010
|
||||
.word 0x10101010
|
||||
|
||||
glabel D_800E9690
|
||||
glabel __osIntTable
|
||||
.word .L800D3168
|
||||
.word .L800D3130
|
||||
.word .L800D3110
|
||||
@@ -24,8 +24,8 @@ glabel D_800E9690
|
||||
.section .text
|
||||
|
||||
glabel __osException
|
||||
/* 0D38C0 800D2CC0 3C1A8013 */ lui $k0, %hi(D_8012D240) # $k0, 0x8013
|
||||
/* 0D38C4 800D2CC4 275AD240 */ addiu $k0, %lo(D_8012D240) # addiu $k0, $k0, -0x2dc0
|
||||
/* 0D38C0 800D2CC0 3C1A8013 */ lui $k0, %hi(gInterruptedThread) # $k0, 0x8013
|
||||
/* 0D38C4 800D2CC4 275AD240 */ addiu $k0, %lo(gInterruptedThread) # addiu $k0, $k0, -0x2dc0
|
||||
/* 0D38C8 800D2CC8 FF410020 */ sd $at, 0x20($k0)
|
||||
/* 0D38CC 800D2CCC 401B6000 */ mfc0 $k1, $12
|
||||
/* 0D38D0 800D2CD0 AF5B0118 */ sw $k1, 0x118($k0)
|
||||
@@ -95,8 +95,8 @@ glabel __osException
|
||||
/* 0D39D0 800D2DD0 0369D825 */ or $k1, $k1, $t1
|
||||
/* 0D39D4 800D2DD4 AF5B0118 */ sw $k1, 0x118($k0)
|
||||
.L800D2DD8:
|
||||
/* 0D39D8 800D2DD8 3C09A430 */ lui $t1, %hi(D_A430000C) # $t1, 0xa430
|
||||
/* 0D39DC 800D2DDC 8D29000C */ lw $t1, %lo(D_A430000C)($t1)
|
||||
/* 0D39D8 800D2DD8 3C09A430 */ lui $t1, %hi(MI_INTR_MASK_REG) # $t1, 0xa430
|
||||
/* 0D39DC 800D2DDC 8D29000C */ lw $t1, %lo(MI_INTR_MASK_REG)($t1)
|
||||
/* 0D39E0 800D2DE0 1120000B */ beqz $t1, .L800D2E10
|
||||
/* 0D39E4 800D2DE4 00000000 */ nop
|
||||
/* 0D39E8 800D2DE8 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) # $t0, 0x800e
|
||||
@@ -159,12 +159,12 @@ glabel __osException
|
||||
/* 0D3AC0 800D2EC0 00095202 */ srl $t2, $t1, 8
|
||||
/* 0D3AC4 800D2EC4 214A0010 */ addi $t2, $t2, 0x10
|
||||
.L800D2EC8:
|
||||
/* 0D3AC8 800D2EC8 3C01800F */ lui $at, %hi(D_800E9670) # $at, 0x800f
|
||||
/* 0D3AC8 800D2EC8 3C01800F */ lui $at, %hi(__osIntOffTable) # $at, 0x800f
|
||||
/* 0D3ACC 800D2ECC 002A0821 */ addu $at, $at, $t2
|
||||
/* 0D3AD0 800D2ED0 902A9670 */ lbu $t2, %lo(D_800E9670)($at)
|
||||
/* 0D3AD4 800D2ED4 3C01800F */ lui $at, %hi(D_800E9690) # $at, 0x800f
|
||||
/* 0D3AD0 800D2ED0 902A9670 */ lbu $t2, %lo(__osIntOffTable)($at)
|
||||
/* 0D3AD4 800D2ED4 3C01800F */ lui $at, %hi(__osIntTable) # $at, 0x800f
|
||||
/* 0D3AD8 800D2ED8 002A0821 */ addu $at, $at, $t2
|
||||
/* 0D3ADC 800D2EDC 8C2A9690 */ lw $t2, %lo(D_800E9690)($at)
|
||||
/* 0D3ADC 800D2EDC 8C2A9690 */ lw $t2, %lo(__osIntTable)($at)
|
||||
/* 0D3AE0 800D2EE0 01400008 */ jr $t2
|
||||
/* 0D3AE4 800D2EE4 00000000 */ nop
|
||||
.L800D2EE8:
|
||||
@@ -188,11 +188,11 @@ glabel __osException
|
||||
/* 0D3B20 800D2F20 2401F7FF */ li $at, -2049
|
||||
/* 0D3B24 800D2F24 02018024 */ and $s0, $s0, $at
|
||||
/* 0D3B28 800D2F28 240A0004 */ li $t2, 4
|
||||
/* 0D3B2C 800D2F2C 3C01800E */ lui $at, %hi(D_800E48A0) # $at, 0x800e
|
||||
/* 0D3B2C 800D2F2C 3C01800E */ lui $at, %hi(__osHwIntTable) # $at, 0x800e
|
||||
/* 0D3B30 800D2F30 002A0821 */ addu $at, $at, $t2
|
||||
/* 0D3B34 800D2F34 8C2A48A0 */ lw $t2, %lo(D_800E48A0)($at)
|
||||
/* 0D3B38 800D2F38 3C1D8013 */ lui $sp, %hi(D_8012AAE0) # $sp, 0x8013
|
||||
/* 0D3B3C 800D2F3C 27BDAAE0 */ addiu $sp, %lo(D_8012AAE0) # addiu $sp, $sp, -0x5520
|
||||
/* 0D3B34 800D2F34 8C2A48A0 */ lw $t2, %lo(__osHwIntTable)($at)
|
||||
/* 0D3B38 800D2F38 3C1D8013 */ lui $sp, %hi(leoDiskStack) # $sp, 0x8013
|
||||
/* 0D3B3C 800D2F3C 27BDAAE0 */ addiu $sp, %lo(leoDiskStack) # addiu $sp, $sp, -0x5520
|
||||
/* 0D3B40 800D2F40 24040010 */ li $a0, 16
|
||||
/* 0D3B44 800D2F44 11400007 */ beqz $t2, .L800D2F64
|
||||
/* 0D3B48 800D2F48 27BD0FF0 */ addiu $sp, $sp, 0xff0
|
||||
@@ -211,21 +211,21 @@ glabel __osException
|
||||
/* 0D3B74 800D2F74 3C08800E */ lui $t0, %hi(__OSGlobalIntMask) # $t0, 0x800e
|
||||
/* 0D3B78 800D2F78 250838AC */ addiu $t0, %lo(__OSGlobalIntMask) # addiu $t0, $t0, 0x38ac
|
||||
/* 0D3B7C 800D2F7C 8D080000 */ lw $t0, ($t0)
|
||||
/* 0D3B80 800D2F80 3C11A430 */ lui $s1, %hi(D_A4300008) # $s1, 0xa430
|
||||
/* 0D3B84 800D2F84 8E310008 */ lw $s1, %lo(D_A4300008)($s1)
|
||||
/* 0D3B80 800D2F80 3C11A430 */ lui $s1, %hi(MI_INTR_REG) # $s1, 0xa430
|
||||
/* 0D3B84 800D2F84 8E310008 */ lw $s1, %lo(MI_INTR_REG)($s1)
|
||||
/* 0D3B88 800D2F88 00084402 */ srl $t0, $t0, 0x10
|
||||
/* 0D3B8C 800D2F8C 02288824 */ and $s1, $s1, $t0
|
||||
/* 0D3B90 800D2F90 32290001 */ andi $t1, $s1, 1
|
||||
/* 0D3B94 800D2F94 11200013 */ beqz $t1, .L800D2FE4
|
||||
/* 0D3B98 800D2F98 00000000 */ nop
|
||||
/* 0D3B9C 800D2F9C 3C0CA404 */ lui $t4, %hi(D_A4040010) # $t4, 0xa404
|
||||
/* 0D3BA0 800D2FA0 8D8C0010 */ lw $t4, %lo(D_A4040010)($t4)
|
||||
/* 0D3B9C 800D2F9C 3C0CA404 */ lui $t4, %hi(SP_STATUS_REG) # $t4, 0xa404
|
||||
/* 0D3BA0 800D2FA0 8D8C0010 */ lw $t4, %lo(SP_STATUS_REG)($t4)
|
||||
/* 0D3BA4 800D2FA4 24090008 */ li $t1, 8
|
||||
/* 0D3BA8 800D2FA8 3C01A404 */ lui $at, %hi(D_A4040010) # $at, 0xa404
|
||||
/* 0D3BA8 800D2FA8 3C01A404 */ lui $at, %hi(SP_STATUS_REG) # $at, 0xa404
|
||||
/* 0D3BAC 800D2FAC 318C0300 */ andi $t4, $t4, 0x300
|
||||
/* 0D3BB0 800D2FB0 3231003E */ andi $s1, $s1, 0x3e
|
||||
/* 0D3BB4 800D2FB4 11800007 */ beqz $t4, .L800D2FD4
|
||||
/* 0D3BB8 800D2FB8 AC290010 */ sw $t1, %lo(D_A4040010)($at)
|
||||
/* 0D3BB8 800D2FB8 AC290010 */ sw $t1, %lo(SP_STATUS_REG)($at)
|
||||
/* 0D3BBC 800D2FBC 0C034C79 */ jal send_mesg
|
||||
/* 0D3BC0 800D2FC0 24040020 */ li $a0, 32
|
||||
/* 0D3BC4 800D2FC4 12200038 */ beqz $s1, .L800D30A8
|
||||
@@ -240,9 +240,9 @@ glabel __osException
|
||||
.L800D2FE4:
|
||||
/* 0D3BE4 800D2FE4 32290008 */ andi $t1, $s1, 8
|
||||
/* 0D3BE8 800D2FE8 11200007 */ beqz $t1, .L800D3008
|
||||
/* 0D3BEC 800D2FEC 3C01A440 */ lui $at, %hi(D_A4400010) # $at, 0xa440
|
||||
/* 0D3BEC 800D2FEC 3C01A440 */ lui $at, %hi(VI_CURRENT_REG) # $at, 0xa440
|
||||
/* 0D3BF0 800D2FF0 32310037 */ andi $s1, $s1, 0x37
|
||||
/* 0D3BF4 800D2FF4 AC200010 */ sw $zero, %lo(D_A4400010)($at)
|
||||
/* 0D3BF4 800D2FF4 AC200010 */ sw $zero, %lo(VI_CURRENT_REG)($at)
|
||||
/* 0D3BF8 800D2FF8 0C034C79 */ jal send_mesg
|
||||
/* 0D3BFC 800D2FFC 24040038 */ li $a0, 56
|
||||
/* 0D3C00 800D3000 12200029 */ beqz $s1, .L800D30A8
|
||||
@@ -252,9 +252,9 @@ glabel __osException
|
||||
/* 0D3C0C 800D300C 11200009 */ beqz $t1, .L800D3034
|
||||
/* 0D3C10 800D3010 00000000 */ nop
|
||||
/* 0D3C14 800D3014 24090001 */ li $t1, 1
|
||||
/* 0D3C18 800D3018 3C01A450 */ lui $at, %hi(D_A450000C) # $at, 0xa450
|
||||
/* 0D3C18 800D3018 3C01A450 */ lui $at, %hi(AI_STATUS_REG) # $at, 0xa450
|
||||
/* 0D3C1C 800D301C 3231003B */ andi $s1, $s1, 0x3b
|
||||
/* 0D3C20 800D3020 AC29000C */ sw $t1, %lo(D_A450000C)($at)
|
||||
/* 0D3C20 800D3020 AC29000C */ sw $t1, %lo(AI_STATUS_REG)($at)
|
||||
/* 0D3C24 800D3024 0C034C79 */ jal send_mesg
|
||||
/* 0D3C28 800D3028 24040030 */ li $a0, 48
|
||||
/* 0D3C2C 800D302C 1220001E */ beqz $s1, .L800D30A8
|
||||
@@ -262,9 +262,9 @@ glabel __osException
|
||||
.L800D3034:
|
||||
/* 0D3C34 800D3034 32290002 */ andi $t1, $s1, 2
|
||||
/* 0D3C38 800D3038 11200007 */ beqz $t1, .L800D3058
|
||||
/* 0D3C3C 800D303C 3C01A480 */ lui $at, %hi(D_A4800018) # $at, 0xa480
|
||||
/* 0D3C3C 800D303C 3C01A480 */ lui $at, %hi(SI_STATUS_REG) # $at, 0xa480
|
||||
/* 0D3C40 800D3040 3231003D */ andi $s1, $s1, 0x3d
|
||||
/* 0D3C44 800D3044 AC200018 */ sw $zero, %lo(D_A4800018)($at)
|
||||
/* 0D3C44 800D3044 AC200018 */ sw $zero, %lo(SI_STATUS_REG)($at)
|
||||
/* 0D3C48 800D3048 0C034C79 */ jal send_mesg
|
||||
/* 0D3C4C 800D304C 24040028 */ li $a0, 40
|
||||
/* 0D3C50 800D3050 12200015 */ beqz $s1, .L800D30A8
|
||||
@@ -274,9 +274,9 @@ glabel __osException
|
||||
/* 0D3C5C 800D305C 11200009 */ beqz $t1, .L800D3084
|
||||
/* 0D3C60 800D3060 00000000 */ nop
|
||||
/* 0D3C64 800D3064 24090002 */ li $t1, 2
|
||||
/* 0D3C68 800D3068 3C01A460 */ lui $at, %hi(D_A4600010) # $at, 0xa460
|
||||
/* 0D3C68 800D3068 3C01A460 */ lui $at, %hi(PI_STATUS_REG) # $at, 0xa460
|
||||
/* 0D3C6C 800D306C 3231002F */ andi $s1, $s1, 0x2f
|
||||
/* 0D3C70 800D3070 AC290010 */ sw $t1, %lo(D_A4600010)($at)
|
||||
/* 0D3C70 800D3070 AC290010 */ sw $t1, %lo(PI_STATUS_REG)($at)
|
||||
/* 0D3C74 800D3074 0C034C79 */ jal send_mesg
|
||||
/* 0D3C78 800D3078 24040040 */ li $a0, 64
|
||||
/* 0D3C7C 800D307C 1220000A */ beqz $s1, .L800D30A8
|
||||
@@ -369,8 +369,8 @@ glabel __osException
|
||||
/* 0D3DB0 800D31B0 AD3A0000 */ sw $k0, ($t1)
|
||||
|
||||
.L800D31B4:
|
||||
/* 0D3DB4 800D31B4 3C01800E */ lui $at, %hi(D_800E4894) # $at, 0x800e
|
||||
/* 0D3DB8 800D31B8 AC3A4894 */ sw $k0, %lo(D_800E4894)($at)
|
||||
/* 0D3DB4 800D31B4 3C01800E */ lui $at, %hi(__osFaultedThread) # $at, 0x800e
|
||||
/* 0D3DB8 800D31B8 AC3A4894 */ sw $k0, %lo(__osFaultedThread)($at)
|
||||
/* 0D3DBC 800D31BC 24090001 */ li $t1, 1
|
||||
/* 0D3DC0 800D31C0 A7490010 */ sh $t1, 0x10($k0)
|
||||
/* 0D3DC4 800D31C4 24090002 */ li $t1, 2
|
||||
|
||||
@@ -17,8 +17,8 @@ glabel __scHandleRSP
|
||||
/* 07A76C 80079B6C 00808025 */ move $s0, $a0
|
||||
/* 07A770 80079B70 0C031E34 */ jal osGetCount
|
||||
/* 07A774 80079B74 AFA50034 */ sw $a1, 0x34($sp)
|
||||
/* 07A778 80079B78 3C038012 */ lui $v1, %hi(D_80126124) # $v1, 0x8012
|
||||
/* 07A77C 80079B7C 24636124 */ addiu $v1, %lo(D_80126124) # addiu $v1, $v1, 0x6124
|
||||
/* 07A778 80079B78 3C038012 */ lui $v1, %hi(gRSPAudTaskCount) # $v1, 0x8012
|
||||
/* 07A77C 80079B7C 24636124 */ addiu $v1, %lo(gRSPAudTaskCount) # addiu $v1, $v1, 0x6124
|
||||
/* 07A780 80079B80 AC620000 */ sw $v0, ($v1)
|
||||
/* 07A784 80079B84 3C188012 */ lui $t8, %hi(D_80126120) # $t8, 0x8012
|
||||
/* 07A788 80079B88 8F186120 */ lw $t8, %lo(D_80126120)($t8)
|
||||
@@ -46,7 +46,7 @@ glabel __scHandleRSP
|
||||
/* 07A7DC 80079BDC C4EA0000 */ lwc1 $f10, ($a3)
|
||||
/* 07A7E0 80079BE0 C4C80000 */ lwc1 $f8, ($a2)
|
||||
/* 07A7E4 80079BE4 46128103 */ div.s $f4, $f16, $f18
|
||||
/* 07A7E8 80079BE8 3C02800E */ lui $v0, %hi(D_800DE750) # $v0, 0x800e
|
||||
/* 07A7E8 80079BE8 3C02800E */ lui $v0, %hi(gRetraceCounter32) # $v0, 0x800e
|
||||
/* 07A7EC 80079BEC E4840000 */ swc1 $f4, ($a0)
|
||||
/* 07A7F0 80079BF0 C4800000 */ lwc1 $f0, ($a0)
|
||||
/* 07A7F4 80079BF4 00000000 */ nop
|
||||
@@ -56,7 +56,7 @@ glabel __scHandleRSP
|
||||
/* 07A804 80079C04 E4C60000 */ swc1 $f6, ($a2)
|
||||
/* 07A808 80079C08 E4E00000 */ swc1 $f0, ($a3)
|
||||
.L80079C0C:
|
||||
/* 07A80C 80079C0C 8C42E750 */ lw $v0, %lo(D_800DE750)($v0)
|
||||
/* 07A80C 80079C0C 8C42E750 */ lw $v0, %lo(gRetraceCounter32)($v0)
|
||||
/* 07A810 80079C10 240103E8 */ li $at, 1000
|
||||
/* 07A814 80079C14 0041001A */ div $zero, $v0, $at
|
||||
/* 07A818 80079C18 24010001 */ li $at, 1
|
||||
|
||||
@@ -1,119 +0,0 @@
|
||||
glabel __scMain
|
||||
/* 07A1AC 800795AC 27BDFF98 */ addiu $sp, $sp, -0x68
|
||||
/* 07A1B0 800795B0 AFBE0038 */ sw $fp, 0x38($sp)
|
||||
/* 07A1B4 800795B4 AFB70034 */ sw $s7, 0x34($sp)
|
||||
/* 07A1B8 800795B8 AFB60030 */ sw $s6, 0x30($sp)
|
||||
/* 07A1BC 800795BC AFB5002C */ sw $s5, 0x2c($sp)
|
||||
/* 07A1C0 800795C0 AFB40028 */ sw $s4, 0x28($sp)
|
||||
/* 07A1C4 800795C4 AFB30024 */ sw $s3, 0x24($sp)
|
||||
/* 07A1C8 800795C8 AFB20020 */ sw $s2, 0x20($sp)
|
||||
/* 07A1CC 800795CC 00809025 */ move $s2, $a0
|
||||
/* 07A1D0 800795D0 AFBF003C */ sw $ra, 0x3c($sp)
|
||||
/* 07A1D4 800795D4 AFB1001C */ sw $s1, 0x1c($sp)
|
||||
/* 07A1D8 800795D8 AFB00018 */ sw $s0, 0x18($sp)
|
||||
/* 07A1DC 800795DC AFA00064 */ sw $zero, 0x64($sp)
|
||||
/* 07A1E0 800795E0 AFA00054 */ sw $zero, 0x54($sp)
|
||||
/* 07A1E4 800795E4 AFA00050 */ sw $zero, 0x50($sp)
|
||||
/* 07A1E8 800795E8 24930040 */ addiu $s3, $a0, 0x40
|
||||
/* 07A1EC 800795EC 27B40064 */ addiu $s4, $sp, 0x64
|
||||
/* 07A1F0 800795F0 24150063 */ li $s5, 99
|
||||
/* 07A1F4 800795F4 2416029A */ li $s6, 666
|
||||
/* 07A1F8 800795F8 2417029B */ li $s7, 667
|
||||
/* 07A1FC 800795FC 241E029C */ li $fp, 668
|
||||
/* 07A200 80079600 02602025 */ move $a0, $s3
|
||||
.L80079604:
|
||||
/* 07A204 80079604 02802825 */ move $a1, $s4
|
||||
/* 07A208 80079608 0C0322EC */ jal osRecvMesg
|
||||
/* 07A20C 8007960C 24060001 */ li $a2, 1
|
||||
/* 07A210 80079610 8FAE0064 */ lw $t6, 0x64($sp)
|
||||
/* 07A214 80079614 00000000 */ nop
|
||||
/* 07A218 80079618 11D50017 */ beq $t6, $s5, .L80079678
|
||||
/* 07A21C 8007961C 00000000 */ nop
|
||||
/* 07A220 80079620 11D60009 */ beq $t6, $s6, .L80079648
|
||||
/* 07A224 80079624 00000000 */ nop
|
||||
/* 07A228 80079628 11D7000B */ beq $t6, $s7, .L80079658
|
||||
/* 07A22C 8007962C 00000000 */ nop
|
||||
/* 07A230 80079630 11DE000D */ beq $t6, $fp, .L80079668
|
||||
/* 07A234 80079634 2401029D */ li $at, 669
|
||||
/* 07A238 80079638 11C10013 */ beq $t6, $at, .L80079688
|
||||
/* 07A23C 8007963C 00000000 */ nop
|
||||
/* 07A240 80079640 10000020 */ b .L800796C4
|
||||
/* 07A244 80079644 8FA50064 */ lw $a1, 0x64($sp)
|
||||
.L80079648:
|
||||
/* 07A248 80079648 0C01E606 */ jal func_80079818
|
||||
/* 07A24C 8007964C 02402025 */ move $a0, $s2
|
||||
/* 07A250 80079650 1000FFEC */ b .L80079604
|
||||
/* 07A254 80079654 02602025 */ move $a0, $s3
|
||||
.L80079658:
|
||||
/* 07A258 80079658 0C01E6D1 */ jal __scHandleRSP
|
||||
/* 07A25C 8007965C 02402025 */ move $a0, $s2
|
||||
/* 07A260 80079660 1000FFE8 */ b .L80079604
|
||||
/* 07A264 80079664 02602025 */ move $a0, $s3
|
||||
.L80079668:
|
||||
/* 07A268 80079668 0C01E757 */ jal __scHandleRDP
|
||||
/* 07A26C 8007966C 02402025 */ move $a0, $s2
|
||||
/* 07A270 80079670 1000FFE4 */ b .L80079604
|
||||
/* 07A274 80079674 02602025 */ move $a0, $s3
|
||||
.L80079678:
|
||||
/* 07A278 80079678 0C01E5D8 */ jal func_80079760
|
||||
/* 07A27C 8007967C 02402025 */ move $a0, $s2
|
||||
/* 07A280 80079680 1000FFE0 */ b .L80079604
|
||||
/* 07A284 80079684 02602025 */ move $a0, $s3
|
||||
.L80079688:
|
||||
/* 07A288 80079688 8E500260 */ lw $s0, 0x260($s2)
|
||||
/* 07A28C 8007968C 26510020 */ addiu $s1, $s2, 0x20
|
||||
/* 07A290 80079690 1200FFDC */ beqz $s0, .L80079604
|
||||
/* 07A294 80079694 02602025 */ move $a0, $s3
|
||||
.L80079698:
|
||||
/* 07A298 80079698 8E040008 */ lw $a0, 8($s0)
|
||||
/* 07A29C 8007969C 02202825 */ move $a1, $s1
|
||||
/* 07A2A0 800796A0 0C03238C */ jal osSendMesg
|
||||
/* 07A2A4 800796A4 00003025 */ move $a2, $zero
|
||||
/* 07A2A8 800796A8 8E100004 */ lw $s0, 4($s0)
|
||||
/* 07A2AC 800796AC 00000000 */ nop
|
||||
/* 07A2B0 800796B0 1600FFF9 */ bnez $s0, .L80079698
|
||||
/* 07A2B4 800796B4 00000000 */ nop
|
||||
/* 07A2B8 800796B8 1000FFD2 */ b .L80079604
|
||||
/* 07A2BC 800796BC 02602025 */ move $a0, $s3
|
||||
/* 07A2C0 800796C0 8FA50064 */ lw $a1, 0x64($sp)
|
||||
.L800796C4:
|
||||
/* 07A2C4 800796C4 0C01E7D0 */ jal __scAppendList
|
||||
/* 07A2C8 800796C8 02402025 */ move $a0, $s2
|
||||
/* 07A2CC 800796CC 8E4F0274 */ lw $t7, 0x274($s2)
|
||||
/* 07A2D0 800796D0 8E480278 */ lw $t0, 0x278($s2)
|
||||
/* 07A2D4 800796D4 2DF80001 */ sltiu $t8, $t7, 1
|
||||
/* 07A2D8 800796D8 0018C840 */ sll $t9, $t8, 1
|
||||
/* 07A2DC 800796DC 2D090001 */ sltiu $t1, $t0, 1
|
||||
/* 07A2E0 800796E0 03298025 */ or $s0, $t9, $t1
|
||||
/* 07A2E4 800796E4 02003825 */ move $a3, $s0
|
||||
/* 07A2E8 800796E8 02402025 */ move $a0, $s2
|
||||
/* 07A2EC 800796EC 27A50054 */ addiu $a1, $sp, 0x54
|
||||
/* 07A2F0 800796F0 0C01E835 */ jal __scSchedule
|
||||
/* 07A2F4 800796F4 27A60050 */ addiu $a2, $sp, 0x50
|
||||
/* 07A2F8 800796F8 1050FFC2 */ beq $v0, $s0, .L80079604
|
||||
/* 07A2FC 800796FC 02602025 */ move $a0, $s3
|
||||
/* 07A300 80079700 8FA50054 */ lw $a1, 0x54($sp)
|
||||
/* 07A304 80079704 8FA60050 */ lw $a2, 0x50($sp)
|
||||
/* 07A308 80079708 0C01E7EA */ jal __scExec
|
||||
/* 07A30C 8007970C 02402025 */ move $a0, $s2
|
||||
/* 07A310 80079710 1000FFBC */ b .L80079604
|
||||
/* 07A314 80079714 02602025 */ move $a0, $s3
|
||||
/* 07A318 80079718 00000000 */ nop
|
||||
/* 07A31C 8007971C 00000000 */ nop
|
||||
/* 07A320 80079720 00000000 */ nop
|
||||
/* 07A324 80079724 00000000 */ nop
|
||||
/* 07A328 80079728 00000000 */ nop
|
||||
/* 07A32C 8007972C 00000000 */ nop
|
||||
/* 07A330 80079730 8FBF003C */ lw $ra, 0x3c($sp)
|
||||
/* 07A334 80079734 8FB00018 */ lw $s0, 0x18($sp)
|
||||
/* 07A338 80079738 8FB1001C */ lw $s1, 0x1c($sp)
|
||||
/* 07A33C 8007973C 8FB20020 */ lw $s2, 0x20($sp)
|
||||
/* 07A340 80079740 8FB30024 */ lw $s3, 0x24($sp)
|
||||
/* 07A344 80079744 8FB40028 */ lw $s4, 0x28($sp)
|
||||
/* 07A348 80079748 8FB5002C */ lw $s5, 0x2c($sp)
|
||||
/* 07A34C 8007974C 8FB60030 */ lw $s6, 0x30($sp)
|
||||
/* 07A350 80079750 8FB70034 */ lw $s7, 0x34($sp)
|
||||
/* 07A354 80079754 8FBE0038 */ lw $fp, 0x38($sp)
|
||||
/* 07A358 80079758 03E00008 */ jr $ra
|
||||
/* 07A35C 8007975C 27BD0068 */ addiu $sp, $sp, 0x68
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user