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Decompiled func_800CD240 as __osSpSetStatus

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This commit is contained in:
David Benepe
2020-07-03 15:35:33 -05:00
parent 5bd994ff50
commit 95162c2f96
8 changed files with 138 additions and 14 deletions
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asm/non_matchings/unknown_066AA0/D_8006C330.s
+1 -1
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@@ -26,7 +26,7 @@ glabel D_8006C330
/* 06CF8C 8006C38C 0C031CEF */ jal func_800C73BC
/* 06CF90 8006C390 00000000 */ nop
/* 06CF94 8006C394 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa
/* 06CF98 8006C398 0C033490 */ jal func_800CD240
/* 06CF98 8006C398 0C033490 */ jal __osSpSetStatus
/* 06CF9C 8006C39C 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82
/* 06CFA0 8006C3A0 0C033494 */ jal func_800CD250
/* 06CFA4 8006C3A4 240401D6 */ li $a0, 470
asm/non_matchings/unknown_079F50/func_80079818.s
+2 -2
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@@ -37,7 +37,7 @@ glabel func_80079818
/* 07A49C 8007989C 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa
/* 07A4A0 800798A0 AC600000 */ sw $zero, ($v1)
/* 07A4A4 800798A4 24100001 */ li $s0, 1
/* 07A4A8 800798A8 0C033490 */ jal func_800CD240
/* 07A4A8 800798A8 0C033490 */ jal __osSpSetStatus
/* 07A4AC 800798AC 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82
/* 07A4B0 800798B0 10000005 */ b .L800798C8
/* 07A4B4 800798B4 00000000 */ nop
@@ -69,7 +69,7 @@ glabel func_80079818
/* 07A510 80079910 3C01800E */ lui $at, %hi(D_800DE758) # $at, 0x800e
/* 07A514 80079914 3C0400AA */ lui $a0, (0x00AAAA82 >> 16) # lui $a0, 0xaa
/* 07A518 80079918 AC20E758 */ sw $zero, %lo(D_800DE758)($at)
/* 07A51C 8007991C 0C033490 */ jal func_800CD240
/* 07A51C 8007991C 0C033490 */ jal __osSpSetStatus
/* 07A520 80079920 3484AA82 */ ori $a0, (0x00AAAA82 & 0xFFFF) # ori $a0, $a0, 0xaa82
/* 07A524 80079924 0C033494 */ jal func_800CD250
/* 07A528 80079928 240401D6 */ li $a0, 470
asm/non_matchings/unknown_0CDE40/func_800CD240.s
-7
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@@ -1,7 +0,0 @@
glabel func_800CD240
/* 0CDE40 800CD240 3C0EA404 */ lui $t6, 0xa404
/* 0CDE44 800CD244 03E00008 */ jr $ra
/* 0CDE48 800CD248 ADC40010 */ sw $a0, 0x10($t6)
/* 0CDE4C 800CD24C 00000000 */ nop
asm/non_matchings/unknown_0D29F0/func_800D200C.s
+1 -1
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@@ -24,7 +24,7 @@ glabel func_800D200C
/* 0D2C60 800D2060 8FA4001C */ lw $a0, 0x1c($sp)
/* 0D2C64 800D2064 0C03518C */ jal func_800D4630
/* 0D2C68 800D2068 24050040 */ li $a1, 64
/* 0D2C6C 800D206C 0C033490 */ jal func_800CD240
/* 0D2C6C 800D206C 0C033490 */ jal __osSpSetStatus
/* 0D2C70 800D2070 24042B00 */ li $a0, 11008
/* 0D2C74 800D2074 3C040400 */ lui $a0, (0x04001000 >> 16) # lui $a0, 0x400
/* 0D2C78 800D2078 0C035900 */ jal func_800D6400
asm/non_matchings/unknown_0D29F0/func_800D216C.s
+1 -1
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@@ -11,7 +11,7 @@ glabel func_800D216C
/* 0D2D8C 800D218C 1440FFFD */ bnez $v0, .L800D2184
/* 0D2D90 800D2190 00000000 */ nop
.L800D2194:
/* 0D2D94 800D2194 0C033490 */ jal func_800CD240
/* 0D2D94 800D2194 0C033490 */ jal __osSpSetStatus
/* 0D2D98 800D2198 24040125 */ li $a0, 293
/* 0D2D9C 800D219C 8FBF0014 */ lw $ra, 0x14($sp)
/* 0D2DA0 800D21A0 27BD0018 */ addiu $sp, $sp, 0x18
asm/non_matchings/unknown_0D2E40/func_800D2240.s
+1 -1
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@@ -1,7 +1,7 @@
glabel func_800D2240
/* 0D2E40 800D2240 27BDFFE8 */ addiu $sp, $sp, -0x18
/* 0D2E44 800D2244 AFBF0014 */ sw $ra, 0x14($sp)
/* 0D2E48 800D2248 0C033490 */ jal func_800CD240
/* 0D2E48 800D2248 0C033490 */ jal __osSpSetStatus
/* 0D2E4C 800D224C 24040400 */ li $a0, 1024
/* 0D2E50 800D2250 8FBF0014 */ lw $ra, 0x14($sp)
/* 0D2E54 800D2254 27BD0018 */ addiu $sp, $sp, 0x18
include/hardware.h
+128
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@@ -0,0 +1,128 @@
#ifndef _HARDWARE_H_
#define _HARDWARE_H_
#include "types.h"
#define HW_REG(reg, type) *(volatile type *)(u32*)(reg | 0xa0000000)
#define AI_DRAM_ADDR_REG 0x04500000
#define AI_LEN_REG 0x04500004
#define AI_CONTROL_REG 0x04500008
#define AI_STATUS_REG 0x0450000C
#define AI_STATUS_AI_FULL (1 << 31)
#define AI_STATUS_AI_BUSY (1 << 30)
#define AI_DACRATE_REG 0x04500010
#define AI_BITRATE_REG 0x04500014
#define VI_STATUS_REG 0x04400000
#define VI_CONTROL_REG 0x04400000
#define VI_ORIGIN_REG 0x04400004
#define VI_DRAM_ADDR_REG 0x04400004
#define VI_WIDTH_REG 0x04400008
#define VI_H_WIDTH_REG 0x04400008
#define VI_INTR_REG 0x0440000C
#define VI_V_INTER_REG 0x0440000C
#define VI_CURRENT_REG 0x04400010
#define VI_V_CURRENT_LINE_REG 0x04400010
#define VI_BURST_REG 0x04400014
#define VI_TIMING_REG 0x04400014
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
#define VI_H_SYNC_LEAP_REG 0x04400020
#define VI_H_START_REG 0x04400024 //VI horizontal video
#define VI_H_VIDEO_REG 0x04400024
#define VI_V_START_REG 0x04400028 //VI vertical video
#define VI_V_VIDEO_REG 0x04400028
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
#define SP_IMEM_START 0x04001000
#define SP_DMEM_START 0x04000000
#define SP_MEM_ADDR_REG 0x04040000
#define SP_DRAM_ADDR_REG 0x04040004
#define SP_RD_LEN_REG 0x04040008
#define SP_WR_LEN_REG 0x0404000C
#define SP_STATUS_REG 0x04040010
#define SP_PC_REG 0x04080000
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
#define PI_RD_LEN_REG 0x04600008 //PI read length
#define PI_WR_LEN_REG 0x0460000C //PI write length
#define PI_STATUS_REG 0x04600010 //PI status
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
#define PI_DOMAIN1_REG 0x04600014
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
#define PI_DOMAIN2_REG 0x04600024
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_STATUS_BUSY 0x1
#define PI_STATUS_IOBUSY 0x2
#define PI_STATUS_ERROR 0x3
#define PI_STATUS_RESET_CONTROLLER 0x1
#define PI_STATUS_CLEAR_INTR 0x2
#define SI_DRAM_ADDR_REG 0x04800000
#define SI_PIF_ADDR_RD64B_REG 0x04800004
#define SI_PIF_ADDR_WR64B_REG 0x04800010
#define SI_STATUS_REG 0x04800018
#define SI_STATUS_DMA_BUSY 0x1
#define SI_STATUS_IO_READ_BUSY 0x2
#define SI_STATUS_DMA_ERROR 0x8
#define SI_STATUS_INTERRUPT (1 << 12)
#define MI_INIT_MODE_REG 0x04300000
#define MI_MODE_REG MI_INIT_MODE_REG
#define MI_VERSION_REG 0x04300004
#define MI_INTR_REG 0x04300008
#define MI_INTR_MASK_REG 0x0430000C
//https://github.com/LuigiBlood/64dd/wiki/Registers
#define ASIC_STATUS 0x05000508
#define DATA_REQUEST 0x40000000
#define C2_TRANSFER 0x10000000
#define BUFFER_MANAGER_ERROR 0x08000000
#define BUFFER_MANAGER_INTERRUPT 0x04000000
#define MECHANIC_INTERRUPT 0x02000000
#define DISK_PRESENT 0x01000000
#define BUSY_STATE 0x00800000
#define RESET_STATE 0x00400000
#define MOTOR_NOT_SPINNING 0x00100000
#define HEAD_RETRACTED 0x00080000
#define WRITE_PROTECT_ERROR 0x00040000
#define MECHANIC_ERROR 0x00020000
#define DISK_CHANGE 0x00010000
#define _64DD_PRESENT_MASK 0xFFFF
//ro
#define ASIC_BM_STATUS 0x05000510
#define MICRO_STATUS 0x02000000
#define C1_DOUBLE 0x00400000
#define C1_SINGLE 0x00200000
//wo
#define ASIC_BM_CTL 0x05000510
#define BUFFER_MANAGER_RESET 0x10000000
#define MECHANIC_INTERRUPT_RESET 0x01000000
/*- Start Buffer Manager (0x80000000)
- Buffer Manager Mode (0x40000000)
- BM Interrupt Mask (0x20000000)
- Buffer Manager Reset (0x10000000)
- Disable OR Check? (0x08000000)
- Disable C1 Correction (0x04000000)
- Block Transfer (0x02000000)
- Mechanic Interrupt Reset (0x01000000)*/
#endif
src/mips1/unknown_0CDE40.c → src/mips2/__osSpSetStatus.c
+4 -1
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@@ -3,5 +3,8 @@
#include "types.h"
#include "macros.h"
#include "hardware.h"
GLOBAL_ASM("asm/non_matchings/unknown_0CDE40/func_800CD240.s")
void __osSpSetStatus(u32 status) {
HW_REG(SP_STATUS_REG, u32) = status;
}