Match __osSiRawStartDma

lib/src/os/__osSiRawStartDma.c

@@ -0,0 +1,25 @@
+/* The comment below is needed for this file to be picked up by generate_ld */
+/* RAM_POS: 0x800CD6C0 */
+
+#include "libultra_internal.h"
+#include "src/memory.h"
+
+s32 __osSiRawStartDma(s32 direction, void *dramAddr) {
+    if (__osSiDeviceBusy())
+        return -1;
+
+    if (direction == OS_WRITE)
+        osWritebackDCache(dramAddr, 64);
+
+    IO_WRITE(SI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
+
+    if (direction == OS_READ)
+        IO_WRITE(SI_PIF_ADDR_RD64B_REG, 0x1FC007C0);
+    else
+        IO_WRITE(SI_PIF_ADDR_WR64B_REG, 0x1FC007C0);
+
+    if (direction == OS_READ)
+        osInvalDCache(dramAddr, 64);
+
+    return 0;
+}

lib/src/os/siacs.c

@@ -1,8 +1,6 @@
 /* The comment below is needed for this file to be picked up by generate_ld */
 /* RAM_POS: 0x800CD600 */
 
-#include "types.h"
-#include "macros.h"
 #include "libultra_internal.h"
 #include "controller.h"
 #include "src/memory.h"
@@ -51,5 +49,3 @@ void __osSiGetAccess(void) {
 void __osSiRelAccess(void) {
 	osSendMesg(&__osSiAccessQueue, NULL, OS_MESG_NOBLOCK);
 }
-
-GLOBAL_ASM("lib/asm/non_matchings/unknown_0CE200/__osSiRawStartDma.s")

tools/python/generate_ld.py

@@ -31,7 +31,7 @@ BSS_LIB_ORDER_FILES = [
     BUILD_DIR + '/lib/src/os/osViMgr.o',
     BUILD_DIR + '/lib/src/os/osSetEventMesg.o',
     BUILD_DIR + '/lib/src/os/controller.o',
-    BUILD_DIR + '/lib/src/os/unknown_0CE200.o'
+    BUILD_DIR + '/lib/src/os/siacs.o'
 ]
 
 class GenerateLD: