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Splat merge (#470)

Browse Source 
* First pass

* Fix n64crc and add submodules properly

* Fix other versions

* Match func_8005B818 for v80 code.

* Formatting

* Fix build for JPN in last commit. Still broken in post v77 roms though.

* Fix builds for other versions.

* Match load_menu_text for other versions.

* Fix progress script

* update m2c

* Modify asset tools to remove the LD script code.

* Fix asm file macro inclue

* Get a working splat version for us_1.0 to build from the assets tool.

* update asm differ

* Update tools again

* Fix the makefile to only compile assets when requested. This will build all versions successfully, and compile assets for us_1.0 when requested.

* First round of suggestions

* Small cleanup

* Fix the gcc_generate.py path.

* Make entrypointThreadStack

* Small addition to the last commit

* "Fix" score script. Still need to fix the score values themselves, but at least it runs and is kind of close.

* Much closer matching score script

* Fix the splat version due to a breaking change in 0.33.0 for this repo for now.

* Fix the main function name

* Add gitignore entries

* Fix the padding problem to be handled by objcopy instead of a binary pad from splat.

* Update the README and change dependencies to setup.

* Have a hasm header that can be tweaked.

* Still calculate the checksum on no_verify builds or they won't work.

* Add support for boot_custom.bin

* Fix custom boot ld code.

* Fix score script

* Fix gcc building.

* Update m2c

* Fix warning, stop ignoring mod assets, and add some handy make rules.

* Uggh, serves me right for not testing.

* First stab at modifiable entrypoint.

* Fix typo, and small README change

* Stop n64crd from defaulting to returning 6105, so we can properly fail if the CIC checksum fails. Also, fix the

* Extract custom boot script

* Update automated scripts.

* Woops, fixed the MAXCONTROLLERS thing now.

* Add the method for building binutils back. Sorry!

* Only use -m32 when the longbit says we're on a 64 bit platform.

* Woops....

* Hopefully fix arm detection for raspi ido downloads.
This commit is contained in:
Ryan Myers
2025-03-25 09:07:00 -04:00
committed by GitHub
parent 59f86699a1
commit 6db9a8d6ea
513 changed files with 33145 additions and 85304 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/workflows/UpdateScore.yml
+8 -17
View File
@@ -17,36 +17,27 @@ jobs:
- name: Install packages
run: |
sudo apt-get update
sudo apt-get install -y build-essential pkg-config git python3 libssl-dev wget binutils-mips-linux-gnu
sudo apt-get install -y build-essential libssl-dev pkg-config git python3 python3-pip binutils-mips-linux-gnu python3-venv libpcre2-dev libpcre2-8-0
- name: Get ROM
run: wget -q -O baseroms/dkr.z64 ${{secrets.ROMURL}}
run: wget -q -O baseroms/baserom.us.v77.z64 ${{secrets.ROMURL}}
- name: Verify ROM
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/dkr.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/baserom.us.v77.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
- name: Download Recomp
- name: Make Setup
run: |
wget -q -O ido-static-recomp.tar.gz https://github.com/decompals/ido-static-recomp/releases/download/v1.2/ido-5.3-recomp-linux.tar.gz
mkdir -p tools/ido-static-recomp/build5.3/out
tar -xvzf ido-static-recomp.tar.gz -C tools/ido-static-recomp/build5.3/out
make setup -j4
- name: Build Tools
- name: Make Extract
run: |
cd tools
make -j4
cd ..
- name: Extract Assets
run: |
./extract.sh
python3 tools/python/check_if_need_to_extract.py us_1.0
make extract
- name: Build ROM
run: make -j4
- name: Verify Build
run: if [[ $(sha1sum -c --quiet sha1/dkr.us_1.0.sha1) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(sha1sum -c --quiet ver/verification/dkr.us.v77.sha1) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
- name: Update Score
run: ./update-score.sh
.github/workflows/VerifyBuild.yml
+9 -17
View File
@@ -21,33 +21,25 @@ jobs:
- name: Install packages
run: |
sudo apt-get update
sudo apt-get install -y build-essential pkg-config git python3 libssl-dev wget binutils-mips-linux-gnu
sudo apt-get install -y build-essential libssl-dev pkg-config git python3 python3-pip binutils-mips-linux-gnu python3-venv libpcre2-dev libpcre2-8-0
- name: Get ROM
run: wget -q -O baseroms/dkr.z64 ${{secrets.ROMURL}}
run: wget -q -O baseroms/baserom.us.v77.z64 ${{secrets.ROMURL}}
- name: Verify ROM
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/dkr.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/baserom.us.v77.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
- name: Download Recomp
run: |
wget -q -O ido-static-recomp.tar.gz https://github.com/decompals/ido-static-recomp/releases/download/v1.2/ido-5.3-recomp-linux.tar.gz
mkdir -p tools/ido-static-recomp/build5.3/out
tar -xvzf ido-static-recomp.tar.gz -C tools/ido-static-recomp/build5.3/out
- name: Make Setup
run: make setup -j4
- name: Build Tools
run: |
cd tools
make -j4
cd ..
- name: Make Extract
run: make extract
- name: Extract Assets
run: |
./extract.sh
python3 tools/python/check_if_need_to_extract.py us_1.0
run: make assets -j4
- name: Build ROM
run: make -j4
- name: Verify Build
run: if [[ $(sha1sum -c --quiet sha1/dkr.us_1.0.sha1) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(sha1sum -c --quiet ver/verification/dkr.us.v77.sha1) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
.github/workflows/VerifyNonEquivalent.yml
+8 -16
View File
@@ -21,30 +21,22 @@ jobs:
- name: Install packages
run: |
sudo apt-get update
sudo apt-get install -y build-essential pkg-config git python3 libssl-dev wget binutils-mips-linux-gnu
sudo apt-get install -y build-essential libssl-dev pkg-config git python3 python3-pip binutils-mips-linux-gnu python3-venv libpcre2-dev libpcre2-8-0
- name: Get ROM
run: wget -q -O baseroms/dkr.z64 ${{secrets.ROMURL}}
run: wget -q -O baseroms/baserom.us.v77.z64 ${{secrets.ROMURL}}
- name: Verify ROM
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/dkr.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/baserom.us.v77.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
- name: Download Recomp
run: |
wget -q -O ido-static-recomp.tar.gz https://github.com/decompals/ido-static-recomp/releases/download/v1.2/ido-5.3-recomp-linux.tar.gz
mkdir -p tools/ido-static-recomp/build5.3/out
tar -xvzf ido-static-recomp.tar.gz -C tools/ido-static-recomp/build5.3/out
- name: Make Setup
run: make setup -j4
- name: Build Tools
run: |
cd tools
make -j4
cd ..
- name: Make Extract
run: make extract
- name: Extract Assets
run: |
./extract.sh
python3 tools/python/check_if_need_to_extract.py us_1.0
run: make assets -j4
- name: Verify NON_EQUIVALENT
run: make -j4 NON_EQUIVALENT=1
.github/workflows/VerifyNonMatching.yml
+8 -16
View File
@@ -21,30 +21,22 @@ jobs:
- name: Install packages
run: |
sudo apt-get update
sudo apt-get install -y build-essential pkg-config git python3 libssl-dev wget binutils-mips-linux-gnu
sudo apt-get install -y build-essential libssl-dev pkg-config git python3 python3-pip binutils-mips-linux-gnu python3-venv libpcre2-dev libpcre2-8-0
- name: Get ROM
run: wget -q -O baseroms/dkr.z64 ${{secrets.ROMURL}}
run: wget -q -O baseroms/baserom.us.v77.z64 ${{secrets.ROMURL}}
- name: Verify ROM
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/dkr.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
run: if [[ $(echo "0cb115d8716dbbc2922fda38e533b9fe63bb9670 baseroms/baserom.us.v77.z64" | sha1sum -c --quiet -) = "" ]]; then echo "Signature OK"; else echo "Failed"; exit 1; fi
- name: Download Recomp
run: |
wget -q -O ido-static-recomp.tar.gz https://github.com/decompals/ido-static-recomp/releases/download/v1.2/ido-5.3-recomp-linux.tar.gz
mkdir -p tools/ido-static-recomp/build5.3/out
tar -xvzf ido-static-recomp.tar.gz -C tools/ido-static-recomp/build5.3/out
- name: Make Setup
run: make setup -j4
- name: Build Tools
run: |
cd tools
make -j4
cd ..
- name: Make Extract
run: make extract
- name: Extract Assets
run: |
./extract.sh
python3 tools/python/check_if_need_to_extract.py us_1.0
run: make assets -j4
- name: Verify NON_MATCHING
run: make -j4 NON_MATCHING=1
.gitignore
+65 -39
View File
@@ -1,50 +1,76 @@
# Baseroms is where the user will place their ROM files.
baseroms/*
nonmatchings/*
# ignore all rom files
*.z64
*.n64
*.v64
# Ignore pycache
__pycache__
#Ignore any custom boot files if any.
boot_custom.bin
# Automatically generated folders should be ignored
tools/dkr_assets_tool_src/_build/
#compiled or ripped asm
asm/*
asm
build/*
build/
assets/
ucode/
!asm/assets/
!mods/*
# Linker file is automatically generated, so it should be ignored
dkr.ld
#permuter folder
nonmatchings/*
nonmatchings/
# CTX files for mips2c should be ignored as we generate those
ctx.c
ctx_includes.c
ctx.c.m2c
#binaries ripped from the ROMs
assets/*
assets_*/
assets_*/*
bin/
bin/*
ucode/*
#Folder for automatically decompiled functions output from mips2c
m2cfiles/
#compiled object files
*.slo
*.lo
*.o
*.obj
# Misc stuff that should be ignored.
.*/
!.github
#Precompiled Headers
*.gch
*.pch
# Ignore .deb packages
*.deb
#compiled dynamic libraries
*.so
*.dylib
*.dll
# Ignore batch and executable files.
*.exe
#static libraries
*.lai
*.la
*.a
*.lib
#Windows stuff
*.bat
dkr_hot_reload.py
lastRomPath.txt
gcc_safe_files.mk
*.DS_Store
*.exe
# Temp ignore for splat related stuff.
asm/data/
asm/header.s
asm/nonmatchings/
tools/asm-differ/
tools/asm-processor/
tools/ido-recomp/
tools/m2c/
ver/
#misc
__pycache__/
*__pycache__/
expected/
.*/
*.ld
*/*.ld
*.map
*/*.map
*auto.txt
*_auto.*.txt
*.*auto.txt
*/.splat_cache
.splat_cache
.splat_cache*
ctx.c
ctx.c.m2c
ctx_includes.c
tools/n64crc
!tools/build
m2cfiles/
gcc_safe_files.mk
tools/ido-recomp
tools/binutils
*.DS_Store
.gitmodules
+9 -6
View File
@@ -1,9 +1,12 @@
[submodule "tools/ido-static-recomp"]
path = tools/ido-static-recomp
url = https://github.com/decompals/ido-static-recomp
[submodule "tools/asm_processor"]
path = tools/asm_processor
url = https://github.com/simonlindholm/asm-processor.git
[submodule "tools/asm-processor"]
path = tools/asm-processor
url = https://github.com/simonlindholm/asm-processor
[submodule "tools/asm-differ"]
path = tools/asm-differ
url = https://github.com/simonlindholm/asm-differ.git
[submodule "tools/m2c"]
path = tools/m2c
url = https://github.com/matt-kempster/m2c.git
[submodule "tools/Flips"]
path = tools/Flips
url = https://github.com/Alcaro/Flips.git
Makefile
+337 -382
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File diff suppressed because it is too large Load Diff
README.md
+18 -51
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@@ -2,7 +2,7 @@
This repo contains a work-in-progress decompilation of Diddy Kong Racing for the N64. You will need to have a original copy of the ROM to extract the game's assets.
Currently, only the US 1.0 version (SHA1 = 0cb115d8716dbbc2922fda38e533b9fe63bb9670) of the game is supported. US 1.1, EU 1.0, EU 1.1, and JP are not supported at this time.
All versions are supported, and the US 1.0 version (SHA1 = 0cb115d8716dbbc2922fda38e533b9fe63bb9670) of the game is the default if not specified.
<!-- README_SCORE_SUMMARY_BEGIN -->
As of March 20, 2025, this is our current score:
@@ -19,23 +19,19 @@ As of March 20, 2025, this is our current score:
* `gcc`, Version 8.0 or higher
* `make`, Version 4.2 or higher
* `python3`
* `wget`
* `libpcre2-dev` and `libpcre2-8-0` (Not technically required, but will speedup extracting/building some assets.)
* `gcc-mips-linux-gnu` is optionally used if compiling NON_MATCHING with COMPILER=gcc
`sudo apt install build-essential pkg-config git python3 wget libpcre2-dev libpcre2-8-0`
### binutils
You are not required to install a binutils package, but it does speed up the initial setup if you do have it installed.
* Ubuntu/Debian (x86): `sudo apt install binutils-mips-linux-gnu`
`sudo apt install build-essential pkg-config git python3 python3-pip binutils-mips-linux-gnu python3-venv libpcre2-dev libpcre2-8-0`
## Setup / Building
1. Install the dependencies
2. Place the ROM file within the `baseroms` directory.
**a.** The name of the ROM file does not matter. It will be detected automatically from an md5 checksum.
**b.** If you use a byte-swapped or little-endian ROM, then it will automatically be converted to a big-endian (.z64) ROM file.
3. Run `make` in the main directory.
**a.** The name of the ROM file does not matter. It will be detected automatically from an sha1 checksum.
3. Grab tools: `git submodule update --init --recursive`
4. Run `make setup` to install the IDO compiler, python venv, and packages required.
5. Run `make extract` to run splat to extract all required files from the baserom.
6. Run `make` in the main directory.
**a.** Use the `-jN` argument to use `N` number of threads to speed up building. For example, if you have a system with 4 cores / 4 threads, you should do `make -j4`.
### Building on macOS
@@ -43,6 +39,16 @@ You are not required to install a binutils package, but it does speed up the ini
2. Place the ROM file within the `baseroms` directory. See [Setup](#setup--building) above for more info.
3. Run `gmake` from the main directory. Note that macOS built-in `make` will not work since it does not meet the version requirements.
### Building other versions
To build other versions of the ROM, just specifcy the region and version in the make command. All examples are below:
Baserom|REGION|VERSION|Command
---|--|---|-
US 1.0 | US | v77 | `make REGION=US VERSION=v77`
PAL 1.0 | PAL | v77 | `make REGION=PAL VERSION=v77`
JPN 1.0 | JPN | v79 | `make REGION=JPN VERSION=v79`
US 1.1 | US | v80 | `make REGION=US VERSION=v80`
PAL 1.1 | PAL | v80 | `make REGION=PAL VERSION=v80`
## Modding
If you are modifying the code in the repo, then you should add `NON_MATCHING=1` to the make command.
Example: `make NON_MATCHING=1 -j4`
@@ -85,21 +91,6 @@ Example: `./rename.sh D_A4001000 SP_IMEM`
---
#### `./get_symbol.sh <ram_address>|<symbol>`
Given either a RAM address or symbol, returns its `(symbol, address)` pairing as defined in `/build/us_1.0/dkr.map`. If specified, the RAM address must be in base 16. The `0x` prefix is not required.
Example:
```
./get_symbol.sh 0xA4001000
0xA4001000 = SP_IMEM
./get_symbol.sh osCicId
0x80000310 = osCicId
```
---
#### `./score.sh`
Prints out the current completion percentage of the decomp. You do need to have an `OK` build for this to work properly.
@@ -153,27 +144,3 @@ As of March 20, 2025, this is our current score:
=======================================================================
```
<!-- README_SCORE_END -->
---
## TODO list
### Major
What should be focused on.
* Decompiling the non-matching asm files into matching C functions.
* Documenting variables & functions
### Minor
What can be done, but not essential.
* Figuring out the formats for the assets in the /assets/ folder.
* Creating tools to modify assets
### Future
These features won't be complete anytime soon.
* Add support for the other 4 versions.
asm/assets/assets.s
-13928
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File diff suppressed because it is too large Load Diff
asm/assets/ucode_data.s
-14
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@@ -1,14 +0,0 @@
# This file is automatically generated. Any changes you make to this file will get overwritten.
.include "macros.inc"
glabel aspMainDataStart
.incbin "build/us_1.0/ucode/data_audio.bin"
glabel rspF3DDKRDataDramStart
.incbin "build/us_1.0/ucode/data_f3ddkr_dram.bin"
glabel rspF3DDKRDataFifoStart
.incbin "build/us_1.0/ucode/data_f3ddkr_fifo.bin"
glabel rspF3DDKRDataXbusStart
.incbin "build/us_1.0/ucode/data_f3ddkr_xbus.bin"
glabel rspUnknown2DataStart
.incbin "build/us_1.0/ucode/data_unknown_2.bin"
asm/assets/ucode_text.s
-16
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@@ -1,16 +0,0 @@
# This file is automatically generated. Any changes you make to this file will get overwritten.
.include "macros.inc"
glabel aspMainTextStart
.incbin "build/us_1.0/ucode/ucode_audio.bin"
glabel rspF3DDKRBootStart
.incbin "build/us_1.0/ucode/ucode_boot.bin"
glabel rspF3DDKRDramStart
.incbin "build/us_1.0/ucode/ucode_f3ddkr_dram.bin"
glabel rspF3DDKRFifoStart
.incbin "build/us_1.0/ucode/ucode_f3ddkr_fifo.bin"
glabel rspF3DDKRXbusStart
.incbin "build/us_1.0/ucode/ucode_f3ddkr_xbus.bin"
glabel rspUnknown2Start
.incbin "build/us_1.0/ucode/ucode_unknown_2.bin"
asm/boot/boot.bin
BIN
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Binary file not shown.
asm/boot/rom_boot.s
-1
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@@ -1 +0,0 @@
.incbin "asm/boot/boot.bin"
asm/boot/rom_header.s
-20
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@@ -1,20 +0,0 @@
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # 64-bit instructions are used
# header
.byte 0x80, 0x37, 0x12, 0x40 # PI BSD Domain 1 register
.word 0x0000000F # clock rate setting
.word 0x80100400 # entry point
.word 0x00001447 # release
.word 0x53D440E7 # checksum1
.word 0x7519B011 # checksum2
.word 0x00000000 # unknown
.word 0x00000000 # unknown
.ascii "Diddy Kong Racing " # ROM name: 20 bytes
.word 0x00000000 # unknown
.word 0x0000004E # cartridge
.ascii "DY" # cartridge ID
.ascii "E" # country
.byte 0x00 # version
asm/collision/func_80031130.s
-265
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@@ -1,265 +0,0 @@
glabel func_80031130
/* 031D30 80031130 27BDFF90 */ addiu $sp, $sp, -0x70
/* 031D34 80031134 3C080001 */ lui $t0, (0x000186A0 >> 16) # lui $t0, 1
/* 031D38 80031138 3C09FFFE */ lui $t1, %hi(0xFFFDFFFB) # $t1, 0xfffe
/* 031D3C 8003113C AFB6002C */ sw $s6, 0x2c($sp)
/* 031D40 80031140 AFB50028 */ sw $s5, 0x28($sp)
/* 031D44 80031144 AFB40024 */ sw $s4, 0x24($sp)
/* 031D48 80031148 AFB30020 */ sw $s3, 0x20($sp)
/* 031D4C 8003114C AFB2001C */ sw $s2, 0x1c($sp)
/* 031D50 80031150 350886A0 */ ori $t0, (0x000186A0 & 0xFFFF) # ori $t0, $t0, 0x86a0
/* 031D54 80031154 35297960 */ ori $t1, (0xFFFE7960 & 0xFFFF) # ori $t1, $t1, 0x7960
/* 031D58 80031158 AFBF0030 */ sw $ra, 0x30($sp)
/* 031D5C 8003115C AFB10018 */ sw $s1, 0x18($sp)
/* 031D60 80031160 AFB00014 */ sw $s0, 0x14($sp)
/* 031D64 80031164 0100A825 */ move $s5, $t0
/* 031D68 80031168 0120A025 */ move $s4, $t1
/* 031D6C 8003116C 01009825 */ move $s3, $t0
/* 031D70 80031170 01209025 */ move $s2, $t1
/* 031D74 80031174 10800035 */ beqz $a0, .L8003124C
/* 031D78 80031178 00E0B025 */ move $s6, $a3
/* 031D7C 8003117C 000440C0 */ sll $t0, $a0, 3
/* 031D80 80031180 00044880 */ sll $t1, $a0, 2
/* 031D84 80031184 01092020 */ add $a0, $t0, $t1
/* 031D88 80031188 00852020 */ add $a0, $a0, $a1
.L8003118C:
/* 031D8C 8003118C C4A00000 */ lwc1 $f0, ($a1)
/* 031D90 80031190 C4A20008 */ lwc1 $f2, 8($a1)
/* 031D94 80031194 C4C40000 */ lwc1 $f4, ($a2)
/* 031D98 80031198 4600000D */ trunc.w.s $f0, $f0
/* 031D9C 8003119C C4C60008 */ lwc1 $f6, 8($a2)
/* 031DA0 800311A0 4600108D */ trunc.w.s $f2, $f2
/* 031DA4 800311A4 44080000 */ mfc1 $t0, $f0
/* 031DA8 800311A8 4600210D */ trunc.w.s $f4, $f4
/* 031DAC 800311AC 44091000 */ mfc1 $t1, $f2
/* 031DB0 800311B0 0288082A */ slt $at, $s4, $t0
/* 031DB4 800311B4 4600318D */ trunc.w.s $f6, $f6
/* 031DB8 800311B8 440A2000 */ mfc1 $t2, $f4
/* 031DBC 800311BC 440B3000 */ mfc1 $t3, $f6
/* 031DC0 800311C0 50200003 */ beql $at, $zero, .L800311D0
/* 031DC4 800311C4 0115082A */ slt $at, $t0, $s5
/* 031DC8 800311C8 0100A025 */ move $s4, $t0
/* 031DCC 800311CC 0115082A */ slt $at, $t0, $s5
.L800311D0:
/* 031DD0 800311D0 50200003 */ beql $at, $zero, .L800311E0
/* 031DD4 800311D4 0249082A */ slt $at, $s2, $t1
/* 031DD8 800311D8 0100A825 */ move $s5, $t0
/* 031DDC 800311DC 0249082A */ slt $at, $s2, $t1
.L800311E0:
/* 031DE0 800311E0 50200003 */ beql $at, $zero, .L800311F0
/* 031DE4 800311E4 0133082A */ slt $at, $t1, $s3
/* 031DE8 800311E8 01209025 */ move $s2, $t1
/* 031DEC 800311EC 0133082A */ slt $at, $t1, $s3
.L800311F0:
/* 031DF0 800311F0 50200003 */ beql $at, $zero, .L80031200
/* 031DF4 800311F4 028A082A */ slt $at, $s4, $t2
/* 031DF8 800311F8 01209825 */ move $s3, $t1
/* 031DFC 800311FC 028A082A */ slt $at, $s4, $t2
.L80031200:
/* 031E00 80031200 50200003 */ beql $at, $zero, .L80031210
/* 031E04 80031204 0155082A */ slt $at, $t2, $s5
/* 031E08 80031208 0140A025 */ move $s4, $t2
/* 031E0C 8003120C 0155082A */ slt $at, $t2, $s5
.L80031210:
/* 031E10 80031210 50200003 */ beql $at, $zero, .L80031220
/* 031E14 80031214 024B082A */ slt $at, $s2, $t3
/* 031E18 80031218 0140A825 */ move $s5, $t2
/* 031E1C 8003121C 024B082A */ slt $at, $s2, $t3
.L80031220:
/* 031E20 80031220 50200003 */ beql $at, $zero, .L80031230
/* 031E24 80031224 0173082A */ slt $at, $t3, $s3
/* 031E28 80031228 01609025 */ move $s2, $t3
/* 031E2C 8003122C 0173082A */ slt $at, $t3, $s3
.L80031230:
/* 031E30 80031230 50200003 */ beql $at, $zero, .L80031240
/* 031E34 80031234 24A5000C */ addiu $a1, $a1, 0xc
/* 031E38 80031238 01609825 */ move $s3, $t3
/* 031E3C 8003123C 24A5000C */ addiu $a1, $a1, 0xc
.L80031240:
/* 031E40 80031240 00A4082A */ slt $at, $a1, $a0
/* 031E44 80031244 1420FFD1 */ bnez $at, .L8003118C
/* 031E48 80031248 24C6000C */ addiu $a2, $a2, 0xc
.L8003124C:
/* 031E4C 8003124C 26B5FFEC */ addiu $s5, $s5, -0x14
/* 031E50 80031250 26940014 */ addiu $s4, $s4, 0x14
/* 031E54 80031254 0295082A */ slt $at, $s4, $s5
/* 031E58 80031258 2673FFEC */ addiu $s3, $s3, -0x14
/* 031E5C 8003125C 10200004 */ beqz $at, .L80031270
/* 031E60 80031260 26520014 */ addiu $s2, $s2, 0x14
/* 031E64 80031264 02A04025 */ move $t0, $s5
/* 031E68 80031268 0280A825 */ move $s5, $s4
/* 031E6C 8003126C 0100A025 */ move $s4, $t0
.L80031270:
/* 031E70 80031270 0253082A */ slt $at, $s2, $s3
/* 031E74 80031274 10200004 */ beqz $at, .L80031288
/* 031E78 80031278 00000000 */ nop
/* 031E7C 8003127C 02604025 */ move $t0, $s3
/* 031E80 80031280 02409825 */ move $s3, $s2
/* 031E84 80031284 01009025 */ move $s2, $t0
.L80031288:
/* 031E88 80031288 3C08800E */ lui $t0, %hi(gCurrentLevelModel) # $t0, 0x800e
/* 031E8C 8003128C 8D08C918 */ lw $t0, %lo(gCurrentLevelModel)($t0)
/* 031E90 80031290 23B10034 */ addi $s1, $sp, 0x34
/* 031E94 80031294 23B00048 */ addi $s0, $sp, 0x48
/* 031E98 80031298 850F001A */ lh $t7, 0x1a($t0)
/* 031E9C 8003129C 0000C025 */ move $t8, $zero
/* 031EA0 800312A0 8D040008 */ lw $a0, 8($t0)
/* 031EA4 800312A4 11E00023 */ beqz $t7, .L80031334
/* 031EA8 800312A8 8D0E0004 */ lw $t6, 4($t0)
.L800312AC:
/* 031EAC 800312AC 84820006 */ lh $v0, 6($a0)
/* 031EB0 800312B0 84830000 */ lh $v1, ($a0)
/* 031EB4 800312B4 24420005 */ addiu $v0, $v0, 5
/* 031EB8 800312B8 0055082A */ slt $at, $v0, $s5
/* 031EBC 800312BC 14200019 */ bnez $at, .L80031324
/* 031EC0 800312C0 2463FFFB */ addiu $v1, $v1, -5
/* 031EC4 800312C4 0283082A */ slt $at, $s4, $v1
/* 031EC8 800312C8 54200017 */ bnezl $at, .L80031328
/* 031ECC 800312CC 25EFFFFF */ addiu $t7, $t7, -1
/* 031ED0 800312D0 8488000A */ lh $t0, 0xa($a0)
/* 031ED4 800312D4 84890004 */ lh $t1, 4($a0)
/* 031ED8 800312D8 25080005 */ addiu $t0, $t0, 5
/* 031EDC 800312DC 0113082A */ slt $at, $t0, $s3
/* 031EE0 800312E0 14200010 */ bnez $at, .L80031324
/* 031EE4 800312E4 2529FFFB */ addiu $t1, %lo(0xFFFDFFFB) # addiu $t1, $t1, -5
/* 031EE8 800312E8 0249082A */ slt $at, $s2, $t1
/* 031EEC 800312EC 5420000E */ bnezl $at, .L80031328
/* 031EF0 800312F0 25EFFFFF */ addiu $t7, $t7, -1
/* 031EF4 800312F4 02A02825 */ move $a1, $s5
/* 031EF8 800312F8 02603025 */ move $a2, $s3
/* 031EFC 800312FC 02803825 */ move $a3, $s4
/* 031F00 80031300 0C00C537 */ jal func_800314DC
/* 031F04 80031304 AFB20010 */ sw $s2, 0x10($sp)
/* 031F08 80031308 A6220000 */ sh $v0, ($s1)
/* 031F0C 8003130C 27180001 */ addiu $t8, $t8, 1
/* 031F10 80031310 2401000A */ li $at, 10
/* 031F14 80031314 AE0E0000 */ sw $t6, ($s0)
/* 031F18 80031318 26310002 */ addiu $s1, $s1, 2
/* 031F1C 8003131C 13010005 */ beq $t8, $at, .L80031334
/* 031F20 80031320 26100004 */ addiu $s0, $s0, 4
.L80031324:
/* 031F24 80031324 25EFFFFF */ addiu $t7, $t7, -1
.L80031328:
/* 031F28 80031328 2484000C */ addiu $a0, $a0, 0xc
/* 031F2C 8003132C 15E0FFDF */ bnez $t7, .L800312AC
/* 031F30 80031330 25CE0044 */ addiu $t6, $t6, 0x44
.L80031334:
/* 031F34 80031334 1300005C */ beqz $t8, .L800314A8
/* 031F38 80031338 00009825 */ move $s3, $zero
/* 031F3C 8003133C 3C04800E */ lui $a0, %hi(gCurrentLevelModel) # $a0, 0x800e
/* 031F40 80031340 8C84C918 */ lw $a0, %lo(gCurrentLevelModel)($a0)
/* 031F44 80031344 3C128012 */ lui $s2, %hi(D_8011D370) # $s2, 0x8012
/* 031F48 80031348 3C198012 */ lui $t9, %hi(D_8011D374) # $t9, 0x8012
/* 031F4C 8003134C 23B10034 */ addi $s1, $sp, 0x34
/* 031F50 80031350 0018C040 */ sll $t8, $t8, 1
/* 031F54 80031354 8E52D370 */ lw $s2, %lo(D_8011D370)($s2)
/* 031F58 80031358 8F39D374 */ lw $t9, %lo(D_8011D374)($t9)
/* 031F5C 8003135C 23B00048 */ addi $s0, $sp, 0x48
/* 031F60 80031360 0238C020 */ add $t8, $s1, $t8
/* 031F64 80031364 8C840000 */ lw $a0, ($a0)
.L80031368:
/* 031F68 80031368 8E0F0000 */ lw $t7, ($s0)
/* 031F6C 8003136C 3C017FFF */ lui $at, (0x7FFFFFFF >> 16) # lui $at, 0x7fff
/* 031F70 80031370 3421FFFF */ ori $at, (0x7FFFFFFF & 0xFFFF) # ori $at, $at, 0xffff
/* 031F74 80031374 862E0000 */ lh $t6, ($s1)
/* 031F78 80031378 01E11024 */ and $v0, $t7, $at
/* 031F7C 8003137C AE420000 */ sw $v0, ($s2)
/* 031F80 80031380 85E80020 */ lh $t0, 0x20($t7)
/* 031F84 80031384 8DED000C */ lw $t5, 0xc($t7)
/* 031F88 80031388 26730001 */ addiu $s3, $s3, 1
/* 031F8C 8003138C 000810C0 */ sll $v0, $t0, 3
/* 031F90 80031390 00081880 */ sll $v1, $t0, 2
/* 031F94 80031394 00435820 */ add $t3, $v0, $v1
/* 031F98 80031398 26520004 */ addiu $s2, $s2, 4
/* 031F9C 8003139C 27390001 */ addiu $t9, $t9, 1
/* 031FA0 800313A0 016D5820 */ add $t3, $t3, $t5
/* 031FA4 800313A4 25AC000C */ addiu $t4, $t5, 0xc
.L800313A8:
/* 031FA8 800313A8 8DA80008 */ lw $t0, 8($t5)
/* 031FAC 800313AC 31020200 */ andi $v0, $t0, 0x200
/* 031FB0 800313B0 14400035 */ bnez $v0, .L80031488
/* 031FB4 800313B4 2401FFFF */ li $at, -1
/* 031FB8 800313B8 56C10005 */ bnel $s6, $at, .L800313D0
/* 031FBC 800313BC 91A30000 */ lbu $v1, ($t5)
/* 031FC0 800313C0 31020100 */ andi $v0, $t0, 0x100
/* 031FC4 800313C4 54400031 */ bnezl $v0, .L8003148C
/* 031FC8 800313C8 25AD000C */ addiu $t5, $t5, 0xc
/* 031FCC 800313CC 91A30000 */ lbu $v1, ($t5)
.L800313D0:
/* 031FD0 800313D0 240100FF */ li $at, 255
/* 031FD4 800313D4 00005025 */ move $t2, $zero
/* 031FD8 800313D8 50610010 */ beql $v1, $at, .L8003141C
/* 031FDC 800313DC 85A80004 */ lh $t0, 4($t5)
/* 031FE0 800313E0 000318C0 */ sll $v1, $v1, 3
/* 031FE4 800313E4 00641820 */ add $v1, $v1, $a0
/* 031FE8 800313E8 806A0007 */ lb $t2, 7($v1)
/* 031FEC 800313EC 2401000B */ li $at, 11
/* 031FF0 800313F0 11410025 */ beq $t2, $at, .L80031488
/* 031FF4 800313F4 24010002 */ li $at, 2
/* 031FF8 800313F8 16C10003 */ bne $s6, $at, .L80031408
/* 031FFC 800313FC 24010011 */ li $at, 17
/* 032000 80031400 51410022 */ beql $t2, $at, .L8003148C
/* 032004 80031404 25AD000C */ addiu $t5, $t5, 0xc
.L80031408:
/* 032008 80031408 12C00003 */ beqz $s6, .L80031418
/* 03200C 8003140C 24010012 */ li $at, 18
/* 032010 80031410 5141001E */ beql $t2, $at, .L8003148C
/* 032014 80031414 25AD000C */ addiu $t5, $t5, 0xc
.L80031418:
/* 032018 80031418 85A80004 */ lh $t0, 4($t5)
.L8003141C:
/* 03201C 8003141C 85890004 */ lh $t1, 4($t4)
/* 032020 80031420 8DE60010 */ lw $a2, 0x10($t7)
/* 032024 80031424 8DE70014 */ lw $a3, 0x14($t7)
/* 032028 80031428 00094840 */ sll $t1, $t1, 1
/* 03202C 8003142C 00081040 */ sll $v0, $t0, 1
/* 032030 80031430 000818C0 */ sll $v1, $t0, 3
/* 032034 80031434 00C92820 */ add $a1, $a2, $t1
/* 032038 80031438 00C23020 */ add $a2, $a2, $v0
/* 03203C 8003143C 00E33820 */ add $a3, $a3, $v1
.L80031440:
/* 032040 80031440 84C80000 */ lh $t0, ($a2)
/* 032044 80031444 010E4024 */ and $t0, $t0, $t6
/* 032048 80031448 310200FF */ andi $v0, $t0, 0xff
/* 03204C 8003144C 1040000A */ beqz $v0, .L80031478
/* 032050 80031450 3103FF00 */ andi $v1, $t0, 0xff00
/* 032054 80031454 50600009 */ beql $v1, $zero, .L8003147C
/* 032058 80031458 24C60002 */ addiu $a2, $a2, 2
/* 03205C 8003145C AE470000 */ sw $a3, ($s2)
/* 032060 80031460 26730001 */ addiu $s3, $s3, 1
/* 032064 80031464 240101F4 */ li $at, 500
/* 032068 80031468 A32A0000 */ sb $t2, ($t9)
/* 03206C 8003146C 26520004 */ addiu $s2, $s2, 4
/* 032070 80031470 1261000D */ beq $s3, $at, .L800314A8
/* 032074 80031474 27390001 */ addiu $t9, $t9, 1
.L80031478:
/* 032078 80031478 24C60002 */ addiu $a2, $a2, 2
.L8003147C:
/* 03207C 8003147C 00C5082A */ slt $at, $a2, $a1
/* 032080 80031480 1420FFEF */ bnez $at, .L80031440
/* 032084 80031484 24E70008 */ addiu $a3, $a3, 8
.L80031488:
/* 032088 80031488 25AD000C */ addiu $t5, $t5, 0xc
.L8003148C:
/* 03208C 8003148C 01AB082A */ slt $at, $t5, $t3
/* 032090 80031490 1420FFC5 */ bnez $at, .L800313A8
/* 032094 80031494 258C000C */ addiu $t4, $t4, 0xc
/* 032098 80031498 26310002 */ addiu $s1, $s1, 2
/* 03209C 8003149C 0238082A */ slt $at, $s1, $t8
/* 0320A0 800314A0 1420FFB1 */ bnez $at, .L80031368
/* 0320A4 800314A4 26100004 */ addiu $s0, $s0, 4
.L800314A8:
/* 0320A8 800314A8 8FBF0030 */ lw $ra, 0x30($sp)
/* 0320AC 800314AC 3C018012 */ lui $at, %hi(D_8011D378) # $at, 0x8012
/* 0320B0 800314B0 AC33D378 */ sw $s3, %lo(D_8011D378)($at)
/* 0320B4 800314B4 8FB6002C */ lw $s6, 0x2c($sp)
/* 0320B8 800314B8 8FB50028 */ lw $s5, 0x28($sp)
/* 0320BC 800314BC 8FB40024 */ lw $s4, 0x24($sp)
/* 0320C0 800314C0 8FB30020 */ lw $s3, 0x20($sp)
/* 0320C4 800314C4 8FB2001C */ lw $s2, 0x1c($sp)
/* 0320C8 800314C8 8FB10018 */ lw $s1, 0x18($sp)
/* 0320CC 800314CC 8FB00014 */ lw $s0, 0x14($sp)
/* 0320D0 800314D0 00001025 */ move $v0, $zero
/* 0320D4 800314D4 03E00008 */ jr $ra
/* 0320D8 800314D8 27BD0070 */ addiu $sp, $sp, 0x70
asm/collision/func_800314DC.s
-90
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@@ -1,90 +0,0 @@
glabel func_800314DC
/* 0320DC 800314DC 10800046 */ beqz $a0, .L800315F8
/* 0320E0 800314E0 00001025 */ move $v0, $zero
/* 0320E4 800314E4 84880000 */ lh $t0, ($a0)
/* 0320E8 800314E8 8FAD0010 */ lw $t5, 0x10($sp)
/* 0320EC 800314EC 84890004 */ lh $t1, 4($a0)
/* 0320F0 800314F0 00E8082A */ slt $at, $a3, $t0
/* 0320F4 800314F4 848A0006 */ lh $t2, 6($a0)
/* 0320F8 800314F8 10200002 */ beqz $at, .L80031504
/* 0320FC 800314FC 848B000A */ lh $t3, 0xa($a0)
/* 032100 80031500 01003825 */ move $a3, $t0
.L80031504:
/* 032104 80031504 00A8082A */ slt $at, $a1, $t0
/* 032108 80031508 50200003 */ beql $at, $zero, .L80031518
/* 03210C 8003150C 01A9082A */ slt $at, $t5, $t1
/* 032110 80031510 01002825 */ move $a1, $t0
/* 032114 80031514 01A9082A */ slt $at, $t5, $t1
.L80031518:
/* 032118 80031518 50200003 */ beql $at, $zero, .L80031528
/* 03211C 8003151C 00C9082A */ slt $at, $a2, $t1
/* 032120 80031520 01206825 */ move $t5, $t1
/* 032124 80031524 00C9082A */ slt $at, $a2, $t1
.L80031528:
/* 032128 80031528 50200003 */ beql $at, $zero, .L80031538
/* 03212C 8003152C 0147082A */ slt $at, $t2, $a3
/* 032130 80031530 01203025 */ move $a2, $t1
/* 032134 80031534 0147082A */ slt $at, $t2, $a3
.L80031538:
/* 032138 80031538 50200003 */ beql $at, $zero, .L80031548
/* 03213C 8003153C 0145082A */ slt $at, $t2, $a1
/* 032140 80031540 01403825 */ move $a3, $t2
/* 032144 80031544 0145082A */ slt $at, $t2, $a1
.L80031548:
/* 032148 80031548 50200003 */ beql $at, $zero, .L80031558
/* 03214C 8003154C 016D082A */ slt $at, $t3, $t5
/* 032150 80031550 01402825 */ move $a1, $t2
/* 032154 80031554 016D082A */ slt $at, $t3, $t5
.L80031558:
/* 032158 80031558 50200003 */ beql $at, $zero, .L80031568
/* 03215C 8003155C 0166082A */ slt $at, $t3, $a2
/* 032160 80031560 01606825 */ move $t5, $t3
/* 032164 80031564 0166082A */ slt $at, $t3, $a2
.L80031568:
/* 032168 80031568 50200003 */ beql $at, $zero, .L80031578
/* 03216C 8003156C 01485022 */ sub $t2, $t2, $t0
/* 032170 80031570 01603025 */ move $a2, $t3
/* 032174 80031574 01485022 */ sub $t2, $t2, $t0
.L80031578:
/* 032178 80031578 000A50C3 */ sra $t2, $t2, 3
/* 03217C 8003157C 254A0001 */ addiu $t2, $t2, 1
/* 032180 80031580 24030001 */ li $v1, 1
/* 032184 80031584 01486020 */ add $t4, $t2, $t0
.L80031588:
/* 032188 80031588 0185082A */ slt $at, $t4, $a1
/* 03218C 8003158C 14200004 */ bnez $at, .L800315A0
/* 032190 80031590 00E8082A */ slt $at, $a3, $t0
/* 032194 80031594 54200003 */ bnezl $at, .L800315A4
/* 032198 80031598 00031840 */ sll $v1, $v1, 1
/* 03219C 8003159C 00431025 */ or $v0, $v0, $v1
.L800315A0:
/* 0321A0 800315A0 00031840 */ sll $v1, $v1, 1
.L800315A4:
/* 0321A4 800315A4 28610100 */ slti $at, $v1, 0x100
/* 0321A8 800315A8 018A6020 */ add $t4, $t4, $t2
/* 0321AC 800315AC 1420FFF6 */ bnez $at, .L80031588
/* 0321B0 800315B0 010A4020 */ add $t0, $t0, $t2
/* 0321B4 800315B4 01695022 */ sub $t2, $t3, $t1
/* 0321B8 800315B8 000A50C3 */ sra $t2, $t2, 3
/* 0321BC 800315BC 254A0001 */ addiu $t2, $t2, 1
/* 0321C0 800315C0 01496020 */ add $t4, $t2, $t1
/* 0321C4 800315C4 01204025 */ move $t0, $t1
.L800315C8:
/* 0321C8 800315C8 0186082A */ slt $at, $t4, $a2
/* 0321CC 800315CC 14200004 */ bnez $at, .L800315E0
/* 0321D0 800315D0 01A8082A */ slt $at, $t5, $t0
/* 0321D4 800315D4 54200003 */ bnezl $at, .L800315E4
/* 0321D8 800315D8 00031840 */ sll $v1, $v1, 1
/* 0321DC 800315DC 00431025 */ or $v0, $v0, $v1
.L800315E0:
/* 0321E0 800315E0 00031840 */ sll $v1, $v1, 1
.L800315E4:
/* 0321E4 800315E4 3C010001 */ lui $at, 1
/* 0321E8 800315E8 0061082A */ slt $at, $v1, $at
/* 0321EC 800315EC 018A6020 */ add $t4, $t4, $t2
/* 0321F0 800315F0 1420FFF5 */ bnez $at, .L800315C8
/* 0321F4 800315F4 010A4020 */ add $t0, $t0, $t2
.L800315F8:
/* 0321F8 800315F8 03E00008 */ jr $ra
/* 0321FC 800315FC 00000000 */ nop
asm/collision/func_80031600.s
-397
View File
@@ -1,397 +0,0 @@
.section .rodata
glabel D_800E5F60
.float -0.1
glabel D_800E5F64
.float -0.1
glabel D_800E5F68
.float 0.707
glabel D_800E5F6C
.float 0.45
glabel D_800E5F70
.float -0.1
.section .text
glabel func_80031600
/* 032200 80031600 24080001 */ li $t0, 1
/* 032204 80031604 A3A80001 */ sb $t0, 1($sp)
/* 032208 80031608 3C088012 */ lui $t0, %hi(D_8011D378) # $t0, 0x8012
/* 03220C 8003160C 8D08D378 */ lw $t0, %lo(D_8011D378)($t0)
/* 032210 80031610 3C018012 */ lui $at, %hi(D_8011B0F0) # $at, 0x8012
/* 032214 80031614 A3A00000 */ sb $zero, ($sp)
/* 032218 80031618 1100014C */ beqz $t0, .L80031B4C
/* 03221C 8003161C AC20B0F0 */ sw $zero, %lo(D_8011B0F0)($at)
.L80031620:
/* 032220 80031620 00007025 */ move $t6, $zero
.L80031624:
/* 032224 80031624 3C0D8012 */ lui $t5, %hi(D_8011D374) # $t5, 0x8012
/* 032228 80031628 3C098012 */ lui $t1, %hi(D_8011D370) # $t1, 0x8012
/* 03222C 8003162C 3C088012 */ lui $t0, %hi(D_8011D378) # $t0, 0x8012
/* 032230 80031630 00007825 */ move $t7, $zero
/* 032234 80031634 8DADD374 */ lw $t5, %lo(D_8011D374)($t5)
/* 032238 80031638 8D29D370 */ lw $t1, %lo(D_8011D370)($t1)
/* 03223C 8003163C 8D08D378 */ lw $t0, %lo(D_8011D378)($t0)
.L80031640:
/* 032240 80031640 8D2A0000 */ lw $t2, ($t1)
/* 032244 80031644 59400006 */ blezl $t2, .L80031660
/* 032248 80031648 95420000 */ lhu $v0, ($t2)
/* 03224C 8003164C 3C0B8000 */ lui $t3, 0x8000
/* 032250 80031650 016A5825 */ or $t3, $t3, $t2
/* 032254 80031654 0800C651 */ j .L80031944
/* 032258 80031658 8D6B0018 */ lw $t3, 0x18($t3)
/* 03225C 8003165C 95420000 */ lhu $v0, ($t2)
.L80031660:
/* 032260 80031660 C4A80000 */ lwc1 $f8, ($a1)
/* 032264 80031664 C4AA0004 */ lwc1 $f10, 4($a1)
/* 032268 80031668 00021100 */ sll $v0, $v0, 4
/* 03226C 8003166C 004B1021 */ addu $v0, $v0, $t3
/* 032270 80031670 C4400000 */ lwc1 $f0, ($v0)
/* 032274 80031674 C4420004 */ lwc1 $f2, 4($v0)
/* 032278 80031678 C4440008 */ lwc1 $f4, 8($v0)
/* 03227C 8003167C 46004202 */ mul.s $f8, $f8, $f0
/* 032280 80031680 C4B00008 */ lwc1 $f16, 8($a1)
/* 032284 80031684 C446000C */ lwc1 $f6, 0xc($v0)
/* 032288 80031688 46025282 */ mul.s $f10, $f10, $f2
/* 03228C 8003168C 3C01800E */ lui $at, %hi(D_800E5F60) # $at, 0x800e
/* 032290 80031690 46048402 */ mul.s $f16, $f16, $f4
/* 032294 80031694 460A4200 */ add.s $f8, $f8, $f10
/* 032298 80031698 46104200 */ add.s $f8, $f8, $f16
/* 03229C 8003169C 46064480 */ add.s $f18, $f8, $f6
/* 0322A0 800316A0 C4C80000 */ lwc1 $f8, ($a2)
/* 0322A4 800316A4 46089481 */ sub.s $f18, $f18, $f8
/* 0322A8 800316A8 C4285F60 */ lwc1 $f8, %lo(D_800E5F60)($at)
/* 0322AC 800316AC 46089034 */ c.olt.s $f18, $f8
/* 0322B0 800316B0 450200A5 */ bc1fl .L80031948
/* 0322B4 800316B4 2508FFFF */ addiu $t0, $t0, -1
/* 0322B8 800316B8 C4880000 */ lwc1 $f8, ($a0)
/* 0322BC 800316BC C48A0004 */ lwc1 $f10, 4($a0)
/* 0322C0 800316C0 C4900008 */ lwc1 $f16, 8($a0)
/* 0322C4 800316C4 46004202 */ mul.s $f8, $f8, $f0
/* 0322C8 800316C8 3C01800E */ lui $at, %hi(D_800E5F64) # $at, 0x800e
/* 0322CC 800316CC 46025282 */ mul.s $f10, $f10, $f2
/* 0322D0 800316D0 460A4200 */ add.s $f8, $f8, $f10
/* 0322D4 800316D4 46048402 */ mul.s $f16, $f16, $f4
/* 0322D8 800316D8 46104200 */ add.s $f8, $f8, $f16
/* 0322DC 800316DC 46064400 */ add.s $f16, $f8, $f6
/* 0322E0 800316E0 C4C80000 */ lwc1 $f8, ($a2)
/* 0322E4 800316E4 46088401 */ sub.s $f16, $f16, $f8
/* 0322E8 800316E8 C4285F64 */ lwc1 $f8, %lo(D_800E5F64)($at)
/* 0322EC 800316EC 46088034 */ c.olt.s $f16, $f8
/* 0322F0 800316F0 45030095 */ bc1tl .L80031948
/* 0322F4 800316F4 2508FFFF */ addiu $t0, $t0, -1
/* 0322F8 800316F8 C4880000 */ lwc1 $f8, ($a0)
/* 0322FC 800316FC C4AA0000 */ lwc1 $f10, ($a1)
/* 032300 80031700 46085001 */ sub.s $f0, $f10, $f8
/* 032304 80031704 C4880004 */ lwc1 $f8, 4($a0)
/* 032308 80031708 C4AA0004 */ lwc1 $f10, 4($a1)
/* 03230C 8003170C 46085081 */ sub.s $f2, $f10, $f8
/* 032310 80031710 C4880008 */ lwc1 $f8, 8($a0)
/* 032314 80031714 C4AA0008 */ lwc1 $f10, 8($a1)
/* 032318 80031718 46085101 */ sub.s $f4, $f10, $f8
/* 03231C 8003171C 44805000 */ mtc1 $zero, $f10
/* 032320 80031720 46128201 */ sub.s $f8, $f16, $f18
/* 032324 80031724 460A4033 */ c.ueq.s $f8, $f10
/* 032328 80031728 45010002 */ bc1t .L80031734
/* 03232C 8003172C 00000000 */ nop
/* 032330 80031730 46088283 */ div.s $f10, $f16, $f8
.L80031734:
/* 032334 80031734 460A0002 */ mul.s $f0, $f0, $f10
/* 032338 80031738 C4860000 */ lwc1 $f6, ($a0)
/* 03233C 8003173C 3C014080 */ li $at, 0x40800000 # 4.000000
/* 032340 80031740 460A1082 */ mul.s $f2, $f2, $f10
/* 032344 80031744 240C0003 */ li $t4, 3
/* 032348 80031748 460A2102 */ mul.s $f4, $f4, $f10
/* 03234C 8003174C 44815000 */ mtc1 $at, $f10
/* 032350 80031750 46003000 */ add.s $f0, $f6, $f0
/* 032354 80031754 C4860004 */ lwc1 $f6, 4($a0)
/* 032358 80031758 46023080 */ add.s $f2, $f6, $f2
/* 03235C 8003175C C4860008 */ lwc1 $f6, 8($a0)
/* 032360 80031760 46043100 */ add.s $f4, $f6, $f4
.L80031764:
/* 032364 80031764 95430002 */ lhu $v1, 2($t2)
/* 032368 80031768 0000C025 */ move $t8, $zero
/* 03236C 8003176C 30798000 */ andi $t9, $v1, 0x8000
/* 032370 80031770 53200004 */ beql $t9, $zero, .L80031784
/* 032374 80031774 00031900 */ sll $v1, $v1, 4
/* 032378 80031778 30637FFF */ andi $v1, $v1, 0x7fff
/* 03237C 8003177C 24180001 */ li $t8, 1
/* 032380 80031780 00031900 */ sll $v1, $v1, 4
.L80031784:
/* 032384 80031784 006B1821 */ addu $v1, $v1, $t3
/* 032388 80031788 C4660000 */ lwc1 $f6, ($v1)
/* 03238C 8003178C C4680004 */ lwc1 $f8, 4($v1)
/* 032390 80031790 46060182 */ mul.s $f6, $f0, $f6
/* 032394 80031794 00000000 */ nop
/* 032398 80031798 46081202 */ mul.s $f8, $f2, $f8
/* 03239C 8003179C 46083180 */ add.s $f6, $f6, $f8
/* 0323A0 800317A0 C4680008 */ lwc1 $f8, 8($v1)
/* 0323A4 800317A4 46082202 */ mul.s $f8, $f4, $f8
/* 0323A8 800317A8 46083180 */ add.s $f6, $f6, $f8
/* 0323AC 800317AC C468000C */ lwc1 $f8, 0xc($v1)
/* 0323B0 800317B0 13000002 */ beqz $t8, .L800317BC
/* 0323B4 800317B4 46083180 */ add.s $f6, $f6, $f8
/* 0323B8 800317B8 46003187 */ neg.s $f6, $f6
.L800317BC:
/* 0323BC 800317BC 460A3036 */ c.ole.s $f6, $f10
/* 0323C0 800317C0 45020061 */ bc1fl .L80031948
/* 0323C4 800317C4 2508FFFF */ addiu $t0, $t0, -1
/* 0323C8 800317C8 258CFFFF */ addiu $t4, $t4, -1
/* 0323CC 800317CC 1580FFE5 */ bnez $t4, .L80031764
/* 0323D0 800317D0 254A0002 */ addiu $t2, $t2, 2
/* 0323D4 800317D4 3C01800E */ lui $at, %hi(D_800E5F68) # $at, 0x800e
/* 0323D8 800317D8 C4205F68 */ lwc1 $f0, %lo(D_800E5F68)($at)
/* 0323DC 800317DC C4420004 */ lwc1 $f2, 4($v0)
/* 0323E0 800317E0 C4440008 */ lwc1 $f4, 8($v0)
/* 0323E4 800317E4 46001035 */ c.ult.s $f2, $f0
/* 0323E8 800317E8 C4400000 */ lwc1 $f0, ($v0)
/* 0323EC 800317EC 45010016 */ bc1t .L80031848
/* 0323F0 800317F0 00000000 */ nop
/* 0323F4 800317F4 81A30000 */ lb $v1, ($t5)
/* 0323F8 800317F8 24010004 */ li $at, 4
/* 0323FC 800317FC 10610012 */ beq $v1, $at, .L80031848
/* 032400 80031800 00000000 */ nop
/* 032404 80031804 3C038012 */ lui $v1, %hi(D_8011B0F4) # $v1, 0x8012
/* 032408 80031808 8C63B0F4 */ lw $v1, %lo(D_8011B0F4)($v1)
/* 03240C 8003180C 1460000E */ bnez $v1, .L80031848
/* 032410 80031810 00000000 */ nop
/* 032414 80031814 C4A60000 */ lwc1 $f6, ($a1)
/* 032418 80031818 46003002 */ mul.s $f0, $f6, $f0
/* 03241C 8003181C C4A60008 */ lwc1 $f6, 8($a1)
/* 032420 80031820 46043102 */ mul.s $f4, $f6, $f4
/* 032424 80031824 C446000C */ lwc1 $f6, 0xc($v0)
/* 032428 80031828 46040000 */ add.s $f0, $f0, $f4
/* 03242C 8003182C C4A40008 */ lwc1 $f4, 8($a1)
/* 032430 80031830 46060000 */ add.s $f0, $f0, $f6
/* 032434 80031834 C4C60000 */ lwc1 $f6, ($a2)
/* 032438 80031838 46003001 */ sub.s $f0, $f6, $f0
/* 03243C 8003183C 46020083 */ div.s $f2, $f0, $f2
/* 032440 80031840 0800C632 */ j .L800318C8
/* 032444 80031844 C4A00000 */ lwc1 $f0, ($a1)
.L80031848:
/* 032448 80031848 3C01800E */ lui $at, %hi(D_800E5F6C) # $at, 0x800e
/* 03244C 8003184C C42A5F6C */ lwc1 $f10, %lo(D_800E5F6C)($at)
/* 032450 80031850 460A1034 */ c.olt.s $f2, $f10
/* 032454 80031854 45000012 */ bc1f .L800318A0
/* 032458 80031858 00000000 */ nop
/* 03245C 8003185C 3C038012 */ lui $v1, %hi(D_8011B0F4) # $v1, 0x8012
/* 032460 80031860 8C63B0F4 */ lw $v1, %lo(D_8011B0F4)($v1)
/* 032464 80031864 24010002 */ li $at, 2
/* 032468 80031868 1061000D */ beq $v1, $at, .L800318A0
/* 03246C 8003186C 00000000 */ nop
/* 032470 80031870 24030001 */ li $v1, 1
/* 032474 80031874 3C018012 */ lui $at, %hi(D_8011B0F0) # $at, 0x8012
/* 032478 80031878 AC23B0F0 */ sw $v1, %lo(D_8011B0F0)($at)
/* 03247C 8003187C C4460000 */ lwc1 $f6, ($v0)
/* 032480 80031880 3C018012 */ lui $at, %hi(D_8011B0E4) # $at, 0x8012
/* 032484 80031884 E426B0E4 */ swc1 $f6, %lo(D_8011B0E4)($at)
/* 032488 80031888 C4460004 */ lwc1 $f6, 4($v0)
/* 03248C 8003188C 3C018012 */ lui $at, %hi(D_8011B0E8) # $at, 0x8012
/* 032490 80031890 E426B0E8 */ swc1 $f6, %lo(D_8011B0E8)($at)
/* 032494 80031894 C4460008 */ lwc1 $f6, 8($v0)
/* 032498 80031898 3C018012 */ lui $at, %hi(D_8011B0EC) # $at, 0x8012
/* 03249C 8003189C E426B0EC */ swc1 $f6, %lo(D_8011B0EC)($at)
.L800318A0:
/* 0324A0 800318A0 46120002 */ mul.s $f0, $f0, $f18
/* 0324A4 800318A4 C4A60000 */ lwc1 $f6, ($a1)
/* 0324A8 800318A8 46121082 */ mul.s $f2, $f2, $f18
/* 0324AC 800318AC 00000000 */ nop
/* 0324B0 800318B0 46122102 */ mul.s $f4, $f4, $f18
/* 0324B4 800318B4 46003001 */ sub.s $f0, $f6, $f0
/* 0324B8 800318B8 C4A60004 */ lwc1 $f6, 4($a1)
/* 0324BC 800318BC 46023081 */ sub.s $f2, $f6, $f2
/* 0324C0 800318C0 C4A60008 */ lwc1 $f6, 8($a1)
/* 0324C4 800318C4 46043101 */ sub.s $f4, $f6, $f4
.L800318C8:
/* 0324C8 800318C8 3C038012 */ lui $v1, %hi(D_8011B0F0) # $v1, 0x8012
/* 0324CC 800318CC 8C63B0F0 */ lw $v1, %lo(D_8011B0F0)($v1)
/* 0324D0 800318D0 5460000B */ bnezl $v1, .L80031900
/* 0324D4 800318D4 81AC0000 */ lb $t4, ($t5)
/* 0324D8 800318D8 C4460000 */ lwc1 $f6, ($v0)
/* 0324DC 800318DC 3C018012 */ lui $at, %hi(D_8011B0E4) # $at, 0x8012
/* 0324E0 800318E0 E426B0E4 */ swc1 $f6, %lo(D_8011B0E4)($at)
/* 0324E4 800318E4 C4460004 */ lwc1 $f6, 4($v0)
/* 0324E8 800318E8 3C018012 */ lui $at, %hi(D_8011B0E8) # $at, 0x8012
/* 0324EC 800318EC E426B0E8 */ swc1 $f6, %lo(D_8011B0E8)($at)
/* 0324F0 800318F0 C4460008 */ lwc1 $f6, 8($v0)
/* 0324F4 800318F4 3C018012 */ lui $at, %hi(D_8011B0EC) # $at, 0x8012
/* 0324F8 800318F8 E426B0EC */ swc1 $f6, %lo(D_8011B0EC)($at)
/* 0324FC 800318FC 81AC0000 */ lb $t4, ($t5)
.L80031900:
/* 032500 80031900 80E20000 */ lb $v0, ($a3)
/* 032504 80031904 004C082A */ slt $at, $v0, $t4
/* 032508 80031908 50200003 */ beql $at, $zero, .L80031918
/* 03250C 8003190C 25CE0001 */ addiu $t6, $t6, 1
/* 032510 80031910 A0EC0000 */ sb $t4, ($a3)
/* 032514 80031914 25CE0001 */ addiu $t6, $t6, 1
.L80031918:
/* 032518 80031918 29C1000B */ slti $at, $t6, 0xb
/* 03251C 8003191C 14200005 */ bnez $at, .L80031934
/* 032520 80031920 240F0001 */ li $t7, 1
/* 032524 80031924 00007825 */ move $t7, $zero
/* 032528 80031928 C4800000 */ lwc1 $f0, ($a0)
/* 03252C 8003192C C4820004 */ lwc1 $f2, 4($a0)
/* 032530 80031930 C4840008 */ lwc1 $f4, 8($a0)
.L80031934:
/* 032534 80031934 E4A00000 */ swc1 $f0, ($a1)
/* 032538 80031938 E4A20004 */ swc1 $f2, 4($a1)
/* 03253C 8003193C 0800C655 */ j .L80031954
/* 032540 80031940 E4A40008 */ swc1 $f4, 8($a1)
.L80031944:
/* 032544 80031944 2508FFFF */ addiu $t0, $t0, -1
.L80031948:
/* 032548 80031948 25AD0001 */ addiu $t5, $t5, 1
/* 03254C 8003194C 1500FF3C */ bnez $t0, .L80031640
/* 032550 80031950 25290004 */ addiu $t1, $t1, 4
.L80031954:
/* 032554 80031954 15E0FF33 */ bnez $t7, .L80031624
/* 032558 80031958 00000000 */ nop
/* 03255C 8003195C 11C00008 */ beqz $t6, .L80031980
/* 032560 80031960 93AA0001 */ lbu $t2, 1($sp)
/* 032564 80031964 8FA90014 */ lw $t1, 0x14($sp)
/* 032568 80031968 8D280000 */ lw $t0, ($t1)
/* 03256C 8003196C 25080001 */ addiu $t0, $t0, 1
/* 032570 80031970 AD280000 */ sw $t0, ($t1)
/* 032574 80031974 93A80000 */ lbu $t0, ($sp)
/* 032578 80031978 010A4025 */ or $t0, $t0, $t2
/* 03257C 8003197C A3A80000 */ sb $t0, ($sp)
.L80031980:
/* 032580 80031980 000A5040 */ sll $t2, $t2, 1
/* 032584 80031984 A3AA0001 */ sb $t2, 1($sp)
/* 032588 80031988 00007025 */ move $t6, $zero
.L8003198C:
/* 03258C 8003198C 3C098012 */ lui $t1, %hi(D_8011D370) # $t1, 0x8012
/* 032590 80031990 3C088012 */ lui $t0, %hi(D_8011D378) # $t0, 0x8012
/* 032594 80031994 00007825 */ move $t7, $zero
/* 032598 80031998 8D29D370 */ lw $t1, %lo(D_8011D370)($t1)
/* 03259C 8003199C 8D08D378 */ lw $t0, %lo(D_8011D378)($t0)
.L800319A0:
/* 0325A0 800319A0 8D2A0000 */ lw $t2, ($t1)
/* 0325A4 800319A4 59400006 */ blezl $t2, .L800319C0
/* 0325A8 800319A8 95420000 */ lhu $v0, ($t2)
/* 0325AC 800319AC 3C0B8000 */ lui $t3, 0x8000
/* 0325B0 800319B0 016A5825 */ or $t3, $t3, $t2
/* 0325B4 800319B4 0800C6C6 */ j .L80031B18
/* 0325B8 800319B8 8D6B0018 */ lw $t3, 0x18($t3)
/* 0325BC 800319BC 95420000 */ lhu $v0, ($t2)
.L800319C0:
/* 0325C0 800319C0 C4A80000 */ lwc1 $f8, ($a1)
/* 0325C4 800319C4 C4AA0004 */ lwc1 $f10, 4($a1)
/* 0325C8 800319C8 00021100 */ sll $v0, $v0, 4
/* 0325CC 800319CC 004B1021 */ addu $v0, $v0, $t3
/* 0325D0 800319D0 C4400000 */ lwc1 $f0, ($v0)
/* 0325D4 800319D4 C4420004 */ lwc1 $f2, 4($v0)
/* 0325D8 800319D8 C4440008 */ lwc1 $f4, 8($v0)
/* 0325DC 800319DC 46004202 */ mul.s $f8, $f8, $f0
/* 0325E0 800319E0 C4B00008 */ lwc1 $f16, 8($a1)
/* 0325E4 800319E4 C446000C */ lwc1 $f6, 0xc($v0)
/* 0325E8 800319E8 46025282 */ mul.s $f10, $f10, $f2
/* 0325EC 800319EC 3C01800E */ lui $at, %hi(D_800E5F70) # $at, 0x800e
/* 0325F0 800319F0 46048402 */ mul.s $f16, $f16, $f4
/* 0325F4 800319F4 460A4200 */ add.s $f8, $f8, $f10
/* 0325F8 800319F8 46104200 */ add.s $f8, $f8, $f16
/* 0325FC 800319FC 46064480 */ add.s $f18, $f8, $f6
/* 032600 80031A00 C4C80000 */ lwc1 $f8, ($a2)
/* 032604 80031A04 46089481 */ sub.s $f18, $f18, $f8
/* 032608 80031A08 C4285F70 */ lwc1 $f8, %lo(D_800E5F70)($at)
/* 03260C 80031A0C 46089034 */ c.olt.s $f18, $f8
/* 032610 80031A10 45000041 */ bc1f .L80031B18
/* 032614 80031A14 3C014040 */ li $at, 0x40400000 # 3.000000
/* 032618 80031A18 44815000 */ mtc1 $at, $f10
/* 03261C 80031A1C C4C80000 */ lwc1 $f8, ($a2)
/* 032620 80031A20 460A4200 */ add.s $f8, $f8, $f10
/* 032624 80031A24 46004207 */ neg.s $f8, $f8
/* 032628 80031A28 46089036 */ c.ole.s $f18, $f8
/* 03262C 80031A2C 4501003A */ bc1t .L80031B18
/* 032630 80031A30 3C014080 */ li $at, 0x40800000 # 4.000000
/* 032634 80031A34 44815000 */ mtc1 $at, $f10
/* 032638 80031A38 C4A00000 */ lwc1 $f0, ($a1)
/* 03263C 80031A3C C4A20004 */ lwc1 $f2, 4($a1)
/* 032640 80031A40 C4A40008 */ lwc1 $f4, 8($a1)
/* 032644 80031A44 240C0003 */ li $t4, 3
.L80031A48:
/* 032648 80031A48 95430002 */ lhu $v1, 2($t2)
/* 03264C 80031A4C 0000C025 */ move $t8, $zero
/* 032650 80031A50 30798000 */ andi $t9, $v1, 0x8000
/* 032654 80031A54 53200004 */ beql $t9, $zero, .L80031A68
/* 032658 80031A58 00031900 */ sll $v1, $v1, 4
/* 03265C 80031A5C 30637FFF */ andi $v1, $v1, 0x7fff
/* 032660 80031A60 24180001 */ li $t8, 1
/* 032664 80031A64 00031900 */ sll $v1, $v1, 4
.L80031A68:
/* 032668 80031A68 006B1821 */ addu $v1, $v1, $t3
/* 03266C 80031A6C C4660000 */ lwc1 $f6, ($v1)
/* 032670 80031A70 C4680004 */ lwc1 $f8, 4($v1)
/* 032674 80031A74 46060182 */ mul.s $f6, $f0, $f6
/* 032678 80031A78 00000000 */ nop
/* 03267C 80031A7C 46081202 */ mul.s $f8, $f2, $f8
/* 032680 80031A80 46083180 */ add.s $f6, $f6, $f8
/* 032684 80031A84 C4680008 */ lwc1 $f8, 8($v1)
/* 032688 80031A88 46082202 */ mul.s $f8, $f4, $f8
/* 03268C 80031A8C 46083180 */ add.s $f6, $f6, $f8
/* 032690 80031A90 C468000C */ lwc1 $f8, 0xc($v1)
/* 032694 80031A94 13000002 */ beqz $t8, .L80031AA0
/* 032698 80031A98 46083180 */ add.s $f6, $f6, $f8
/* 03269C 80031A9C 46003187 */ neg.s $f6, $f6
.L80031AA0:
/* 0326A0 80031AA0 460A3036 */ c.ole.s $f6, $f10
/* 0326A4 80031AA4 4502001D */ bc1fl .L80031B1C
/* 0326A8 80031AA8 2508FFFF */ addiu $t0, $t0, -1
/* 0326AC 80031AAC 258CFFFF */ addiu $t4, $t4, -1
/* 0326B0 80031AB0 1580FFE5 */ bnez $t4, .L80031A48
/* 0326B4 80031AB4 254A0002 */ addiu $t2, $t2, 2
/* 0326B8 80031AB8 C4400000 */ lwc1 $f0, ($v0)
/* 0326BC 80031ABC C4420004 */ lwc1 $f2, 4($v0)
/* 0326C0 80031AC0 C4A60000 */ lwc1 $f6, ($a1)
/* 0326C4 80031AC4 46120002 */ mul.s $f0, $f0, $f18
/* 0326C8 80031AC8 C4440008 */ lwc1 $f4, 8($v0)
/* 0326CC 80031ACC 25CE0001 */ addiu $t6, $t6, 1
/* 0326D0 80031AD0 46121082 */ mul.s $f2, $f2, $f18
/* 0326D4 80031AD4 29C1000B */ slti $at, $t6, 0xb
/* 0326D8 80031AD8 240F0001 */ li $t7, 1
/* 0326DC 80031ADC 46122102 */ mul.s $f4, $f4, $f18
/* 0326E0 80031AE0 46003001 */ sub.s $f0, $f6, $f0
/* 0326E4 80031AE4 C4A60004 */ lwc1 $f6, 4($a1)
/* 0326E8 80031AE8 46023081 */ sub.s $f2, $f6, $f2
/* 0326EC 80031AEC C4A60008 */ lwc1 $f6, 8($a1)
/* 0326F0 80031AF0 14200005 */ bnez $at, .L80031B08
/* 0326F4 80031AF4 46043101 */ sub.s $f4, $f6, $f4
/* 0326F8 80031AF8 00007825 */ move $t7, $zero
/* 0326FC 80031AFC C4800000 */ lwc1 $f0, ($a0)
/* 032700 80031B00 C4820004 */ lwc1 $f2, 4($a0)
/* 032704 80031B04 C4840008 */ lwc1 $f4, 8($a0)
.L80031B08:
/* 032708 80031B08 E4A00000 */ swc1 $f0, ($a1)
/* 03270C 80031B0C E4A20004 */ swc1 $f2, 4($a1)
/* 032710 80031B10 0800C6C9 */ j .L80031B24
/* 032714 80031B14 E4A40008 */ swc1 $f4, 8($a1)
.L80031B18:
/* 032718 80031B18 2508FFFF */ addiu $t0, $t0, -1
.L80031B1C:
/* 03271C 80031B1C 1500FFA0 */ bnez $t0, .L800319A0
/* 032720 80031B20 25290004 */ addiu $t1, $t1, 4
.L80031B24:
/* 032724 80031B24 15E0FF99 */ bnez $t7, .L8003198C
/* 032728 80031B28 00000000 */ nop
/* 03272C 80031B2C 8FA80010 */ lw $t0, 0x10($sp)
/* 032730 80031B30 2484000C */ addiu $a0, $a0, 0xc
/* 032734 80031B34 24A5000C */ addiu $a1, $a1, 0xc
/* 032738 80031B38 2508FFFF */ addiu $t0, $t0, -1
/* 03273C 80031B3C 24C60004 */ addiu $a2, $a2, 4
/* 032740 80031B40 24E70001 */ addiu $a3, $a3, 1
/* 032744 80031B44 1500FEB6 */ bnez $t0, .L80031620
/* 032748 80031B48 AFA80010 */ sw $t0, 0x10($sp)
.L80031B4C:
/* 03274C 80031B4C 03E00008 */ jr $ra
/* 032750 80031B50 83A20000 */ lb $v0, ($sp)
/* 032754 80031B54 00000000 */ nop
/* 032758 80031B58 00000000 */ nop
/* 03275C 80031B5C 00000000 */ nop
asm/entrypoint.s
-35
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@@ -1,35 +0,0 @@
/* The comment below is needed for this file to be picked up by generate_ld */
/* RAM_POS: 0x80000400 */
.include "macros.inc"
.set noat # allow manual use of $at
.set noreorder # dont insert nops after branches
.set gp=64 # 64-bit instructions are used
.section .text
glabel entrypoint
.ent entrypoint
/* 001000 80000400 3C08800F */ lui $t0, %hi(gAudioHeapStack) # $t0, 0x800f
/* 001004 80000404 3C090004 */ lui $t1, %hi(__BSS_SECTION_SIZE) # lui $t1, 4
/* 001008 80000408 2508BF60 */ addiu $t0, %lo(gAudioHeapStack) # addiu $t0, $t0, -0x40a0
/* 00100C 8000040C 35291490 */ ori $t1, %lo(__BSS_SECTION_SIZE) # ori $t1, $t1, 0x1490
.L80000410:
/* 001010 80000410 2129FFF8 */ addi $t1, $t1, -8
/* 001014 80000414 AD000000 */ sw $zero, ($t0)
/* 001018 80000418 AD000004 */ sw $zero, 4($t0)
/* 00101C 8000041C 1520FFFC */ bnez $t1, .L80000410
/* 001020 80000420 21080008 */ addi $t0, $t0, 8
/* 001024 80000424 3C0A8006 */ lui $t2, %hi(mainproc) # $t2, 0x8006
/* 001028 80000428 3C1D8012 */ lui $sp, %hi(gCameraSegment) # $sp, 0x8012
/* 00102C 8000042C 254A5D40 */ addiu $t2, %lo(mainproc) # addiu $t2, $t2, 0x5d40
/* 001030 80000430 01400008 */ jr $t2
/* 001034 80000434 27BD0AC0 */ addiu $sp, %lo(gCameraSegment) # addiu $sp, $sp, 0xac0
/* 001038 80000438 00000000 */ nop
/* 00103C 8000043C 00000000 */ nop
/* 001040 80000440 00000000 */ nop
/* 001044 80000444 00000000 */ nop
/* 001048 80000448 00000000 */ nop
/* 00104C 8000044C 00000000 */ nop
.end entrypoint
asm/get_stack_pointer.s
-15
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@@ -1,15 +0,0 @@
/* The comment below is needed for this file to be picked up by generate_ld */
/* RAM_POS: 0x800B7D10 */
.section .text
.include "macros.inc"
.set noat # allow manual use of $at
.set noreorder # dont insert nops after branches
.set gp=64 # 64-bit instructions are used
glabel stack_pointer
jr $ra
move $v0, $sp
asm/gzip.s
-40
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@@ -1,40 +0,0 @@
/* The comment below is needed for this file to be picked up by generate_ld */
/* RAM_POS: 0x800C68C0 */
.include "macros.inc"
.set noat # allow manual use of $at
.set noreorder # dont insert nops after branches
.set gp=64 # 64-bit instructions are used
.section .text
.include "asm/gzip/gzip_inflate_block.s"
.include "asm/gzip/gzip_inflate_dynamic.s"
.include "asm/gzip/gzip_inflate_fixed.s"
.include "asm/gzip/gzip_inflate_stored.s"
.include "asm/gzip/gzip_inflate_codes.s"
.section .rodata
glabel gzip_border
.byte 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15
glabel gzip_cplens
.half 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0
glabel gzip_cplext
.byte 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99
glabel gzip_cpdist
.half 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, 8193, 12289, 16385, 24577
glabel gzip_cpdext
.byte 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13
glabel gzip_mask_bits
.half 0x0000, 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
# This might just be padding.
glabel D_800E94AE
.half 0x0000

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