Asm Formatting (#82)

* Replace STAY2 with per instruction macros

Co-authored-by: Tharo <17233964+Thar0@users.noreply.github.com>

* asm Formatting

Co-authored-by: Tharo <17233964+Thar0@users.noreply.github.com>

* Remove unused STAY macros

* space after comma for some asm args

---------

Co-authored-by: Tharo <17233964+Thar0@users.noreply.github.com>

include/sys/asm.h

@@ -83,22 +83,6 @@ extern "C" {
 #endif
 
 
-
-#define STAY1(stmnt)    \
-    .set noreorder     ;\
-        stmnt          ;\
-    .set reorder
-
-#define STAY2(stmnt, arg1)  \
-    .set noreorder         ;\
-        stmnt, arg1        ;\
-    .set reorder
-
-#define STAY3(stmnt, arg1, arg2)    \
-    .set noreorder                 ;\
-        stmnt, arg1, arg2          ;\
-    .set reorder
-
 #define NOP         \
     .set noreorder ;\
         nop        ;\
@@ -109,6 +93,27 @@ extern "C" {
         cache op, reg  ;\
     .set reorder
 
+#define MFC0(reg, op)  \
+    .set noreorder     ;\
+        mfc0 reg, op  ;\
+    .set reorder
+
+#define MTC0(reg, op)  \
+    .set noreorder     ;\
+        mtc0 reg, op  ;\
+    .set reorder
+
+#define CFC1(reg, op)  \
+    .set noreorder     ;\
+        cfc1 reg, op  ;\
+    .set reorder
+
+#define CTC1(reg, op)  \
+    .set noreorder     ;\
+        ctc1 reg, op  ;\
+    .set reorder
+
+
 #ifdef __cplusplus
 }
 #endif

src/error/errorasm.s

@@ -7,23 +7,23 @@
 
 LEAF(__osError)
 #if BUILD_VERSION < VERSION_J
-    lw      t0,__osErrorHandler
-    beqz    t0,1f
+    lw      t0, __osErrorHandler
+    beqz    t0, 1f
     jr      t0
 #elif BUILD_VERSION < VERSION_K
-    lw      t0,__kmc_pt_mode
-    bnez    t0,_kmc_mode
+    lw      t0, __kmc_pt_mode
+    bnez    t0, _kmc_mode
 
-    lw      t0,__osErrorHandler
-    beqz    t0,1f
+    lw      t0, __osErrorHandler
+    beqz    t0, 1f
     jr      t0
 _kmc_mode:
-    lw      t0,__kmcErrorHandler
-    beqz    t0,1f
+    lw      t0, __kmcErrorHandler
+    beqz    t0, 1f
     jr      t0
 #else
-    lw      t0,__osCommonHandler
-    beqz    t0,1f
+    lw      t0, __osCommonHandler
+    beqz    t0, 1f
     jr      t0
 #endif
 1:

src/libc/bcmp.s

@@ -9,88 +9,88 @@ WEAK(bcmp, _bcmp)
 #define _bcmp bcmp
 #endif
 LEAF(_bcmp)
-    xor v0, a0, a1
-    blt a2, 16, bytecmp
+    xor     v0, a0, a1
+    blt     a2, 16, bytecmp
 
-    andi v0, v0, 0x3
-    negu t8, a0
-    bnez v0, unalgncmp
+    andi    v0, v0, 0x3
+    negu    t8, a0
+    bnez    v0, unalgncmp
 
-    andi t8, t8, 0x3
-    subu a2, a2, t8
-    beqz t8, wordcmp
+    andi    t8, t8, 0x3
+    subu    a2, a2, t8
+    beqz    t8, wordcmp
     
-    move v0, v1
-    lwl v0, 0(a0)
-    lwl v1, 0(a1)
-    addu a0, a0, t8
-    addu a1, a1, t8
-    bne v0, v1, cmpne
+    move    v0, v1
+    lwl     v0, 0(a0)
+    lwl     v1, 0(a1)
+    addu    a0, a0, t8
+    addu    a1, a1, t8
+    bne     v0, v1, cmpne
 
 wordcmp:
-    and a3, a2, ~3
-    subu a2, a2, a3
-    beqz a3, bytecmp
+    and     a3, a2, ~3
+    subu    a2, a2, a3
+    beqz    a3, bytecmp
 
-    addu a3, a3, a0
+    addu    a3, a3, a0
 1:
-    lw v0, 0(a0)
-    lw v1, 0(a1)
-    addiu a0, a0, 4
-    addiu a1, a1, 4
-    bne v0, v1, cmpne
-    bne a0, a3, 1b
+    lw      v0, 0(a0)
+    lw      v1, 0(a1)
+    addiu   a0, a0, 4
+    addiu   a1, a1, 4
+    bne     v0, v1, cmpne
+    bne     a0, a3, 1b
 
-    b bytecmp
+    b       bytecmp
 unalgncmp:
-    negu a3, a1
-    andi a3, a3, 0x3
-    subu a2, a2, a3
-    beqz a3, partaligncmp
+    negu    a3, a1
+    andi    a3, a3, 0x3
+    subu    a2, a2, a3
+    beqz    a3, partaligncmp
+
+    addu    a3, a3, a0
 
-    addu a3, a3, a0
-    
 1:
-    lbu v0, 0(a0)
-    lbu v1, 0(a1)
-    addiu a0, a0, 1
-    addiu a1, a1, 1
-    bne v0, v1, cmpne
-    bne a0, a3, 1b 
+    lbu     v0, 0(a0)
+    lbu     v1, 0(a1)
+    addiu   a0, a0, 1
+    addiu   a1, a1, 1
+    bne     v0, v1, cmpne
+    bne     a0, a3, 1b 
 
 partaligncmp:
-    and a3, a2, ~3
-    subu a2, a2, a3
-    beqz a3, bytecmp
+    and     a3, a2, ~3
+    subu    a2, a2, a3
+    beqz    a3, bytecmp
 
-    addu a3, a3, a0
+    addu    a3, a3, a0
     
 1:
-    lwl v0, 0(a0)
-    lwr v0, 3(a0)
-    lw v1, 0(a1)
-    addiu a0, a0, 4
-    addiu a1, a1, 4
-    bne v0, v1, cmpne
-    bne a0, a3, 1b 
+    lwl     v0, 0(a0)
+    lwr     v0, 3(a0)
+    lw      v1, 0(a1)
+    addiu   a0, a0, 4
+    addiu   a1, a1, 4
+    bne     v0, v1, cmpne
+    bne     a0, a3, 1b 
     
 bytecmp:
-    addu a3, a2, a0
-    blez a2, cmpdone
+    addu    a3, a2, a0
+    blez    a2, cmpdone
 
 1:
-    lbu v0, 0(a0)
-    lbu v1, 0(a1)
-    addiu a0, a0, 1
-    addiu a1, a1, 1
-    bne v0, v1, cmpne
-    bne a0, a3, 1b 
+    lbu     v0, 0(a0)
+    lbu     v1, 0(a1)
+    addiu   a0, a0, 1
+    addiu   a1, a1, 1
+    bne     v0, v1, cmpne
+    bne     a0, a3, 1b 
 
 cmpdone:
-    move v0, zero
-    jr ra
+    move    v0, zero
+    jr      ra
 cmpne:
-    li v0, 1
-    jr ra
+    li      v0, 1
+    jr      ra
 
 .end _bcmp

src/libc/bcopy.s

@@ -9,212 +9,212 @@ WEAK(bcopy, _bcopy)
 #define _bcopy bcopy
 #endif
 LEAF(_bcopy)
-    move a3, a1
-    beqz a2, ret
-    beq a0, a1, ret
-    blt a1, a0, goforwards
+    move    a3, a1
+    beqz    a2, ret
+    beq     a0, a1, ret
+    blt     a1, a0, goforwards
     
-    add v0, a0, a2
-    bge a1, v0, goforwards
-    b gobackwards
+    add     v0, a0, a2
+    bge     a1, v0, goforwards
+    b       gobackwards
 
 goforwards:
 
-    blt a2, 16, forwards_bytecopy
+    blt     a2, 16, forwards_bytecopy
     
-    andi v0, a0, 0x3
-    andi v1, a1, 0x3
-    beq v0, v1,forwalignable
+    andi    v0, a0, 0x3
+    andi    v1, a1, 0x3
+    beq     v0, v1, forwalignable
     
 
 forwards_bytecopy:
-    beqz a2, ret
-    addu v1, a0, a2
+    beqz    a2, ret
+    addu    v1, a0, a2
 99:
-    lb v0, 0(a0)
-    addiu a0, a0, 1
-    sb v0, 0(a1)
-    addiu a1, a1, 1
-    bne a0, v1, 99b
+    lb      v0, 0(a0)
+    addiu   a0, a0, 1
+    sb      v0, 0(a1)
+    addiu   a1, a1, 1
+    bne     a0, v1, 99b
 ret:
-    move v0, a3
-    jr ra
+    move    v0, a3
+    jr      ra
 
 forwalignable:
-    beqz v0, forwards
-    beq v0, 1, forw_copy3
-    beq v0, 2, forw_copy2
+    beqz    v0, forwards
+    beq     v0, 1, forw_copy3
+    beq     v0, 2, forw_copy2
 
-    lb v0, 0(a0)
-    addiu a0, a0, 1
-    sb v0, 0(a1)
-    addiu a1, a1, 1
-    addiu a2, a2, -1
-    b forwards
+    lb      v0, 0(a0)
+    addiu   a0, a0, 1
+    sb      v0, 0(a1)
+    addiu   a1, a1, 1
+    addiu   a2, a2, -1
+    b       forwards
 
 forw_copy2:
-    lh v0, 0(a0)
-    addiu a0, a0, 2
-    sh v0, 0(a1)
-    addiu a1, a1, 2
-    addiu a2, a2, -2
-    b forwards
+    lh      v0, 0(a0)
+    addiu   a0, a0, 2
+    sh      v0, 0(a1)
+    addiu   a1, a1, 2
+    addiu   a2, a2, -2
+    b       forwards
 
 forw_copy3:
-    lb v0, 0(a0)
-    lh v1, 1(a0)
-    addiu a0, a0, 3
-    sb v0, 0(a1)
-    sh v1, 1(a1)
-    addiu a1, a1, 3
-    addiu a2, a2, -3
+    lb      v0, 0(a0)
+    lh      v1, 1(a0)
+    addiu   a0, a0, 3
+    sb      v0, 0(a1)
+    sh      v1, 1(a1)
+    addiu   a1, a1, 3
+    addiu   a2, a2, -3
 
 forwards:
 forwards_32:
-    blt a2, 32, forwards_16
-    lw v0, 0(a0)
-    lw v1, 4(a0)
-    lw t0, 8(a0)
-    lw t1, 12(a0)
-    lw t2, 16(a0)
-    lw t3, 20(a0)
-    lw ta0, 24(a0)
-    lw ta1, 28(a0)
-    addiu a0, a0, 32
-    sw v0, 0(a1)
-    sw v1, 4(a1)
-    sw t0, 8(a1)
-    sw t1, 12(a1)
-    sw t2, 16(a1)
-    sw t3, 20(a1)
-    sw ta0, 24(a1)
-    sw ta1, 28(a1)
-    addiu a1, a1, 32
-    addiu a2, a2, -32
-    b forwards_32
+    blt     a2, 32, forwards_16
+    lw      v0, 0(a0)
+    lw      v1, 4(a0)
+    lw      t0, 8(a0)
+    lw      t1, 12(a0)
+    lw      t2, 16(a0)
+    lw      t3, 20(a0)
+    lw      ta0, 24(a0)
+    lw      ta1, 28(a0)
+    addiu   a0, a0, 32
+    sw      v0, 0(a1)
+    sw      v1, 4(a1)
+    sw      t0, 8(a1)
+    sw      t1, 12(a1)
+    sw      t2, 16(a1)
+    sw      t3, 20(a1)
+    sw      ta0, 24(a1)
+    sw      ta1, 28(a1)
+    addiu   a1, a1, 32
+    addiu   a2, a2, -32
+    b       forwards_32
 
 forwards_16:
-    blt a2, 16, forwards_4
-    lw v0, 0(a0)
-    lw v1, 4(a0)
-    lw t0, 8(a0)
-    lw t1, 12(a0)
-    addiu a0, a0, 16
-    sw v0, 0(a1)
-    sw v1, 4(a1)
-    sw t0, 8(a1)
-    sw t1, 12(a1)
-    addiu a1, a1, 16
-    addiu a2, a2, -16
-    b forwards_16
+    blt     a2, 16, forwards_4
+    lw      v0, 0(a0)
+    lw      v1, 4(a0)
+    lw      t0, 8(a0)
+    lw      t1, 12(a0)
+    addiu   a0, a0, 16
+    sw      v0, 0(a1)
+    sw      v1, 4(a1)
+    sw      t0, 8(a1)
+    sw      t1, 12(a1)
+    addiu   a1, a1, 16
+    addiu   a2, a2, -16
+    b       forwards_16
 
 forwards_4:
-    blt a2, 4, forwards_bytecopy
+    blt     a2, 4, forwards_bytecopy
     
-    lw v0, 0(a0)
-    addiu a0, a0, 4
-    sw v0, 0(a1)
-    addiu a1, a1, 4
-    addiu a2, a2, -4
-    b forwards_4
+    lw      v0, 0(a0)
+    addiu   a0, a0, 4
+    sw      v0, 0(a1)
+    addiu   a1, a1, 4
+    addiu   a2, a2, -4
+    b       forwards_4
     
 gobackwards:
-    add a0, a0,a2
-    add a1, a1,a2
-    blt a2, 16, backwards_bytecopy
+    add     a0, a0, a2
+    add     a1, a1, a2
+    blt     a2, 16, backwards_bytecopy
 
-    andi v0, a0, 0x3
-    andi v1, a1, 0x3
-    beq v0, v1,backalignable
+    andi    v0, a0, 0x3
+    andi    v1, a1, 0x3
+    beq     v0, v1, backalignable
     
 backwards_bytecopy:
-    beqz a2, ret
-    addiu a0, a0, -1
-    addiu a1, a1, -1
-    subu v1, a0,a2
+    beqz    a2, ret
+    addiu   a0, a0, -1
+    addiu   a1, a1, -1
+    subu    v1, a0, a2
 99:
-    lb v0, 0(a0)
-    addiu a0, a0, -1
-    sb v0, 0(a1)
-    addiu a1, a1, -1
-    bne a0, v1,99b
+    lb      v0, 0(a0)
+    addiu   a0, a0, -1
+    sb      v0, 0(a1)
+    addiu   a1, a1, -1
+    bne     a0, v1, 99b
 
-    move v0, a3
-    jr ra
+    move    v0, a3
+    jr      ra
 backalignable:
-    beqz v0, backwards
-    beq v0, 3, back_copy3
-    beq v0, 2, back_copy2
-    lb v0, -1(a0)
-    addiu a0, a0, -1
-    sb v0, -1(a1)
-    addiu a1, a1, -1
-    addiu a2, a2, -1
+    beqz    v0, backwards
+    beq     v0, 3, back_copy3
+    beq     v0, 2, back_copy2
+    lb      v0, -1(a0)
+    addiu   a0, a0, -1
+    sb      v0, -1(a1)
+    addiu   a1, a1, -1
+    addiu   a2, a2, -1
     b backwards
 
 back_copy2:
-    lh v0, -2(a0)
-    addiu a0, a0, -2
-    sh v0, -2(a1)
-    addiu a1, a1, -2
-    addiu a2, a2, -2
-    b backwards
+    lh      v0, -2(a0)
+    addiu   a0, a0, -2
+    sh      v0, -2(a1)
+    addiu   a1, a1, -2
+    addiu   a2, a2, -2
+    b       backwards
 
 back_copy3:
-    lb v0, -1(a0)
-    lh v1, -3(a0)
-    addiu a0, a0, -3
-    sb v0, -1(a1)
-    sh v1, -3(a1)
-    addiu a1, a1, -3
-    addiu a2, a2, -3
+    lb      v0, -1(a0)
+    lh      v1, -3(a0)
+    addiu   a0, a0, -3
+    sb      v0, -1(a1)
+    sh      v1, -3(a1)
+    addiu   a1, a1, -3
+    addiu   a2, a2, -3
 
 backwards:
 backwards_32:
-    blt a2, 32, backwards_16
-    lw v0, -4(a0)
-    lw v1, -8(a0)
-    lw t0, -12(a0)
-    lw t1, -16(a0)
-    lw t2, -20(a0)
-    lw t3, -24(a0)
-    lw ta0, -28(a0)
-    lw ta1, -32(a0)
-    addiu a0, a0, -32
-    sw v0, -4(a1)
-    sw v1, -8(a1)
-    sw t0, -12(a1)
-    sw t1, -16(a1)
-    sw t2, -20(a1)
-    sw t3, -24(a1)
-    sw ta0, -28(a1)
-    sw ta1, -32(a1)
-    addiu a1, a1, -32
-    addiu a2, a2, -32
-    b backwards_32
+    blt     a2, 32, backwards_16
+    lw      v0, -4(a0)
+    lw      v1, -8(a0)
+    lw      t0, -12(a0)
+    lw      t1, -16(a0)
+    lw      t2, -20(a0)
+    lw      t3, -24(a0)
+    lw      ta0, -28(a0)
+    lw      ta1, -32(a0)
+    addiu   a0, a0, -32
+    sw      v0, -4(a1)
+    sw      v1, -8(a1)
+    sw      t0, -12(a1)
+    sw      t1, -16(a1)
+    sw      t2, -20(a1)
+    sw      t3, -24(a1)
+    sw      ta0, -28(a1)
+    sw      ta1, -32(a1)
+    addiu   a1, a1, -32
+    addiu   a2, a2, -32
+    b       backwards_32
 
 backwards_16:
-    blt a2, 16, backwards_4
-    lw v0, -4(a0)
-    lw v1, -8(a0)
-    lw t0, -12(a0)
-    lw t1, -16(a0)
-    addiu a0, a0, -16
-    sw v0, -4(a1)
-    sw v1, -8(a1)
-    sw t0, -12(a1)
-    sw t1, -16(a1)
-    addiu a1, a1, -16
-    addiu a2, a2, -16
-    b backwards_16
+    blt     a2, 16, backwards_4
+    lw      v0, -4(a0)
+    lw      v1, -8(a0)
+    lw      t0, -12(a0)
+    lw      t1, -16(a0)
+    addiu   a0, a0, -16
+    sw      v0, -4(a1)
+    sw      v1, -8(a1)
+    sw      t0, -12(a1)
+    sw      t1, -16(a1)
+    addiu   a1, a1, -16
+    addiu   a2, a2, -16
+    b       backwards_16
 
 backwards_4:
-    blt a2, 4, backwards_bytecopy
-    lw v0, -4(a0)
-    addiu a0, a0, -4
-    sw v0, -4(a1)
-    addiu a1, a1, -4
-    addiu a2, a2, -4
-    b backwards_4
+    blt     a2, 4, backwards_bytecopy
+    lw      v0, -4(a0)
+    addiu   a0, a0, -4
+    sw      v0, -4(a1)
+    addiu   a1, a1, -4
+    addiu   a2, a2, -4
+    b       backwards_4
 
 .end _bcopy

src/libc/bzero.s

@@ -12,61 +12,61 @@ WEAK(blkclr, _blkclr)
 #endif
 LEAF(_bzero)
 XLEAF(_blkclr)
-    negu v1, a0
-    blt a1, 12, bytezero
+    negu    v1, a0
+    blt     a1, 12, bytezero
 
-    andi v1, v1, 0x3
-    subu a1, a1, v1
+    andi    v1, v1, 0x3
+    subu    a1, a1, v1
 
-    beqz v1, blkzero
-    swl zero, 0(a0)
-    addu a0, a0, v1
+    beqz    v1, blkzero
+    swl     zero, 0(a0)
+    addu    a0, a0, v1
 blkzero:
     /* align backwards to 0x20 */
-    and a3, a1, ~31
-    subu a1, a1, a3
+    and     a3, a1, ~31
+    subu    a1, a1, a3
     /* If the result is zero, the amount to zero is less than 0x20 bytes */
-    beqz a3, wordzero
+    beqz    a3, wordzero
 
     /* zero in blocks of 0x20 at a time */
-    addu a3, a3, a0
+    addu    a3, a3, a0
 1:
-    sw zero, 0(a0)
-    sw zero, 4(a0)
-    sw zero, 8(a0)
-    sw zero, 12(a0)
-    addiu a0, a0, 32
-    sw zero, -16(a0)
-    sw zero, -12(a0)
-    sw zero, -8(a0)
-    sw zero, -4(a0)
-    bne a0, a3, 1b
+    sw      zero, 0(a0)
+    sw      zero, 4(a0)
+    sw      zero, 8(a0)
+    sw      zero, 12(a0)
+    addiu   a0, a0, 32
+    sw      zero, -16(a0)
+    sw      zero, -12(a0)
+    sw      zero, -8(a0)
+    sw      zero, -4(a0)
+    bne     a0, a3, 1b
 
 wordzero:
     /* align backwards to 0x4 */
-    and a3, a1, ~3
-    subu a1, a1, a3
+    and     a3, a1, ~3
+    subu    a1, a1, a3
     /* If the result is zero, the amount to zero is less than 0x4 bytes */
-    beqz a3, bytezero
+    beqz    a3, bytezero
 
     /* zero one word at a time */
-    addu a3, a3, a0
+    addu    a3, a3, a0
 1:
-    addiu a0, a0, 4
-    sw zero, -4(a0)
-    bne a0, a3, 1b
+    addiu   a0, a0, 4
+    sw      zero, -4(a0)
+    bne     a0, a3, 1b
 
 bytezero:
     /* test if nothing left to zero */
-    blez a1, zerodone
-    #nop
+    blez    a1, zerodone
+
     /* zero one byte at a time */
-    addu a1, a1, a0
+    addu    a1, a1, a0
 1:
-    addiu a0, a0, 1
-    sb zero, -1(a0)
-    bne a0, a1, 1b
+    addiu   a0, a0, 1
+    sb      zero, -1(a0)
+    bne     a0, a1, 1b
 zerodone:
-    jr ra
+    jr      ra
 
 .end _bzero

src/log/delay.s

@@ -5,16 +5,16 @@
 #include "sys/regdef.h"
 
 LEAF(osDelay)
-    sll     t0,a0,2
-    addu    t0,a0  
-    sll     t0,t0,2
-    beqz    a0,2f
+    sll     t0, a0, 2
+    addu    t0, a0  
+    sll     t0, t0, 2
+    beqz    a0, 2f
 
 1:
-    subu    t0,1
+    subu    t0, 1
     NOP
     NOP
-    bnez    t0,1b
+    bnez    t0, 1b
 
 2:
     j   ra

src/os/exceptasm.s

@@ -187,11 +187,11 @@ LEAF(__osException)
     sd      $1, THREAD_GP1(k0);
 .set at
     /* Save SR */
-STAY2(mfc0  k1, C0_SR)
+    MFC0(   k1, C0_SR)
     sw      k1, THREAD_SR(k0)
     /* Disable interrupts */
     and     k1, k1, ~(SR_IE | SR_EXL)
-STAY2(mtc0  k1, C0_SR)
+    MTC0(   k1, C0_SR)
     /* Save some temp registers for use in the following */
     sd      $8, THREAD_GP8(k0)
     sd      $9, THREAD_GP9(k0)
@@ -199,7 +199,7 @@ STAY2(mtc0  k1, C0_SR)
     /* Mark FPU as unused */
     sw      zero, THREAD_FP(k0)
     /* This instruction is useless, leftover because of bad placement of an ifdef for the debug version */
-STAY2(mfc0  t0, C0_CAUSE)
+    MFC0(   t0, C0_CAUSE)
 #ifndef _FINALROM
     lw      t2, __kmc_pt_mode
     bnez    t2, skip_kmc_mode
@@ -213,7 +213,7 @@ STAY2(mfc0  t0, C0_CAUSE)
     la      t1, RDB_WRITE_INTR_REG
     sw      zero, (t1)
 IP7check:
-STAY2(mfc0  t0, C0_CAUSE)
+    MFC0(   t0, C0_CAUSE)
     andi    t0, t0, CAUSE_IP7
     bne     zero, t0, IP7check
     la      t2, RDB_BASE_REG
@@ -370,7 +370,7 @@ notIP7:
 5:
     sw      t1, __osRdb_IP6_CurSend
 checkIP6:
-STAY2(mfc0  t0, C0_CAUSE)
+    MFC0(   t0, C0_CAUSE)
     andi    t0, t0, CAUSE_IP6
     bne     zero, t0, checkIP6
     la      t0, RDB_BASE_REG
@@ -383,7 +383,7 @@ rdbout:
     ld      $1, THREAD_GP1(k0)
 .set at
     lw      k1, THREAD_SR(k0)
-STAY2(mtc0  k1, C0_SR)
+    MTC0(   k1, C0_SR)
 .set noreorder
     nop
     nop
@@ -487,12 +487,12 @@ savercp:
     or      t1, t1, t0
 endrcp:
     sw      t1, THREAD_RCP(k0)
-STAY2(mfc0  t0, C0_EPC)
+    MFC0(   t0, C0_EPC)
     sw      t0, THREAD_PC(k0)
     lw      t0, THREAD_FP(k0)
     beqz    t0, 1f
     /* Save FP Registers if FPU was used by the thread */
-STAY2(cfc1  t0, fcr31)
+    CFC1(   t0, fcr31)
     NOP
     sw      t0, THREAD_FPCSR(k0)
     sdc1    $f0, THREAD_FP0(k0)
@@ -516,7 +516,7 @@ STAY2(cfc1  t0, fcr31)
      * Determine the cause of the exception or interrupt and
      *  enter appropriate handling routine
      */
-STAY2(mfc0  t0, C0_CAUSE)
+    MFC0(   t0, C0_CAUSE)
     sw      t0, THREAD_CAUSE(k0)
 
 .set noreorder
@@ -595,8 +595,8 @@ IP7_Hdlr:
  *  cop0 compare register, this interrupt is triggered
  */
 counter:
-STAY2(mfc0  t1, C0_COMPARE)
-STAY2(mtc0  t1, C0_COMPARE)
+    MFC0(   t1, C0_COMPARE)
+    MTC0(   t1, C0_COMPARE)
     li      a0, MESG(OS_EVENT_COUNTER)
     /* Post counter message */
     jal     send_mesg
@@ -878,7 +878,7 @@ firstnmi:
 sw2:
     /* Mask out interrupt */
     and     t0, t0, ~CAUSE_SW2
-STAY2(mtc0  t0, C0_CAUSE)
+    MTC0(   t0, C0_CAUSE)
 
     /* Post sw2 event message */
     li      a0, MESG(OS_EVENT_SW2)
@@ -891,7 +891,7 @@ STAY2(mtc0  t0, C0_CAUSE)
 sw1:
     /* Mask out interrupt */
     and     t0, t0, ~CAUSE_SW1
-STAY2(mtc0  t0, C0_CAUSE)
+    MTC0(   t0, C0_CAUSE)
 
     /* Post sw1 event message */
     li      a0, MESG(OS_EVENT_SW1)
@@ -956,7 +956,7 @@ panic:
     sh      t1, THREAD_FLAGS(k0)
 
     /* Save C0_BADVADDR */
-STAY2(mfc0  t2, C0_BADVADDR)
+    MFC0(   t2, C0_BADVADDR)
 
     sw      t2, THREAD_BADVADDR(k0)
 
@@ -1058,7 +1058,7 @@ LEAF(__osEnqueueAndYield)
     sw      a1, __osPreviousThread
 #endif
     /* Save SR */
-STAY2(mfc0  t0, C0_SR)
+    MFC0(   t0, C0_SR)
     ori     t0, t0, SR_EXL
     sw      t0, THREAD_SR(a1)
 
@@ -1229,7 +1229,7 @@ __osDispatchThreadSave:
     and     t1, t1, t0
     and     k1, k1, ~SR_IMASK
     or      k1, k1, t1
-STAY2(mtc0  k1, C0_SR)
+    MTC0(   k1, C0_SR)
 /* Restore GPRs */
 .set noat
     ld      $1, THREAD_GP1(k0)
@@ -1268,14 +1268,14 @@ STAY2(mtc0  k1, C0_SR)
     mthi    k1
     /* Move thread pc to EPC so that eret will return execution to where the thread left off */
     lw      k1, THREAD_PC(k0)
-STAY2(mtc0  k1, C0_EPC)
+    MTC0(   k1, C0_EPC)
 
     /* Check if the FPU was used by this thread and if so also restore the FPU registers */
     lw      k1, THREAD_FP(k0)
     beqz    k1, 1f
 
     lw      k1, THREAD_FPCSR(k0)
-STAY2(ctc1  k1, fcr31)
+    CTC1(   k1, fcr31)
     ldc1    $f0, THREAD_FP0(k0)
     ldc1    $f2, THREAD_FP2(k0)
     ldc1    $f4, THREAD_FP4(k0)

src/os/getcause.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetCause)
-    STAY2(mfc0 v0, C0_CAUSE)
-    jr ra
+    MFC0(   v0, C0_CAUSE)
+    jr      ra
 END(__osGetCause)

src/os/getcompare.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetCompare)
-    STAY2(mfc0 v0, C0_COMPARE)
-    jr ra
+    MFC0(   v0, C0_COMPARE)
+    jr      ra
 END(__osGetCompare)

src/os/getconfig.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetConfig)
-    STAY2(mfc0 v0, C0_CONFIG)
-    jr ra
+    MFC0(   v0, C0_CONFIG)
+    jr      ra
 END(__osGetConfig)

src/os/getcount.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(osGetCount)
-    STAY2(mfc0 v0, C0_COUNT)
-    jr ra
+    MFC0(   v0, C0_COUNT)
+    jr      ra
 END(osGetCount)

src/os/getfpccsr.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetFpcCsr)
-    STAY2(cfc1 v0, fcr31)
-    jr ra
+    CFC1(   v0, fcr31)
+    jr      ra
 END(__osGetSR) # @bug: Should be __osGetFpcCsr

src/os/getintmask.s

@@ -7,27 +7,26 @@
 .text
 .set noreorder
 LEAF(osGetIntMask)
-    mfc0 v0, C0_SR
-    andi v0, v0, OS_IM_CPU
-    la t0, __OSGlobalIntMask
-    lw t1, 0(t0)
-    xor t0, t1, -1
-    andi t0, t0, SR_IMASK
-    or v0, v0, t0
+    mfc0    v0, C0_SR
+    andi    v0, v0, OS_IM_CPU
+    la      t0, __OSGlobalIntMask
+    lw      t1, 0(t0)
+    xor     t0, t1, -1
+    andi    t0, t0, SR_IMASK
+    or      v0, v0, t0
 
-    lw t1, PHYS_TO_K1(MI_INTR_MASK_REG)
-    beqz t1, 1f
+    lw      t1, PHYS_TO_K1(MI_INTR_MASK_REG)
+    beqz    t1, 1f
+     la      t0, __OSGlobalIntMask # this is intentionally a macro in the branch delay slot
 
-    la t0, __OSGlobalIntMask # this is intentionally a macro in the branch delay slot
-
-    lw t0, 0(t0)
-    srl t0, t0, 0x10
-    xor t0, t0, -1
-    andi t0, t0, 0x3f
-    or t1, t1, t0
+    lw      t0, 0(t0)
+    srl     t0, t0, 0x10
+    xor     t0, t0, -1
+    andi    t0, t0, 0x3f
+    or      t1, t1, t0
 1:
-    sll t2, t1, 0x10
-    or v0, v0, t2
-    jr ra
-    nop
+    sll     t2, t1, 0x10
+    or      v0, v0, t2
+    jr      ra
+     nop
 END(osGetIntMask)

src/os/getsr.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetSR)
-    STAY2(mfc0 v0, C0_SR)
-    jr ra
+    MFC0(   v0, C0_SR)
+    jr      ra
 END(__osGetSR)

src/os/gettlbasid.s

@@ -5,7 +5,7 @@
 .set noreorder
 .text
 LEAF(__osGetTLBASID)
-    mfc0 v0, C0_ENTRYHI
-    jr ra
-    nop
+    mfc0    v0, C0_ENTRYHI
+    jr      ra
+     nop
 END(__osGetTLBASID)

src/os/gettlbhi.s

@@ -5,13 +5,13 @@
 .set noreorder
 .text
 LEAF(__osGetTLBHi)
-    mtc0 a0, C0_INX
+    mtc0    a0, C0_INX
     nop
     tlbr
     nop
     nop
     nop
-    mfc0 v0, C0_ENTRYHI
-    jr ra
-    nop
+    mfc0    v0, C0_ENTRYHI
+    jr      ra
+     nop
 END(__osGetTLBHi)

src/os/gettlblo0.s

@@ -5,13 +5,13 @@
 .set noreorder
 .text
 LEAF(__osGetTLBLo0)
-    mtc0 a0, C0_INX
+    mtc0    a0, C0_INX
     nop
     tlbr
     nop
     nop
     nop
-    mfc0 v0, C0_ENTRYLO0
-    jr ra
-    nop
+    mfc0    v0, C0_ENTRYLO0
+    jr      ra
+     nop
 END(__osGetTLBLo0)

src/os/gettlblo1.s

@@ -5,13 +5,13 @@
 .set noreorder
 .text
 LEAF(__osGetTLBLo1)
-    mtc0 a0, C0_INX
+    mtc0    a0, C0_INX
     nop
     tlbr
     nop
     nop
     nop
-    mfc0 v0, C0_ENTRYLO1
-    jr ra
-    nop
+    mfc0    v0, C0_ENTRYLO1
+    jr      ra
+     nop
 END(__osGetTLBLo1)

src/os/gettlbpagemask.s

@@ -5,13 +5,13 @@
 .set noreorder
 .text
 LEAF(__osGetTLBPageMask)
-    mtc0 a0, C0_INX
+    mtc0    a0, C0_INX
     nop
     tlbr
     nop
     nop
     nop
-    mfc0 v0, C0_PAGEMASK
-    jr ra
-    nop
+    mfc0    v0, C0_PAGEMASK
+    jr      ra
+     nop
 END(__osGetTLBPageMask)

src/os/getwatchlo.s

@@ -4,6 +4,6 @@
 
 .text
 LEAF(__osGetWatchLo)
-    STAY2(mfc0 v0, C0_WATCHLO)
-    jr ra
+    MFC0(   v0, C0_WATCHLO)
+    jr      ra
 END(__osGetWatchLo)